CN201708773U - Arbitrarywaveform generator - Google Patents
Arbitrarywaveform generator Download PDFInfo
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- CN201708773U CN201708773U CN2010202079814U CN201020207981U CN201708773U CN 201708773 U CN201708773 U CN 201708773U CN 2010202079814 U CN2010202079814 U CN 2010202079814U CN 201020207981 U CN201020207981 U CN 201020207981U CN 201708773 U CN201708773 U CN 201708773U
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Abstract
The utility model discloses an arbitrary waveform generator, comprising an upper computer, a USB controller, a data storage, a digital-to-analog converter and a programmable controller, wherein the upper computer is used for generating waveform data; the USB controller is connected with the upper computer and receives the waveform data by a USB interface; the data storage is connected with the USB controller and is used for storing the waveform data; the digital-to-analog converter is connected with the data storage and is used for converting digital signals into analog signals; and the programmable controller is connected with the USB controller, the data storage, the digital-to-analog converter and an analog signal output circuit and is used for controlling receiving, storage, digital-to-analog conversion and outputting of the waveform data. The arbitrary waveform generator has the advantages of higher real-time performance, accuracy and flexibility.
Description
[technical field]
The utility model relates to electronic equipment, particularly a kind of AWG (Arbitrary Waveform Generator) based on FPGA (Field-Programmable Gate Array) and USB (Universal Serial BUS) technology.
[background technology]
At corrosion and electroplating industry, usually need to use the current and voltage signals of random waveform to produce and test.Random waveform is meant changeable frequency, and amplitude is variable, the sinusoidal waveform of phase variable and other waveforms, and as triangular waveform, sawtooth waveforms, special waveform etc.AWG (Arbitrary Waveform Generator) adopts Direct Digital frequency synthesis (Direct Digital Synthesizer mostly at present, DDS) technology, the digital quantity signal that is about to waveform is stored in the memory, embedded host sends to digital to analog converter with the Wave data in the memory cell successively one by one with certain speed, synthesizes the waveform that needs.
Along with the increasingly extensive application of microprocessor and the development of large scale integrated circuit technology, the AWG (Arbitrary Waveform Generator) of multiple waveform and stable performance has appearred can producing in a large number, but most variations all is based on the transmission that the serial or parallel bus is carried out data, though this scheme cost is lower, but the real-time of system is relatively poor, is difficult to satisfy the transmission requirement of the big data quantity of complicated wave form.
[utility model content]
In order to solve the technical problem of prior art, be necessary to provide the AWG (Arbitrary Waveform Generator) that a kind of real-time is good, precision is high.
The technical scheme that the existing technical problem that solves the utility model adopts is: a kind of AWG (Arbitrary Waveform Generator), and it comprises the host computer that is used to produce Wave data, the USB controller that is connected and receives Wave data with host computer by USB interface, the data storage that is used for the stored waveform data that is connected with the USB controller, be connected with data storage be used for digital signal be converted to analog signal digital to analog converter and with described USB controller, data storage, digital to analog converter is connected with the analog signal output circuit is used for the control waveform Data Receiving, the Programmable Logic Controller of storage and digital-to-analogue conversion and output.
In the utility model AWG (Arbitrary Waveform Generator), the interface chip that described USB controller adopts is USB2.0 interface chip CY7C68013AE.
In the utility model AWG (Arbitrary Waveform Generator), described Programmable Logic Controller connects EEPROM (Electrically Erasable Programmable Read Only Memo) and active crystal oscillator.
In the utility model AWG (Arbitrary Waveform Generator), described programmable processor comprises USB control unit, modulus control unit, output control unit, FPGA overall logic control chip, I2C controller, internal clocking lock unit and internal clocking unit, described USB control unit connects described USB controller, described modulus control unit connects described data storage and digital to analog converter simultaneously, described output control unit connects described analog signal output circuit, and described I2C controller connects outside EEPROM.Described internal clocking unit connects the external active crystal oscillator.
In the utility model AWG (Arbitrary Waveform Generator), described data storage comprises pin-saving chip SRAM, and it adopts the IS61LV25616-10T of ISSI company.
In the utility model AWG (Arbitrary Waveform Generator), described Programmable Logic Controller comprises that Cyclone II serial model No. is the FPGA control chip of EP2C20F484.
Compared to prior art, a kind of AWG (Arbitrary Waveform Generator) of the utility model, made full use of the powerful logic function of Programmable Logic Controller, realized utilizing the scheme of monolithic fpga chip control whole system, it adopts the USB interface of USB controller to carry out the Wave data transmission, can be preferably and the fpga chip cooperation, the function that the system that finishes designs in advance, make overall circuit simple, with low cost, the waveform signal precision of generation is higher.Digital waveform data directly is stored in the data storage by usb bus from host computer, by the control of Programmable Logic Controller Wave data is read, and sends into digital to analog converter and carries out obtaining required analog signal waveform after digital-to-analogue conversion and the processing and amplifying.Compare in the method for ROM or FLASH stored waveform data with traditional waveform generator, have bigger flexibility.
[description of drawings]
Fig. 1 is the framework schematic diagram of the utility model AWG (Arbitrary Waveform Generator) one better embodiment.
Fig. 2 is Programmable Logic Controller shown in Figure 1 and USB controller circuitry connection diagram.
Fig. 3 is digital to analog converter shown in Figure 1 and Programmable Logic Controller circuit connection diagram.
[embodiment]
Be described in further detail below in conjunction with accompanying drawing and execution mode of the present utility model.
Please consulting Fig. 1 simultaneously, is the framework schematic diagram of the utility model AWG (Arbitrary Waveform Generator) one better embodiment.AWG (Arbitrary Waveform Generator) comprises host computer, USB (USB) controller, data storage, digital to analog converter (DAC transducer), analog signal output circuit and Programmable Logic Controller.
Described USB controller comprises the USB2.0 interface chip.Described Programmable Logic Controller connects EEPROM (Electrically Erasable Programmable Read Only Memo), and (Electrically Erasable Programmable Read-OnlyMemory is EEPROM) with active crystal oscillator.Described host computer connects described USB controller by usb bus.The USB control section of described USB controller and described Programmable Logic Controller is connected.Described USB controller also connects described data storage.Described data storage connects Programmable Logic Controller and described digital to analog converter.Described digital to analog converter connects described analog signal output circuit.The exportable random waveform of satisfying the demand of described analog signal output circuit.
Described programmable processor comprises USB control unit, modulus control unit, output control unit, FPGA overall logic control chip, I2C controller, internal clocking lock unit and internal clocking unit.Described USB control unit connects described USB controller, is used to control the USB controller and carries out transfer of data.Described modulus control unit connects described data storage and digital to analog converter simultaneously, and the digital signal that is used for control data memory and digital to analog converter converts analog signal to.Described output control unit connects described analog signal output circuit, is used to control described analog signal output circuit output waveform signals.Described I 2C controller connects outside EEPROM.Described internal clocking unit connects the external active crystal oscillator, produces internal clock signal.Described internal clocking lock unit is used for synchronous internal clock signal.The overall control logic chip of described FPGA is used for the described USB control unit of whole control, modulus control unit, output control unit, I2C controller, internal clocking lock unit and internal clocking unit.
In the present embodiment, described host computer major function is to utilize simulation software (as CVI, MATLAB, VB etc.) to produce required Wave data, and download in the waveform generator by USB interface, described in addition host computer also can be stored the driver of USB2.0 interface chip.
USB 2.0 interface chips that described USB controller adopts are EZ-USB FX2 family chip CY7C68013AE of Cypress Semiconductor company.
Described data storage comprises pin-saving chip SRAM, and it adopts the IS61LV25616-10T of ISSI company.
Described digital to analog converter comprises the D/A conversion chip, and that it adopts is AD9726, and this chip controls signal is simple, and the D/A conversion speed is fast, and the hardware designs of system is greatly simplified, and has also alleviated the workload of Design of System Software.
Described Programmable Logic Controller comprises the FPGA control chip, and the FPGA control chip adopts is that the Cyclone II serial model No. of altera corp is the FPGA control chip of EP2C20F484.Cyclone II device EP2C20F484 is based on the 90nm technology, provide 18,752 logical blocks (LE), and have a whole set of best function, comprise embedded 18 bit x18 bit multipliers, special external memory interface circuit, 4kbit in-line memory piece, phase-locked loop (PLL) and high-speed-differential I/O ability etc.
The USB2.0 interface chip of described USB controller has 2 kinds of interface modes: Slave FIFOs and programmable interface GPIF.When the FPGA of Programmable Logic Controller control chip links to each other with the USB2.0 interface chip, utilize the USB2.0 interface chip to realize high-speed communication with main frame as a USB2.0 data channel.Slave FIFOs mode is the slave mode, and peripheral control unit can be read and write the multilayer buffering FIFO of USB2.0 interface chip as common FIFO.The SlaveFIFOs working method of USB2.0 interface chip can be made as synchronous or asynchronous, and work clock is chosen as inner the generation or outside input, and other control signal also can be set to effectively high or effectively low neatly, and circuit connects as shown in Figure 2.
See also Fig. 2, wherein, IFCLK is a synchronizing clock signals, FLAGA, FLAGB and FLAGC are the Status Flags of the inner FIFO of USB2.0 interface chip, EP2C20F484 obtains the sky of the inner FIFO of CY7C68013, half-full (being set by the user half-full threshold value) and full these 3 status signals by universaling I/O port, ISLCS, SLOE, SLRD, SLWR carry out read-write operation control, FD[15:0 to CY7C68013] be data wire, ADD[1:0] be the address wire of selecting 4 FIFO.Its course of work is: host computer passes through the USB controller when fpga chip sends Wave data, the USB controller notifies fpga chip to read Wave data by the request mode, the FPGA control chip is at first checked sky, half-full and full these 3 status signals, select a FIFO, control USB then and receive the suitably data of size, can not overflow with the assurance data, and deposit among the storage chip SRAM of data storage.
Seeing also Fig. 3, is digital to analog converter shown in Figure 1 and Programmable Logic Controller circuit connection diagram.The Wave data of downloading from USB interface is stored in the storage chip SRAM of data storage, and SRAM circulation dateout produces analog waveform to the DAC chip of digital to analog converter according to the DDS principle.
The IS61LV25616 chip has the static random access memory (SRAM) of 256K * 16 a high-speed cmos technology, 3.3V single power supply, stores from the USB data downloaded under FPGA control, and datacycle is outputed to the DAC chip.AD9726 is that (Low-Voltage Differential Signaling, LVDS) modulus conversion chip have outstanding noise and spurious performance and true 16 direct current linearities to a 16 high-performance Low Voltage Differential Signals.It adopts the manufacturing of CMOS technology, and utilizes proprietary switching technique to strengthen dynamic property.This device has the full scale Current Regulation scope (2mA to 20mA) of broad, can be with the lower power consumption horizontal operation.Its electric current output configuration is easy, can be used for various single-ended or difference channel topological structures.
Compared to prior art, a kind of AWG (Arbitrary Waveform Generator) of the utility model has made full use of the powerful logic function of FPGA, has realized utilizing the scheme of monolithic fpga chip control whole system.Select USB2.0 interface chip CY7C68013 simultaneously, it can be preferably and the fpga chip cooperation, and the function that the system that finishes designs in advance makes overall circuit simple, and is with low cost, and the waveform signal precision of generation is higher.Digital waveform data directly is stored in the data storage by usb bus from host computer, by the control of Programmable Logic Controller Wave data is read, and sends into digital to analog converter and carries out obtaining required analog signal waveform after digital-to-analogue conversion and the processing and amplifying.Compare in the method for ROM or FLASH stored waveform data with traditional waveform generator, have bigger flexibility.
Above content be in conjunction with concrete preferred implementation to further describing that the utility model is done, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be considered as belonging to protection range of the present utility model.
Claims (6)
1. AWG (Arbitrary Waveform Generator) is characterized in that: comprise that the host computer that is used to produce Wave data is connected with host computer and receive the digital to analog converter and the Programmable Logic Controller that is used for control waveform Data Receiving, storage and digital-to-analogue conversion and output that is connected with described USB controller, data storage, digital to analog converter and analog signal output circuit that are used for digital signal is converted to analog signal that the data storage that is used for the stored waveform data that the USB controller of Wave data is connected with the USB controller is connected with data storage by USB interface.
2. AWG (Arbitrary Waveform Generator) according to claim 1 is characterized in that: the interface chip that described USB controller adopts is USB2.0 interface chip CY7C68013AE.
3. AWG (Arbitrary Waveform Generator) according to claim 2 is characterized in that: described Programmable Logic Controller connects EEPROM (Electrically Erasable Programmable Read Only Memo) and active crystal oscillator.
4. AWG (Arbitrary Waveform Generator) according to claim 3, it is characterized in that: described programmable processor comprises USB control unit, modulus control unit, output control unit, FPGA overall logic control chip, I2C controller, internal clocking lock unit and internal clocking unit, described USB control unit connects described USB controller, described modulus control unit connects described data storage and digital to analog converter simultaneously, described output control unit connects described analog signal output circuit, and described I2C controller connects outside EEPROM.Described internal clocking unit connects the external active crystal oscillator.
5. AWG (Arbitrary Waveform Generator) according to claim 1 is characterized in that: described data storage comprises pin-saving chip SRAM, and it adopts the IS61LV25616-10T of ISSI company.
6. AWG (Arbitrary Waveform Generator) according to claim 1 is characterized in that: described Programmable Logic Controller comprises that Cyclone II serial model No. is the FPGA control chip of EP2C20F484.
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| CN2010202079814U CN201708773U (en) | 2010-05-28 | 2010-05-28 | Arbitrarywaveform generator |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102520761A (en) * | 2011-12-20 | 2012-06-27 | 北京航天测控技术有限公司 | Arbitrary waveform generating system based on user-defined processor |
| CN102685512A (en) * | 2012-04-14 | 2012-09-19 | 广州航新航空科技股份有限公司 | Programmable array logic (PAL) video signal generation device based on arbitrary waveform generator |
| CN102684648A (en) * | 2012-01-10 | 2012-09-19 | 河南科技大学 | Waveform generating system and method based on microcontroller |
| CN102749531A (en) * | 2011-04-19 | 2012-10-24 | 联发科技股份有限公司 | Testing module, testing method, and testing system |
| CN104063007A (en) * | 2013-03-21 | 2014-09-24 | 特克特朗尼克公司 | Asynchronous time-interleaved waveform generator using harmonic mixing |
| CN104678968A (en) * | 2015-02-10 | 2015-06-03 | 中国科学院西安光学精密机械研究所 | Firefly luminous simulator |
| CN105005240A (en) * | 2015-07-08 | 2015-10-28 | 中国电子科技集团公司第四十一研究所 | Arbitrary wave generator based on off-line calculation |
| CN105651682A (en) * | 2016-03-28 | 2016-06-08 | 国网四川省电力公司电力科学研究院 | Soil corrosion simulation device and corrosion simulation method thereof for oil-gas pipelines |
| CN109240157A (en) * | 2018-09-13 | 2019-01-18 | 华北电力科学研究院有限责任公司 | SOE signal generation apparatus and SOE signal output method |
| CN109710023A (en) * | 2018-12-26 | 2019-05-03 | 中科院计算技术研究所南京移动通信与计算创新研究院 | One kind being based on the united arbitrary signal generating system of matlab and Qt and its method |
| CN109714115A (en) * | 2018-12-28 | 2019-05-03 | 中科院计算技术研究所南京移动通信与计算创新研究院 | A kind of FPGA Waveform generating method, device, equipment and the storage medium of Remote configuration |
| CN109799373A (en) * | 2019-02-18 | 2019-05-24 | 杭州长川科技股份有限公司 | The arbitrary waveform generator for having multi-channel synchronous function |
| CN111416596A (en) * | 2020-03-31 | 2020-07-14 | 上海工程技术大学 | Waveform generator based on SoC FPGA |
| CN112953470A (en) * | 2021-02-06 | 2021-06-11 | 江苏信息职业技术学院 | Four-channel 12GSaps arbitrary waveform generation module and waveform generation method |
| CN114050810A (en) * | 2022-01-13 | 2022-02-15 | 武汉通力路达科技有限公司 | PWM waveform generation method, device, embedded equipment and storage medium |
-
2010
- 2010-05-28 CN CN2010202079814U patent/CN201708773U/en not_active Expired - Fee Related
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102749531A (en) * | 2011-04-19 | 2012-10-24 | 联发科技股份有限公司 | Testing module, testing method, and testing system |
| CN102520761A (en) * | 2011-12-20 | 2012-06-27 | 北京航天测控技术有限公司 | Arbitrary waveform generating system based on user-defined processor |
| CN102684648A (en) * | 2012-01-10 | 2012-09-19 | 河南科技大学 | Waveform generating system and method based on microcontroller |
| CN102684648B (en) * | 2012-01-10 | 2014-07-30 | 河南科技大学 | Waveform generating system and method based on microcontroller |
| CN102685512A (en) * | 2012-04-14 | 2012-09-19 | 广州航新航空科技股份有限公司 | Programmable array logic (PAL) video signal generation device based on arbitrary waveform generator |
| CN102685512B (en) * | 2012-04-14 | 2014-09-10 | 广州航新航空科技股份有限公司 | Programmable array logic (PAL) video signal generation device based on arbitrary waveform generator |
| CN104063007B (en) * | 2013-03-21 | 2018-09-21 | 特克特朗尼克公司 | Use the asynchronous time intertexture waveform generator of harmonic mixing |
| CN104063007A (en) * | 2013-03-21 | 2014-09-24 | 特克特朗尼克公司 | Asynchronous time-interleaved waveform generator using harmonic mixing |
| CN104678968A (en) * | 2015-02-10 | 2015-06-03 | 中国科学院西安光学精密机械研究所 | Firefly luminous simulator |
| CN105005240A (en) * | 2015-07-08 | 2015-10-28 | 中国电子科技集团公司第四十一研究所 | Arbitrary wave generator based on off-line calculation |
| CN105651682A (en) * | 2016-03-28 | 2016-06-08 | 国网四川省电力公司电力科学研究院 | Soil corrosion simulation device and corrosion simulation method thereof for oil-gas pipelines |
| CN105651682B (en) * | 2016-03-28 | 2019-02-22 | 国网四川省电力公司电力科学研究院 | The corrosion simulated device of oil-gas pipeline soil environment and its corrosion simulation method |
| CN109240157A (en) * | 2018-09-13 | 2019-01-18 | 华北电力科学研究院有限责任公司 | SOE signal generation apparatus and SOE signal output method |
| CN109710023A (en) * | 2018-12-26 | 2019-05-03 | 中科院计算技术研究所南京移动通信与计算创新研究院 | One kind being based on the united arbitrary signal generating system of matlab and Qt and its method |
| CN109714115A (en) * | 2018-12-28 | 2019-05-03 | 中科院计算技术研究所南京移动通信与计算创新研究院 | A kind of FPGA Waveform generating method, device, equipment and the storage medium of Remote configuration |
| CN109714115B (en) * | 2018-12-28 | 2021-02-23 | 中科院计算技术研究所南京移动通信与计算创新研究院 | Method, device and equipment for generating remotely configured FPGA (field programmable Gate array) waveform and storage medium |
| CN109799373A (en) * | 2019-02-18 | 2019-05-24 | 杭州长川科技股份有限公司 | The arbitrary waveform generator for having multi-channel synchronous function |
| CN111416596A (en) * | 2020-03-31 | 2020-07-14 | 上海工程技术大学 | Waveform generator based on SoC FPGA |
| CN111416596B (en) * | 2020-03-31 | 2023-09-26 | 上海工程技术大学 | Waveform generator based on SoC FPGA |
| CN112953470A (en) * | 2021-02-06 | 2021-06-11 | 江苏信息职业技术学院 | Four-channel 12GSaps arbitrary waveform generation module and waveform generation method |
| CN114050810A (en) * | 2022-01-13 | 2022-02-15 | 武汉通力路达科技有限公司 | PWM waveform generation method, device, embedded equipment and storage medium |
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Granted publication date: 20110112 Termination date: 20110528 |