CN201681934U - Encapsulating structure for passive device with base island and multi-ring pins - Google Patents
Encapsulating structure for passive device with base island and multi-ring pins Download PDFInfo
- Publication number
- CN201681934U CN201681934U CN2010201825600U CN201020182560U CN201681934U CN 201681934 U CN201681934 U CN 201681934U CN 2010201825600 U CN2010201825600 U CN 2010201825600U CN 201020182560 U CN201020182560 U CN 201020182560U CN 201681934 U CN201681934 U CN 201681934U
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- pin
- dao
- pins
- chip
- base island
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an encapsulating structure for a passive device with a base island and multi-ring pins, which comprises the base island (1), multi-ring of pins (2), a conductive or nonconductive bonding material (6), a chip (7), a metal wire (8) and a filled encapsulation material (9), wherein the pins (2) rightly extend beside the base island (1); an unfilled encapsulation material (3) is embedded in the areas at the periphery of the pins (2), between the pins (2) and the base (1) and between the pins (2) and the pins (2); the chip (7) is arranged on the right side of the base island (1) through the conductive or nonconductive bonding material (6); passive components (10) are connected between the pins (2) and the pins (2) or between the pin (2) and the base island (1); the filled encapsulation material (9) is encapsulated above the base island (1) and the pins (2) and outside the chip (1), the metal wire (8) and the passive components (10); and a first metal layer (4) is arranged on the right sides of the pins (2) and adopts complete area electroplating or partial area electroplating. The utility model has the benefits of large binding capability of an encapsulating body and the metal pins, cost reduction, energy conservation, carbon dioxide emission reduction and waste reduction.
Description
(1) technical field
The utility model relates to a kind of encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
Traditional encapsulating structure mainly contains two kinds:
First kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process.
Second kind:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 4) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but this kind lead frame must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, and in the ball bonding bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of ball bonding bonding parameter, seriously influenced the quality of ball bonding and the stability of production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of this kind lead frame, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 5) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind:
This kind lead frame structure has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 6) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, shown in Fig. 7～8, the length of metal wire is longer, metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (being the product of storage class and the calculating that needs mass data by it, more outstanding); Too because the length of metal wire is longer, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are also higher to the interference of signal; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the constraint ability of good stability, plastic-sealed body and the metal leg of the quality of ball bonding and production reliability is big that basic island multi-turn pin passive device encapsulating structure is arranged.
The purpose of this utility model is achieved in that a kind of basic island multi-turn pin passive device encapsulating structure that has, comprise Ji Dao, pin, conduction or non-conductive bonding material, chip, metal wire and the filler plastic packaging material arranged, front at described Ji Dao and pin is provided with the first metal layer, be provided with second metal level at the back side of described Ji Dao and pin, described pin is provided with multi-turn, described pin front extends to next door, basic island, zone in described pin periphery, zone between pin 2 and the basic island and the zone between pin and the pin are equipped with packless plastic packaging material, described packless plastic packaging material is with periphery, pin bottom, pin bottom and Ji Dao bottom, the positive back side, extension of described pin and pin bottom and pin bottom link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, be provided with chip in front, described basic island by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, in cross-over connection between pin and the pin or between pin and the basic island passive device is arranged, at the top and the chip of described Ji Dao and pin, metal wire and passive device are encapsulated with the filler plastic packaging material outward.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of this kind lead frame.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of this kind lead frame, guaranteed the stability of ball bonding bonding parameter, guaranteed the quality of ball bonding and the stability of production reliability.
4) but again because this kind lead frame need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the zone between described metal leg (pin) and metal leg is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
6) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form the slightly little and big slightly structure of positive basic island size of the size of back side Ji Dao, and slided by the tighter more difficult generation that packless plastic packaging material coated and falling pin with the size that varies in size up and down of a Ji Dao.
7) separate etched technology owing to used the back side with the front, so the pin in lead frame front can be extended to as much as possible the next door of Ji Dao, impel chip and pin distance significantly to shorten, so the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter).
8) also because the shortening of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
9) because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
10) because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
(4) description of drawings
Fig. 1 is basic island multi-turn pin passive device encapsulating structure schematic diagram for the utility model has.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Fig. 4 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 5 was for formed insulation pin schematic diagram in the past.
Fig. 6 pin figure for what formed in the past.
Fig. 7 is an encapsulating structure schematic diagram in the past.
Fig. 8 is the vertical view of Fig. 7.
Reference numeral among the figure:
The base island 1, pin 2, packless plastic packaging material 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material 9, passive device 10 are arranged.
(5) embodiment
Referring to Fig. 1～2, Fig. 1 is basic island multi-turn pin passive device encapsulating structure schematic diagram for the utility model has.Fig. 2 is the vertical view of Fig. 1.By Fig. 1～2 as can be seen, the utility model has basic island multi-turn pin passive device encapsulating structure, comprise basic island 1, pin 2, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material 9 is arranged, front at described basic island 1 and pin 2 is provided with the first metal layer 4, the back side at described basic island 1 and pin 2 is provided with second metal level 5, described pin 2 is provided with multi-turn, described pin 2 fronts extend to 1 next door, basic island, zone in described pin 2 peripheries, zone between zone between pin 2 and the basic island 1 and pin 2 and the pin 2 is equipped with packless plastic packaging material 3, described packless plastic packaging material 3 is with periphery, pin bottom, pin 2 bottoms and 1 bottom, basic island, described pin 2 back sides, positive extension and pin 2 bottoms and pin 2 bottoms link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, be provided with chip 7 in 1 front, described basic island by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, in cross-over connection between pin 2 and the pin 2 or between pin 2 and the basic island 1 passive device 10 is arranged, at the top and the chip 7 of described basic island 1 and pin 2, metal wire 8 and the passive device 10 outer filler plastic packaging materials 9 that are encapsulated with.
The utility model can be electroplated the making that the first metal layer 4 or regional area are electroplated the first metal layer 4 because of the Zone Full that need carry out in the front of above-mentioned pin 2 of chip functions.
Claims (1)
1. one kind has basic island multi-turn pin passive device encapsulating structure, comprise Ji Dao (1), pin (2), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, front at described Ji Dao (1) and pin (2) is provided with the first metal layer (4), the back side at described Ji Dao (1) and pin (2) is provided with second metal level (5), it is characterized in that: described pin (2) is provided with multi-turn, described pin (2) front extends to Ji Dao (1) next door, in the peripheral zone of described pin (2), zone between zone between pin (2) and the Ji Dao (1) and pin (2) and the pin (2) is equipped with packless plastic packaging material (3), described packless plastic packaging material (3) is with periphery, pin bottom, pin (2) bottom and Ji Dao (1) bottom, described pin (2) back side, positive extension and pin (2) bottom and pin (2) bottom link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, be provided with chip (7) in described Ji Dao (1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), in cross-over connection between pin (2) and the pin (2) or between pin (2) and the Ji Dao (1) passive device (10) is arranged, top and chip (7) at described Ji Dao (1) and pin (2), the outer filler plastic packaging material (9) that is encapsulated with of metal wire (8) and passive device (10), the first metal layer (4) that the front of described pin (2) is provided with electroplates for Zone Full or regional area is electroplated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201825600U CN201681934U (en) | 2010-04-30 | 2010-04-30 | Encapsulating structure for passive device with base island and multi-ring pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201825600U CN201681934U (en) | 2010-04-30 | 2010-04-30 | Encapsulating structure for passive device with base island and multi-ring pins |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201681934U true CN201681934U (en) | 2010-12-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201825600U Expired - Lifetime CN201681934U (en) | 2010-04-30 | 2010-04-30 | Encapsulating structure for passive device with base island and multi-ring pins |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201681934U (en) |
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2010
- 2010-04-30 CN CN2010201825600U patent/CN201681934U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101222 |