CN201001163Y

CN201001163Y - TV set having multi-path HDMI interfaces

Info

Publication number: CN201001163Y
Application number: CNU2007200177261U
Authority: CN
Inventors: 陈杰; 王伟; 张建春; 马楔
Original assignee: Qingdao Hisense Electronics Co Ltd
Current assignee: Qingdao Hisense Electronics Co Ltd
Priority date: 2007-01-22
Filing date: 2007-01-22
Publication date: 2008-01-02
Anticipated expiration: 2017-01-22

Abstract

The utility model discloses a multi-HDMI interface television, which comprises a plurality of HDMI interfaces. The signal terminals of a plurality of HDMI interfaces are respectively and correspondingly connected with a plurality of input channels of a multi-channel HDMI decoding chip, the multi-channel HDMI decoding chip is connected with the host CPU of the television, to receive the channel switching control order output by the host CPU, then strobe the HDMI signal of the corresponding input channel to make decoding process, connect the audio signal created by decoding to the accompanying audio signal processing circuit of the television through the audio output terminal, and connect the created video signal to the video signal processing circuit through the television output terminal. Through arranging a plurality of HDMI interfaces on the television, the utility model realizes the simultaneous splicing of the television and a plurality of external HDMI signal sources, therefore avoiding the trouble that an user need to pull out and insert the input terminal when selecting different signal source equipments, and improving the convenience of the television product operation.

Description

Television set with multichannel HDMI interface

Technical field

The utility model belongs to technical field of television sets, relates to a kind of improvement of TV set circuit, specifically, relates to a kind of TV set circuit with multichannel HDMI interface.

Background technology

Along with the continuous development of Display Technique, the HDMI interface also more and more becomes a kind of important display port.The HDMI port is that a kind of digital video signal and audio signal of collecting is in the advanced interfaces mode of a port, because the digitlization and the high integration of its transmission signals, the HDMI interface is adopted by increasing signal source equipment, as high definition DVD, high-quality computer and Digital Video etc.Television set for realizing HDMI digital signal displaying the play in television set, all is provided with the HDMI input interface as most important video display terminal among the domestic consumer on the tv product of producing at present.But, on existing television equipment, the HDMI input interface generally has only one, once can only connect one tunnel outside HDMI signal source, select different signal source equipments need between different input interfaces, carry out manual plug and switch, make troubles for user's operation.

Summary of the invention

The utility model need carry out plug to signaling interface when switching in the prior art in order to solve between different HDMI signal source equipments problem, a kind of novel television set with multichannel HDMI input interface is provided, by multichannel HDMI input interface is set on television set, and the integrated chip that has reception of multichannel HDMI signal and decoding function in the television set internal configurations, thereby be connected when having realized television set and select output function, the trouble that the user need carry out plug to signaling interface when effectively having avoided switching between a plurality of HDMI signal sources with outside multichannel HDMI signal source equipment.

For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:

A kind of television set with multichannel HDMI interface, include multichannel HDMI interface, the signal end of described multichannel HDMI interface respectively with the corresponding connection of input multiplexer of a multichannel HDMI decoding chip, described multichannel HDMI decoding chip connects the host CPU of television set, receive the passage switching controls instruction of host CPU output, and then the HDMI signal of the corresponding input channel of gating carries out decoding processing, and the audio signal that generates of will decoding is connected to the audio signal treatment circuit of television set by its audio output, the vision signal that generates is connected to the video processing circuit of television set by its video output terminals.

In order to prevent electrostatic interference, between the input multiplexer of the signal end of described multichannel HDMI interface and multichannel HDMI decoding chip, be connected with electrostatic discharge protection circuit.

In described HDMI interface, include differential data signals end and differential clock signal end, undertaken after voltage clamping handles, with the corresponding connection of differential signal input of the corresponding input channel of described multichannel HDMI decoding chip by described electrostatic discharge protection circuit.

In order to mate the bus voltage standard of HDMI interface and multichannel HDMI decoding chip, to realize the reliable transmission of bus signals, the bus signals end of described HDMI interface connects voltage conversion circuit, after HDMI interface bus level conversion become the required bus level of described multichannel HDMI decoding chip, with the corresponding connection of bus port of the respective channel of multichannel HDMI decoding chip.

The bus signals end of described HDMI interface passes through I simultaneously ²The C bus connects eeprom memory, data such as the EDID of storage and HDMI signal correction and HDCP.

In order to simplify circuit structure, described electrostatic discharge protection circuit and voltage conversion circuit adopt an ESD integrated chip CM2021 who is integrated with described two kinds of functions to realize.

In the utility model, consider user's actual needs, on television set, designed 2 road HDMI interfaces, by electrostatic discharge protection circuit respectively with the corresponding connection of the two-way input channel of binary channels HDMI decoding chip.24 RGB of video output terminals output or the YUV signal of described binary channels HDMI decoding chip, the video processing circuit of connection television set; Audio output passes through I ²The S bus connects the audio signal treatment circuit of television set.The capable field sync signal output of binary channels HDMI decoding chip and data-signal clock end respectively with corresponding connection of corresponding function pin of television video signal processing circuit, the video data by described binary channels HDMI decoding chip output transmits according to described signal clock.Binary channels HDMI decoding chip passes through I ²The C bus connects the bus port of television set host CPU, receives the passage switching controls instruction of host CPU output.

Compared with prior art, advantage of the present utility model and good effect are: the utility model is by being provided with multichannel HDMI interface on television set, peg graft when having realized television set and extraneous multichannel HDMI signal source equipment, avoided the trouble of user's necessary plug input terminal when selecting the unlike signal source device.For the output that between multichannel HDMI interface, achieves accurate switching and decode, in TV set circuit, set up multichannel HDMI decoding chip, selection according to the user, wherein one road HDMI signal decoding output of gating, efficiently solve the problem of the multichannel HDMI signal source equipment of on a television set, plugging into simultaneously, improve the practicality of tv product and the convenience of operation, greatly promoted the complete machine quality of tv product.

Description of drawings

Fig. 1 is the gating treatment circuit theory diagram of two-way HDMI interface in the utility model;

Fig. 2 is the circuit catenation principle figure of HDMI interface and eeprom memory among Fig. 1;

Fig. 3 is the circuit catenation principle figure of ESD integrated chip among Fig. 1;

Fig. 4 is the circuit catenation principle figure of binary channels HDMI decoding chip SiI9023 among Fig. 1.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is done explanation in further detail.

The utility model is chosen in two-way HDMI interface is set on the TV shell by after the kind of outside signal source equipment and television set cost are taken all factors into consideration, and is connected when can realize television set with outside two-way HDMI signal source equipment.In order to simplify circuit structure, avoid using special selection to switch chip, the utility model has adopted a binary channels HDMI decoding chip SiI9023 who is integrated with passage switching and HDMI decoding processing dual-use function to be realized that its theory diagram is referring to shown in Figure 1.

In order to prevent electrostatic interference, after the signal end of two-way HDMI interface carries out the voltage clamping processing by one road electrostatic defending chip separately, with the corresponding connection of dual input passage of binary channels HDMI decoding chip SiI9023.Described binary channels HDMI decoding chip SiI9023 passes through I ²The C bus connects the host CPU of television set, receive the passage switching controls instruction of host CPU output, and then the HDMI signal of the corresponding input channel of gating carries out decoding processing, and the voiceband data signal of the generation of will decoding is connected to the audio signal treatment circuit of television set by its audio output, the video data signal that generates is connected to the video processing circuit of television set by its video output terminals, utilize the inner original audio frequency of television set, video signal processing board realizes the demonstration output of audio and video resources on television set in the external signal source device after the audio signal of binary channels HDMI decoding chip SiI9023 output and vision signal are handled.

Its physical circuit syndeton is referring to Fig. 2～shown in Figure 4.Wherein, CNA9, CN403 are two-way HDMI interface, comprise differential data signals end RRX0+, RRX0-, RRX1+, RRX1-, RRX2+, RRX2-; Differential clock signal end RRXC+, RRXC-and bus signals end DDC_CLK, DDC_DATA.

The differential data signals end RR0X0+ of HDMI interface CN403, RR0X0-, RR0X1+, RR0X1-, RR0X2+, RR0X2-and differential clock signal end RR0XC+, RR0XC-are connected the ESD electrostatic defending integrated chip U408 that a model is CM2021, carry out voltage clamp and handle respective differences sub-signal input R0X0+, R0X0-, R0X1+, R0X1-, R0X2+, R0X2-, R0XC+, the R0XC-that the back connects the first via input channel of binary channels HDMI decoding chip SiI9023.Bus signals end DDC_CLK0, the DDC_DATA0 of HDMI interface CN403 connects the level switch module of ESD integrated chip U408, with bus end DSCL0, the DSDA0 of 5V dc bus level conversion, with the bus voltage standard of coupling HDMI interface CN403 and binary channels HDMI decoding chip SiI9023 for the first passage of 3.3V bus level connection binary channels HDMI decoding chip SiI9023.Bus signals end DDC_CLK0, the DDC_DATA0 of HDMI interface CN403 pass through I simultaneously ²The C bus connects eeprom memory U405, data such as the EDID of storage and HDMI signal correction and HDCP.Wherein, the content of EDID data is the signal format of supporting about this machine; The HDCP data are authorization keys.

In like manner, the signal end of HDMI interface CNA9 is by the respective pin of second paths of ESD integrated chip U2411 connection binary channels HDMI decoding chip SiI9023, and its bus signals end DDC_CLK1, DDC_DATA1 pass through I ²The C bus connects eeprom memory U2409.

System bus port CSDA, the CSCL of described binary channels HDMI decoding chip SiI9023 pass through I ²The C bus connects the television set host CPU, receive the passage switching controls instruction of host CPU output, and then the HDMI signal of the gating first or second input channel carries out decoding processing, the audio signal that decoding generates is passed through the sound accompaniment disposable plates that the I2S bus connects television set, 24 RGB generating or yuv video signal ADATA0～ADATA23 are connected to the Video processing plate of television set by its video output terminals Q0～Q23, and then realize that by the loud speaker and the display screen of television set the output of external digital vision signal on television set shows.

The line synchronizing signal output HSYNC of described binary channels HDMI decoding chip SiI9023, field sync signal output VSYNC, control signal end DE and data-signal clock end ODCK respectively with corresponding connection of corresponding function pin of television video signal processing circuit.Wherein, resolves from the differential signal of input by the clock signal of described data-signal clock end ODCK transmission and to draw, video data ADATA0～ADATA23 that binary channels HDMI decoding chip SiI9023 exports transmits according to described signal clock.

The utility model has solved the problem of the two-way HDMI signal source equipment of plugging into simultaneously by adopting above-mentioned simple circuit configuration on a television set.Certainly, also more multichannel HDMI interface can be set in an identical manner, and the HDMI decoding chip of selecting to have multiplexer channel carries out passage switching and decoding processing, grafting requirement when satisfying the user to more HDMI signal source equipments, not only made things convenient for user's operation, and effectively improved the practicality of tv product, promoted the complete machine quality of tv product.

Certainly; above-mentioned explanation is not to be to restriction of the present utility model; the utility model also is not limited in above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present utility model also should belong to protection range of the present utility model.

Claims

1. television set with multichannel HDMI interface, include multichannel HDMI interface, it is characterized in that: the signal end of described multichannel HDMI interface respectively with the corresponding connection of input multiplexer of a multichannel HDMI decoding chip, described multichannel HDMI decoding chip connects the host CPU of television set, receive the passage switching controls instruction of host CPU output, and then the HDMI signal of the corresponding input channel of gating carries out decoding processing, and the audio signal that generates of will decoding is connected to the audio signal treatment circuit of television set by its audio output, the vision signal that generates is connected to the video processing circuit of television set by its video output terminals.

2. the television set with multichannel HDMI interface according to claim 1 is characterized in that: be connected with electrostatic discharge protection circuit between the input multiplexer of the signal end of described multichannel HDMI interface and multichannel HDMI decoding chip.

3. the television set with multichannel HDMI interface according to claim 1 is characterized in that: described multichannel HDMI decoding chip passes through I ²The C bus connects the bus port of television set host CPU, receives the passage switching controls instruction of host CPU output.

4. the television set with multichannel HDMI interface according to claim 2, it is characterized in that: the differential data signals end of described HDMI interface and differential clock signal end are undertaken after voltage clamping handles by described electrostatic discharge protection circuit, with the corresponding connection of differential signal input of the corresponding input channel of described multichannel HDMI decoding chip.

5. the television set with multichannel HDMI interface according to claim 2, it is characterized in that: the bus signals end of described HDMI interface connects voltage conversion circuit, after HDMI interface bus level conversion become the required bus level of described multichannel HDMI decoding chip, with the corresponding connection of bus port of the respective channel of multichannel HDMI decoding chip.

6. the television set with multichannel HDMI interface according to claim 5 is characterized in that: the bus signals end of described HDMI interface passes through I simultaneously ²The C bus connects eeprom memory.

7. according to claim 4 or 5 described television sets with multichannel HDMI interface, it is characterized in that: described electrostatic discharge protection circuit and voltage conversion circuit adopt an ESD integrated chip that is integrated with described two kinds of functions to realize.

8. the television set with multichannel HDMI interface according to claim 1 and 2 is characterized in that: 24 RGB of video output terminals output or the YUV signal of described multichannel HDMI decoding chip, the video processing circuit of connection television set; The audio output of multichannel HDMI decoding chip passes through I ²The S bus connects the audio signal treatment circuit of television set.

9. the television set with multichannel HDMI interface according to claim 1 and 2 is characterized in that: the capable field sync signal output of described multichannel HDMI decoding chip and data-signal clock end respectively with corresponding connection of corresponding function pin of television video signal processing circuit.

10. the television set with multichannel HDMI interface according to claim 1 and 2 is characterized in that: described HDMI interface includes 2 the tunnel, its signal end by the ESD integrated chip respectively with the corresponding connection of the two-way input channel of binary channels HDMI decoding chip.