CN208904873U - A kind of compensation circuit of input voltage sampling - Google Patents
A kind of compensation circuit of input voltage sampling Download PDFInfo
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- CN208904873U CN208904873U CN201821503896.5U CN201821503896U CN208904873U CN 208904873 U CN208904873 U CN 208904873U CN 201821503896 U CN201821503896 U CN 201821503896U CN 208904873 U CN208904873 U CN 208904873U
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Abstract
The utility model provides a kind of compensation circuit of input voltage sampling, including predeterminated voltage V1, pin UVP, pin GT, current mirror, clamper module, the utility model, which can be realized, only provides feedforward compensation electric current in power tube open stage, realize the compensation function of input voltage sampling, it avoids the occurrence of during power tube shutdown, especially under high input voltage, introduce that feedforward compensation is excessive that power tube is caused to be not turned on, caused by the big problem of system output ripple.
Description
Technical field
The utility model relates to switch power technology field, in particular to a kind of compensation circuit of input voltage sampling.
Background technique
With the rapid development of electronic technology, a fully functional Switching Power Supply control handles necessary main power control
Except circuit, need to include other functions toward contact, such as input undervoltage protection and feedforward compensation.In Patent No.
ZL201710678498.0 proposes a kind of input undervoltage protection circuit in the patent document of Publication No. CN107302214A,
Its overall applicability circuit reduction block diagram is as shown in Figure 1, main power topology is well-known technique, including input voltage vin, output electricity
Press Vout, capacitor CVIN, voltage divider resistor Rs1 and Rs2, controller, main power transformer, main power tube M1, diode Dout,
The devices such as capacitor C2, inductance L1 and capacitor C3 composition.The block diagram of its clamper module and current mirror module is as shown in Fig. 2, include drawing
Foot UVP, pin CS, current mirror, clamper module, it is real using the clamper module of UVP pin inner portions and the function of current mirror module
Existing input voltage feed forward compensation function.It realizes that the basic principle of feedforward compensating function is as follows:
If meeting Vin≥V1(1+Rs1/Rs2), then the voltage clamping of pin UVP is V1 by clamper module, is released on divider
Extra electric current ILC, there is following relationship:
Current mirror module is by electric current ILCI1 is generated by mirroring ratios K, i.e.,
I1 flows through resistance R through pin CSLCTo generate offset voltage VRLC=I1RLC, realize feedforward compensating function.
Fig. 1 and it is shown in Fig. 2 in the prior art, feedforward compensating function be it is full-time effective, i.e., opened in power tube M1
It opens and off-phases, all introduces feedforward compensation, during power tube M1 shutdown, the voltage on pin CS is due to sampling resistor
Voltage on Rcs is zero, so being equal to feedforward compensation voltage VRLC, rather than zero；In power tube M1 open stage, pin CS
On voltage be sampling resistor Rcs on voltage superposition feedforward compensation voltage VRLC.As shown in figure 3, being well known PWM mode control
The basic principle block diagram of system: the normal phase input end of PWM comparator CMP_PWM is that the output voltage sampling opto-coupled feedback of controller draws
The inverting input terminal for voltage signal VFB_CS, the PWM comparator CMP_PWM that foot FB is generated by PWM input gain module is control
Voltage signal VCS on device pin CS processed.Under wide scope DC input voitage, to meet the consistent of high-low pressure overpower point
Property, when high input voltage, the feedforward compensation voltage V that addsRLCIt is bigger, during power tube shutdown, if the voltage on pin CS
VRLCGreater than VFB_CS, then it is low level that PWM comparator CMP_PWM exports Toff_L signal always, is sent to the clear of d type flip flop DFF
Zero end Clr_L, then the output end Q output signal of d type flip flop is low level, then GT pin is low level, and power tube is not opened always
Open, power tube driving signal is caused to lack, driving signal, which lacks the problem of bringing, is: primary side does not have energy transmission to secondary side, makes
Power down is exported at system, output ripple is big, and output loop is unstable, is discontented with the requirement of pedal system output-index.
Emulate prior art flyback system waveform, as shown in figure 4, be followed successively by from top to bottom CS, VFB_CS, Toff_L,
CLK, GT and output VOUT waveform due to introducing feedforward compensation, make CS pin voltage 164.8mV during GT shutdown,
Value is greater than the value of VFB_CS, and can be seen that GT from two intermediate vertical lines should be turned into high level in the rising edge of CLK,
But since pin CS voltage is greater than VFB_CS, cause Toff_L is zero always, so GT is caused always to be low level, causes to drive
The missing of dynamic signal GT, primary side does not have energy transmission to secondary side, and then system is caused to export VOUT power down, until the electricity of CS pin
Pressure is less than VFB_CS, and GT becomes high level, and power tube M1 is opened, and CS pin voltage rises, when the voltage of CS pin rises to ratio
When VFB_CS high, power tube M1 shutdown, the energy transmission of primary side storage rises system output VOUT voltage, in this way to secondary side
One, cause the ripple of output VOUT big, simulation value is greater than 300mV, is discontented with pedal system output ripple index request.
Utility model content
Have in view of that, the technical problem to be solved by the present invention is to provide a kind of input voltage sampling compensation circuit,
It realizes and only provides feedforward compensation electric current in power tube open stage, realize the compensation function of input voltage sampling, avoid the occurrence of
During power tube turns off, especially under high input voltage, introduce that feedforward compensation is excessive that power tube is caused to be not turned on, caused by system
The problem of output ripple is big, is discontented with pedal system output-index.
The technical solution that the utility model solves above-mentioned technical problem is:
A kind of compensation circuit 100 of input voltage sampling, including predeterminated voltage V1, pin UVP, pin GT, current mirror
101, clamper module；
101 one end of current mirror is connect with clamper module, node ILC is formed, for receiving input voltage sampled signal；Electric current
The other end of mirror 101 exports feedforward compensation electric current, and then feedforward compensation voltage is generated on external feedforward compensation resistance, before realization
Present compensation function；
Clamper module is connect with predeterminated voltage V1, and predeterminated voltage V1 is the clamper benchmark of clamper module；Clamper module also with
Pin GT, pin UVP connection, when the partial pressure of the external divider of pin UVP is greater than or equal to V1, by the voltage of UVP pin
Clamper is predeterminated voltage V1, i.e., V at this timeUVP=V1.
Preferably as a kind of embodiment of clamper module, the clamper module 102 includes PMOS tube PM1, PMOS tube
The source electrode of PM2, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3 and NMOS tube NM4, PMOS tube PM1 are connect with predeterminated voltage V1,
The drain electrode of the grid and PMOS tube PM1 of PMOS tube PM1 is connect with the drain electrode of the grid of PMOS tube PM2, NMOS tube NM1；PMOS tube
The source electrode of PM2 is connect with pin UVP, drain electrode and the grid of NMOS tube NM1, the grid of NMOS tube NM2 and the leakage of PMOS tube PM2
The grid connection of pole, NMOS tube NM3, the drain electrode of NMOS tube NM3 connect with the source electrode of NMOS tube NM4, the grid of NMOS tube NM4 and
Pin GT connection, output of the drain electrode of NMOS tube NM4 as clamper module 102, forms node ILC；PMOS tube NM1, PMOS tube
NM2, NMOS tube NM3 source electrode with reference to connect.
Preferably as the another embodiment of clamper module, the clamper module 202 includes PMOS tube PM1, PMOS
Pipe PM2, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3 and NMOS tube NM4, the source electrode and predeterminated voltage V1 of PMOS tube PM1 connect
It connects, the drain electrode of the grid and PMOS tube PM1 of PMOS tube PM1 is connect with the drain electrode of the grid of PMOS tube PM2, NMOS tube NM1；PMOS
The source electrode of pipe PM2 is connect with pin UVP, and the drain electrode of PMOS tube PM2 is connect with the drain electrode of NMOS tube NM4, the grid of NMOS tube NM4
It is connect with pin GT, the grid of the source electrode of NMOS tube NM4 and NMOS tube NM1, the grid of NMOS tube and drain electrode, NMOS tube NM3
Grid connection, output of the drain electrode of NMOS tube NM3 as clamper module 202, forms node ILC；NMOS tube NM1, NMOS tube
NM2, NMOS tube NM3 source electrode with reference to connect.
Circuit carries out clamper and generates the principle of ILC in Patent No. ZL 201710678498.0, Publication No.
CN107302214A, patent name be in a kind of patent document of input undervoltage protection circuit in elaborated, this is practical
It is novel to repeat no more.
The utility model is connect in clamper module 102, through NMOS tube NM4 its grid with pin GT, only works as pin
When GT is high level, NMOS tube NM4 is just open-minded, and feedforward current ILC is just generated.Therefore feedforward compensation electric current I1 is only in power tube
Conducting phase, i.e. pin GT just has between high period, and circuit structure is simple.Feedforward compensation size of current is set as I1, electricity
The external feedforward compensation resistance in road is RLC, then the feedforward compensation voltage value generated is VRLC=I1·RLC。
Feedforward compensation electric current I1Calculation formula it is as follows:
Wherein, K is the current mirror ratio of current mirror 101, VinFor input voltage, Rs1、Rs2For the partial pressure of external divider
Resistance.
Fig. 7 is the compensation circuit of the utility model input voltage sampling in opto-coupled feedback inverse-excitation type switch power-supply application scenarios
In simulation waveform, comparison diagram 4 as can be seen that only just have feedforward compensation for high period between in GT, driving GT it is normally-open with
Shutdown, no deficient phenomena, loop stability, output voltage VO UT ripple is small, only 70mV, meets system output ripple index and wants
It asks.
Preferably as the another embodiment of clamper module, the NMOS tube NM4 and PMOS tube PM2 of clamper module 202
Drain electrode connection, the grid of NMOS tube NM4 connect with pin GT, the source electrode of NMOS tube NM4 and grid, the NMOS of NMOS tube NM1
The grid of pipe NM2 is connected with the grid of drain electrode, NMOS tube NM3.Output of the drain electrode of NMOS tube NM3 as clamper module 202, shape
At node ILC.Compared with clamper module 102, the locating circuit position of NMOS tube NM4 pipe is different, and the function of realizing is same,
I.e. only when pin GT is high level, NMOS tube NM4 is open-minded, and NMOS tube NM3 is just connected, and feedforward current ILC is just generated.
The circuit theory of the utility model, effect etc. are analyzed above, now by the beneficial effects of the utility model
It is summarized as follows:
1, compared with prior art, due to adding NMOS tube NM4, the grid of NMOS tube NM4 is connect with pin GT, Bian Keshi
Feedforward compensation electric current only now is introduced in power tube open stage, implementation circuit is few, and area is small, at low cost, function is reliable.
2, feedforward compensation electric current only is introduced in power tube open stage, not only can normally realizes the benefit of input voltage sampling
Function is repaid, and can be avoided the occurrence of during power tube shutdown, especially under high input voltage, introduces that feedforward compensation is excessive causes
Power tube is not turned on, caused by system output ripple it is big, be discontented with pedal system output-index require the problem of.
Detailed description of the invention
Fig. 1 is the application circuit simplification figure of the Switching Power Supply of the external feedforward compensation circuit of the prior art；
Fig. 2 is the current mirror of the prior art and the circuit block diagram of clamper module；
Fig. 3 is the basic circuit functional block diagram that the PWM mode of the prior art controls；
Fig. 4 is the simulation waveform of the opto-coupled feedback inverse-excitation type switch power-supply of the external feedforward compensation circuit of the prior art；
Fig. 5 is circuit reduction figure of the utility model in opto-coupled feedback reverse exciting switching voltage regulator application scenarios；
Fig. 6 is the circuit block diagram of the compensation circuit 100 of the utility model input voltage sampling；
Fig. 7 is the compensation circuit of the utility model input voltage sampling in opto-coupled feedback inverse-excitation type switch power-supply application scenarios
In simulation waveform；
Fig. 8 is the circuit diagram of one clamper module 102 of the utility model embodiment；
Fig. 9 is the circuit diagram of two clamper module 202 of the utility model embodiment.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
The utility model is further described in example.
Embodiment one
Fig. 5 is circuit reduction figure of the utility model in the application scenarios of opto-coupled feedback flyback sourse, and secondary side is omitted
Optocoupler and TL431 and loop compensation part.The compensation circuit of input voltage sampling described in the utility model is in controller 10
Circuit, other circuits are unrelated with the utility model in controller 10, are not unfolded to describe herein.Main power topology is public affairs in Fig. 5
Know technology, including input voltage Vin, output voltage Vout, capacitor CVIN, voltage divider resistor Rs1And Rs2, controller 10, main power become
Depressor, main power tube M1, diode DOUT, capacitor C2, inductance L1With capacitor C3Equal devices composition.GT pin is the drive of controller 10
Dynamic output, for controlling being switched on and off for power tube M1；FB pin is opto-coupled feedback pin, when output voltage Vout is increased,
Optocoupler is taken out electric current and is increased, and FB pin voltage reduces, on the contrary, optocoupler is taken out electric current and is reduced when output voltage Vout declines, FB pin electricity
Pressure increases；CS pin is current sample pin, by detecting current sampling resistor RCSVoltage determine to flow through power tube M1's
Peak point current；UVP pin is through voltage divider resistor Rs1And Rs2Detect input voltage Vin, component voltage section realizes feedforward compensating function, preceding
Feedback compensation electric current is flowed out by CS pin, in resistance RLCUpper generation offset voltage VRLC.Other pins of controller shown in fig. 5 connect
It connects relationship and function is unrelated with the utility model, Fig. 5 is not indicated.
Fig. 6 is the circuit block diagram of the compensation circuit 100 of the utility model input voltage sampling, including predeterminated voltage V1, draws
Foot GT, pin UVP, current mirror 101, clamper module 102.
101 one end of current mirror is connect with clamper module 102, node ILC is formed, for receiving input voltage sampled signal；
101 other end of current mirror is connect with pin CS, for exporting feedforward compensation electric current I1.
Clamper module 102 is connect with predeterminated voltage V1, and predeterminated voltage V1 is the clamper benchmark of clamper module 102.Clamper mould
Block 102 is also connect with pin GT, pin UVP, and when the partial pressure of the external divider of pin UVP is greater than or equal to V1, UVP is drawn
The voltage clamping of foot is predeterminated voltage V1.
Fig. 8 is the circuit diagram of clamper module 102, includes PMOS tube PM1, PM2, NMOS tube NM1, NM2, NM3, NM4.
The source electrode of PM1 is connect with predeterminated voltage V1, and the drain electrode of the grid and PM1 of PM1 is connect with the drain electrode of the grid of PM2, NM1；PM2's
Source electrode is connect with pin UVP, and the drain electrode of PM2 is connect with the grid of the grid of NM1, the grid of NM2 and drain electrode, NM3, the leakage of NM3
The connection of the source electrode of pole and NM4, the grid of NM4 are connect with pin GT, and output of the drain electrode of NM4 as clamper module 102 forms section
Point ILC；The source electrode of NM1, NM2, NM3 are connect with reference.The substrate of all PMOS and NMOS tube all connect with respective source electrode
It connects.
It should be noted that circuit carries out clamper and generates the principle of ILC in Patent No. ZL 201710678498.0,
Publication No. CN107302214A, patent name be a kind of input undervoltage protection circuit patent document in explain in detail
It states, the utility model repeats no more.It introduces with reference to the accompanying drawing, the compensation circuit course of work of input voltage sampling.
After controller 10 starts, if meeting Vin≥V1(1+Rs1/Rs2), then controller 10 exports PWM modulation signal, clamper
The voltage clamping of pin UVP is benchmark voltage V1 by module 102, extra electric current I on divider of releasingUVP, in the drain electrode of NM3
NMOS tube NM4 is added, NM4 grid is connect with pin GT, only when pin GT is high level, i.e. when power tube M1 is connected, NM4
Electric current I that is just open-minded, releasing at this timeUVPCurrent mirror could be passed through and generate I by a certain percentageLC, that is, control output ILC and exist
Power tube M1 open stage just generates, and describes principle, in embodiment 1, I for convenienceLC=IUVP, therefore have following relationship:
Current mirror 101 will export electric current ILCI1 is generated by mirroring ratios K, i.e.,
I1 flows through external feedforward compensation resistance R through pin CSLCTo generate offset voltage VRLC=I1RLC, realize that feedforward is mended
Repay function.Due to adding the control of NMOS tube NM4, circuit also only introduces feedforward compensation electric current in power tube open stage, can
The normal compensation function for realizing input voltage sampling, and can avoid the occurrence of during power tube shutdown, it is especially defeated in high pressure
Under entering, introduce that feedforward compensation is excessive that power tube is caused to be not turned on, caused by system output ripple it is big, be discontented with pedal system output-index
It is required that the problem of.
The particular circuit configurations of current mirror 101 have many implementations, and working principle letter in the prior art in Fig. 6
Single, the utility model is not described in detail one by one.
Embodiment two
As shown in figure 9, being the circuit diagram of the present embodiment clamper module 202, with embodiment 1 the difference lies in that real
The NMOS tube NM4 applied in the clamper module 202 of example 2 is connect with the drain electrode of PMOS tube PM2, and the grid of NM4 is connect with pin GT,
The source electrode of NM4 and grid, the grid of NM2 and the grid of drain electrode, NM3 of NM1 connect.The drain electrode of NM3 is as clamper module 102
Output forms node ILC.Compared with Example 1, the locating circuit position of NM4 pipe is different, and that it is controlled is leakage current IUVP
The inflow moment, only when pin GT be high level when, NM4 just it is open-minded, could NM3 be connected, the electric current I to releaseUVPJust lead to
Overcurrent mirror image generates I by a certain percentageLC, final feedforward current ILC just generates.
Although implementation is different, final purpose is all that feedforward current ILC is allowed just to produce in power tube M1 open stage
Raw, ILC is output in current mirror module 101, generates final feedforward compensation electric current I1.I1 through pin CS flow through resistance RLC with
Offset voltage VRLC=I1RLC is generated, realizes feedforward compensating function.
The above is the preferred embodiment of the utility model, and in addition to this, there are also when many control feedforward compensation electric currents
The mode of sequence, either control leakage current IUVP, feedforward current ILC or final feedforward compensation electric current I1, as long as finally
Purpose is that feedforward compensating function is just added in power tube open stage, it is noted that for the ordinary skill people of the art
For member, without departing from the principle of this utility model, several improvements and modifications made also should be regarded as the utility model
Protection scope.
Claims (3)
1. a kind of compensation circuit of input voltage sampling, it is characterised in that: including predeterminated voltage V1, pin UVP, pin GT, electricity
Flow mirror, clamper module；
Current mirror one end is connect with clamper module, node ILC is formed, for receiving input voltage sampled signal；Current mirror it is another
One end exports feedforward compensation electric current, and then feedforward compensation voltage is generated on external feedforward compensation resistance, realizes feedforward compensation function
Energy；
Clamper module is connect with predeterminated voltage V1, and predeterminated voltage V1 is the clamper benchmark of clamper module；Clamper module also with pin
GT, pin UVP connection, when the branch pressure voltage of the external divider of pin UVP is greater than or equal to predeterminated voltage V1, by UVP pin
Voltage clamping be predeterminated voltage V1.
2. compensation circuit according to claim 1, it is characterised in that: the clamper module includes PMOS tube PM1, PMOS tube
The source electrode of PM2, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3 and NMOS tube NM4, PMOS tube PM1 are connect with predeterminated voltage V1,
The drain electrode of the grid and PMOS tube PM1 of PMOS tube PM1 is connect with the drain electrode of the grid of PMOS tube PM2, NMOS tube NM1；PMOS tube
The source electrode of PM2 is connect with pin UVP, drain electrode and the grid of NMOS tube NM1, the grid of NMOS tube NM2 and the leakage of PMOS tube PM2
The grid connection of pole, NMOS tube NM3, the drain electrode of NMOS tube NM3 connect with the source electrode of NMOS tube NM4, the grid of NMOS tube NM4 and
Pin GT connection, output of the drain electrode of NMOS tube NM4 as clamper module, forms node ILC；PMOS tube NM1, PMOS tube NM2,
The source electrode of NMOS tube NM3 is connect with reference.
3. compensation circuit according to claim 1, it is characterised in that: the clamper module includes PMOS tube PM1, PMOS tube
The source electrode of PM2, NMOS tube NM1, NMOS tube NM2, NMOS tube NM3 and NMOS tube NM4, PMOS tube PM1 are connect with predeterminated voltage V1,
The drain electrode of the grid and PMOS tube PM1 of PMOS tube PM1 is connect with the drain electrode of the grid of PMOS tube PM2, NMOS tube NM1；PMOS tube
The source electrode of PM2 is connect with pin UVP, and the drain electrode of PMOS tube PM2 is connect with the drain electrode of NMOS tube NM4, the grid of NMOS tube NM4 with
The grid of pin GT connection, the source electrode of NMOS tube NM4 and NMOS tube NM1, the grid of NMOS tube NM2 and drain electrode, NMOS tube NM3
Grid connection, output of the drain electrode of NMOS tube NM3 as clamper module, forms node ILC；NMOS tube NM1, NMOS tube NM2,
The source electrode of NMOS tube NM3 is connect with reference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821503896.5U CN208904873U (en) | 2018-09-14 | 2018-09-14 | A kind of compensation circuit of input voltage sampling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821503896.5U CN208904873U (en) | 2018-09-14 | 2018-09-14 | A kind of compensation circuit of input voltage sampling |
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| Publication Number | Publication Date |
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| CN208904873U true CN208904873U (en) | 2019-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821503896.5U Withdrawn - After Issue CN208904873U (en) | 2018-09-14 | 2018-09-14 | A kind of compensation circuit of input voltage sampling |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104072A (en) * | 2018-09-14 | 2018-12-28 | 深圳南云微电子有限公司 | A kind of compensation circuit of input voltage sampling |
| CN112003614A (en) * | 2020-08-27 | 2020-11-27 | 中国电子科技集团公司第五十八研究所 | DDS output compensation circuit |
| CN115065246A (en) * | 2022-08-05 | 2022-09-16 | 苏州锴威特半导体股份有限公司 | Current compensation circuit for power management chip |
-
2018
- 2018-09-14 CN CN201821503896.5U patent/CN208904873U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104072A (en) * | 2018-09-14 | 2018-12-28 | 深圳南云微电子有限公司 | A kind of compensation circuit of input voltage sampling |
| CN109104072B (en) * | 2018-09-14 | 2024-05-17 | 深圳南云微电子有限公司 | Compensation circuit for input voltage sampling |
| CN112003614A (en) * | 2020-08-27 | 2020-11-27 | 中国电子科技集团公司第五十八研究所 | DDS output compensation circuit |
| CN112003614B (en) * | 2020-08-27 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | DDS output compensation circuit |
| CN115065246A (en) * | 2022-08-05 | 2022-09-16 | 苏州锴威特半导体股份有限公司 | Current compensation circuit for power management chip |
| CN115065246B (en) * | 2022-08-05 | 2022-11-04 | 苏州锴威特半导体股份有限公司 | Current compensation circuit for power management chip |
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