CN208224479U - A kind of multichannel active-passive integratedization Radar Signal Processing System - Google Patents
A kind of multichannel active-passive integratedization Radar Signal Processing System Download PDFInfo
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- CN208224479U CN208224479U CN201820880049.4U CN201820880049U CN208224479U CN 208224479 U CN208224479 U CN 208224479U CN 201820880049 U CN201820880049 U CN 201820880049U CN 208224479 U CN208224479 U CN 208224479U
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Abstract
The utility model discloses a kind of multichannel active-passive integratedization Radar Signal Processing System, the utility model includes the first transmitting antenna, the first receiving antenna, the second transmitting antenna, the second receiving antenna, third transmitting antenna, third receiving antenna, the 4th transmitting antenna, the 4th receiving antenna, the first multi-channel digital processing module, the second multi-channel digital processing module, FPGA processor, GPS clock module, USB conversion module, USB interface, network conversion module, network interface, PCIe conversion module, PCIe interface and PC terminal.The utility model is sent simultaneously by the first multi-channel digital processing module and the second multi-channel digital processing modules implement multichannel, receives signal, and the PC terminal carries out data transmission realizing the reception and transmitting of radar signal by the USB interface, network interface, PCIe interface.The utility model advantage is clock accuracy height, and stability is good, is applicable to the synchronization process of the signal of a variety of different frequency bands and agreement.
Description
Technical field
The utility model belongs to wireless communication technology field, believes more particularly to a kind of multichannel active-passive integratedization radar
Number processing system.
Background technique
Software-defined radio (SDR) technology is a kind of new wireless communication technique, is generally studied in radar communication field.
Its basic principle be use a standard, general, modular hardware sample platform as wireless communication basic platform, and to the greatest extent may be used
Wireless communication and personal communication function software realization more than energy.SDR hardware platform is realized by loading various software programmings
Different user, the different demands of different application environment realize various radio functions, and different software procedures is selected to realize different function
Can, software can upgrade update, and hardware can also regenerate as upgrading computer.SDR technology be based on Modern Communication Theory, with
Digital Signal Processing is core, take microelectric technique as the new radio communication architecture of support, is digital radio
Advanced form.
Radar system includes Active Radar and passive radar at present, and Active Radar is itself or partner's electromagnetic radiation
Wave differentiates the Azimuth & Range of target by receiving the echo-signal of target reflection.Its advantage is that independence is strong, by itself
Also more comprehensively, but the disadvantage is that the electromagnetic wave signal of own transmission is easy to be obtained by enemy the target information of acquisition, to expose
The location information of oneself.Passive radar can directly receive the electromagnetic wave signal of target emanation, also can receive external sort algorithm signal, lead to
It crosses the target echo that will be received and direct-path signal compares, to differentiate target bearing information.Passive radar it is excellent
Point is good concealment, and operating distance is remote, but the disadvantage is that range information is not easy to obtain.Therefore, a kind of system how is designed, by the two
Carrying out complementary combine is the critical issue for studying active-passive integratedization radar-probing system.
The structure and principle of both radar system and wireless communication system have certain similarity, therefore software is determined
The basic thought of adopted radio, which is dissolved into the design of radar system, has extremely important application value.
It should be broadband signal, the front end of ideal software radio that radar system, which requires receiver received from antenna,
Part should be able to cover whole wireless communication frequency bands, but usually, due to factors such as internal driving mismatches, it is difficult to by bandwidth
Width is done, and frequency range is smaller, therefore the receiver for designing a broad frequency range just becomes difficult.Furthermore present design
Mostly be all it is unidirectional, i.e., either only emission function or only receive capabilities, mode simple functions are relatively simple and flexible
Property is poor.In clock synchronization aspects, current clock system generally uses constant-temperature crystal oscillator or GPS/ Beidou second pulse signal
Timing signal either external input clock source it is synchronous come the clock for carrying out each system, but understand existing defects in this way: constant temperature is brilliant
Vibration has long-time frequency drift, is easy to produce accumulated error and is unable to maintain that prolonged synchronization；And GPS/ Beidou is severe
It can often be jumped because of various interference under construction environment, synchronous effect is equally not satisfactory, it is therefore desirable in conjunction with respectively excellent
Gesture designs synchronised clock and reduces synchronous error, it is ensured that system stablizes precise operation.
Utility model content
In order to solve the above-mentioned technical problem, the utility model proposes a kind of, and the edible fungus culturing based on Internet of Things is intelligently managed
Reason system.
In order to meet the needs of field and solve the deficiency of above-mentioned technology, the utility model provides a kind of main quilt of multichannel
Movement and motor-driven integrative Radar Signal Processing System, which is characterized in that including the first transmitting antenna, the first receiving antenna, the second transmitting day
Line, the second receiving antenna, third transmitting antenna, third receiving antenna, the 4th transmitting antenna, the 4th receiving antenna, the first multi-pass
Road digital processing module, the second multi-channel digital processing module, FPGA processor, GPS clock module, USB conversion module, USB
Interface, network conversion module, network interface, PCIe conversion module, PCIe interface and PC terminal；
First transmitting antenna is connect with the first multi-channel digital processing module by conducting wire；Described first receives
Antenna is connect with the first multi-channel digital processing module by conducting wire；Second transmitting antenna and first multichannel
Digital processing module is connected by conducting wire；Second receiving antenna and the first multi-channel digital processing module pass through conducting wire
Connection；The third transmitting antenna is connect with the second multi-channel digital processing module by conducting wire；The third receives day
Line is connect with the second multi-channel digital processing module by conducting wire；4th transmitting antenna and the second multichannel number
Word processing module is connected by conducting wire；4th receiving antenna and the second multi-channel digital processing module are connected by conducting wire
It connects；The first multi-channel digital processing module is connect with the FPGA processor by conducting wire；Second multi-channel digital
Processing module is connect with the FPGA processor by conducting wire；The GPS clock module and the FPGA processor pass through conducting wire
Connection；The FPGA processor is connect with the USB conversion module by conducting wire；The USB interface passes through with the PC terminal
Conducting wire connection；The network interface is connect with the PC terminal by conducting wire；The PCIe interface is with the PC terminal by leading
Line connection.
Preferably, first transmitting antenna is for emitting the first radar emission radiofrequency signal；Described first receives day
Line receives radiofrequency signal for receiving the first radar；Second transmitting antenna is for emitting the second radar emission radiofrequency signal；
Second receiving antenna receives radiofrequency signal for receiving the second radar；The third transmitting antenna is for emitting third radar
Emit radiofrequency signal；The third receiving antenna receives radiofrequency signal for receiving third radar；4th transmitting antenna is used
In the 4th radar emission radiofrequency signal of transmitting；4th receiving antenna receives radiofrequency signal for receiving the 4th radar；
The first multi-channel digital processing module is controlled according to the FPGA processor leads to the first transmitting baseband signal
Over-sampling, filtering, up-conversion, amplification are converted to the first radar emission radiofrequency signal, according to FPGA processor control by the
Two transmitting baseband signals are converted to the second radar emission radiofrequency signal by sampling, filtering, up-conversion, amplification, according to described
First radar radio frequency receiving signal is converted to first by amplification, filtering, down coversion, sampling filter and connect by FPGA processor control
Receive baseband signal, according to the FPGA processor control by the second radar radio frequency receiving signal by amplification, filtering, down coversion,
Sampling filter is converted to the second reception baseband signal；
The second multi-channel digital processing module, which is used to be controlled according to the FPGA processor, believes third transmitting baseband
Number third radar emission radiofrequency signal is converted to by sampling, filtering, up-conversion, amplification, is controlled according to the FPGA processor
4th transmitting baseband signal is converted into the 4th radar emission radiofrequency signal by sampling, filtering, up-conversion, amplification, according to institute
It states FPGA processor control and third radar reception radiofrequency signal is converted into third by amplification, filtering, down coversion, sampling filter
Baseband signal is received, the 4th radar is received by radiofrequency signal according to FPGA processor control and passes through amplification, filtering, lower change
Frequently, sampling filter is converted to the 4th reception baseband signal；The GPS clock module is calibrated according to GPS satellite time service clock source
The system clock of the utility model carries out data transmission；
The FPGA processor obtains the first reception baseband signal by controlling the first multi-channel digital processing module
And second receive baseband signal, by control the second multi-channel digital processing module obtain third receive baseband signal with
And the 4th receive baseband signal, receives baseband signal for first by controlling the USB conversion module, second receives base band letter
Number, third receive baseband signal and the 4th reception baseband signal be converted to the data-signal for meeting USB transport protocol, convert
Data-signal afterwards is transmitted to the PC terminal by the USB interface, is connect by controlling the network conversion module by first
Baseband signal, the second reception baseband signal, third reception baseband signal and the 4th reception baseband signal is received to be converted to and meet net
The data-signal of network transport protocol, the data-signal after conversion, to the PC terminal, pass through control by the network interface transfers
Make the PCIe conversion module by first receive baseband signal, second receive baseband signal, third receives baseband signal and the
Four reception baseband signals are converted to the data-signal for meeting PCIe transport protocol, and the data-signal after conversion is connect by the network
The PC terminal is transported in oral instructions；
Emissioning controling signal is transmitted to the USB conversion module by USB interface and passed through described by the PC terminal
FPGA processor control carries out data conversion, and emissioning controling signal after converting is by FPGA processor data analysis into the
One transmitting baseband signal, the second transmitting baseband signal, third transmitting baseband signal are connect with the 4th transmitting baseband signal by network
Oral instructions, which are transported to the network conversion module and controlled by the FPGA processor, carries out data conversion, the emission control after conversion
Signal is the first transmitting baseband signal, the second transmitting baseband signal, third transmitting base by FPGA processor data analysis
Band signal is transmitted to the PCIe conversion module by PCIe interface and is handled by the FPGA with the 4th transmitting baseband signal
Device control carries out data conversion, and the emissioning controling signal after converting is analyzed by the FPGA processor data as the first transmitting base
Band signal, the second transmitting baseband signal, third transmitting baseband signal are with the 4th transmitting baseband signal.
The present invention is based on the active-passive integrated radar systems of the multichannel of software radio thought to have the advantages that multichannel
Radio frequency sampling partitioned signal, which transmits stabilization, changeable frequency, bandwidth of operation, can be changed and have flexible configuration operating characteristics；System is wide
Band multimode multi-channel transceiver, can be used for actively and passive radar, it is compact-sized, it is small and exquisite, be suitable for a variety of different frequency bands and
The signal of agreement；System Clock Reference is calibrated using GPS time service, it is ensured that the clock between system module is synchronous logical with signal
Letter；It is connected by high speed FMC interface with high speed, stable and good portability between system module.
Detailed description of the invention
Fig. 1: the structural block diagram of the utility model；
Fig. 2: USB3.0,10,000,000,000 nets and PCIE module frame chart；
Fig. 3: multi-channel digital processing board work flow diagram.
Specific embodiment
The utility model is understood and implemented for the ease of those of ordinary skill in the art, it is right with reference to the accompanying drawings and embodiments
The utility model is described in further detail, it should be understood that implementation example described herein is only used for describing and explaining this
Utility model is not used to limit the utility model.
Referring to Fig.1, a kind of multichannel active-passive integratedization Radar Signal Processing System provided by the utility model, feature
It is to include: that first transmitting antenna is connect with the first multi-channel digital processing module by conducting wire；Described first connects
Antenna is received to connect with the first multi-channel digital processing module by conducting wire；Second transmitting antenna and first multi-pass
Road digital processing module is connected by conducting wire；Second receiving antenna is with the first multi-channel digital processing module by leading
Line connection；The third transmitting antenna is connect with the second multi-channel digital processing module by conducting wire；The third receives
Antenna is connect with the second multi-channel digital processing module by conducting wire；4th transmitting antenna and second multichannel
Digital processing module is connected by conducting wire；4th receiving antenna and the second multi-channel digital processing module pass through conducting wire
Connection；The first multi-channel digital processing module is connect with the FPGA processor by conducting wire；The second multichannel number
Word processing module is connect with the FPGA processor by conducting wire；The GPS clock module is with the FPGA processor by leading
Line connection；The FPGA processor is connect with the USB conversion module by conducting wire；The USB interface and the PC terminal are logical
Cross conducting wire connection；The network interface is connect with the PC terminal by conducting wire；The PCIe interface passes through with the PC terminal
Conducting wire connection.
First transmitting antenna is for emitting the first radar emission radiofrequency signal；First receiving antenna is for receiving
First radar receives radiofrequency signal；Second transmitting antenna is for emitting the second radar emission radiofrequency signal；Described second connects
It receives antenna and receives radiofrequency signal for receiving the second radar；The third transmitting antenna is for emitting third radar emission radio frequency letter
Number；The third receiving antenna receives radiofrequency signal for receiving third radar；4th transmitting antenna is for emitting the 4th
Radar emission radiofrequency signal；4th receiving antenna receives radiofrequency signal for receiving the 4th radar；First multichannel
Digital processing module is controlled according to the FPGA processor passes through sampling, filtering, up-conversion, amplification for the first transmitting baseband signal
Be converted to the first radar emission radiofrequency signal, according to the FPGA processor control by the second transmitting baseband signal by sampling,
Filtering, up-conversion, amplification are converted to the second radar emission radiofrequency signal, are controlled according to the FPGA processor and penetrate the first radar
Frequency receives signal and is converted to the first reception baseband signal by amplification, filtering, down coversion, sampling filter, at the FPGA
Second radar radio frequency receiving signal is converted to the second reception base band by amplification, filtering, down coversion, sampling filter by reason device control
Signal；The second multi-channel digital processing module is used to be controlled according to the FPGA processor by third transmitting baseband signal
Third radar emission radiofrequency signal is converted to by sampling, filtering, up-conversion, amplification, controlling according to the FPGA processor will
4th transmitting baseband signal is converted to the 4th radar emission radiofrequency signal by sampling, filtering, up-conversion, amplification, according to described
Third radar is received radiofrequency signal and is converted to third by amplification, filtering, down coversion, sampling filter and connects by FPGA processor control
Receive baseband signal, according to the FPGA processor control by the 4th radar receive radiofrequency signal by amplification, filtering, down coversion,
Sampling filter is converted to the 4th reception baseband signal；The GPS clock module calibrates this according to GPS satellite time transfer clock source
The system clock of utility model carries out data transmission；The FPGA processor handles mould by controlling first multi-channel digital
Block obtains the first reception baseband signal and the second reception baseband signal, passes through and controls the second multi-channel digital processing module
It obtains third and receives baseband signal and the 4th reception baseband signal, receive base for first by controlling the USB conversion module
Band signal, the second reception baseband signal, third receive baseband signal and the 4th reception baseband signal is converted to and meets USB transmission
The data-signal of agreement, the data-signal after conversion are transmitted to the PC terminal by the USB interface, by controlling the net
Network conversion module receives baseband signal, the second reception baseband signal, third for first and receives baseband signal and the 4th reception base
Band signal carries out being converted to the data-signal for meeting the network transmission protocol, and the data-signal after conversion is passed by the network interface
The PC terminal is transported to, baseband signal is received by first by controlling the PCIe conversion module, second receives baseband signal, the
Three reception baseband signals and the 4th reception baseband signal are converted to the data-signal for meeting PCIe transport protocol, the number after conversion
It is believed that number passing through the network interface transfers to the PC terminal；The PC terminal passes emissioning controling signal by USB interface
It transports to the USB conversion module and is controlled by the FPGA processor and carry out data conversion, emissioning controling signal is logical after conversion
Crossing the FPGA processor data analysis is the first transmitting baseband signal, the second transmitting baseband signal, third transmitting baseband signal
With the 4th transmitting baseband signal, controlled by network interface transfers to the network conversion module and by the FPGA processor
Carry out data conversion, after converting emissioning controling signal by the FPGA processor data analyze into the first transmitting baseband signal,
Second transmitting baseband signal, third transmitting baseband signal are transmitted to described with the 4th transmitting baseband signal by PCIe interface
PCIe conversion module simultaneously controls progress data conversion by the FPGA processor, and emissioning controling signal passes through described after conversion
The analysis of FPGA processor data is the first transmitting baseband signal, the second transmitting baseband signal, third transmitting baseband signal with the 4th
Transmitting baseband signal.
The embodiments of the present invention are introduced below with reference to Fig. 1 to Fig. 3.The first multi-channel digital processing module with
And the second multi-channel digital processing module is all made of AD9371 chip；The GPS clock module uses LEA-M8F module；
The FPGA processor uses Virtex-7 chip；The USB conversion module uses CYUSB3014 chip；The network interface conversion
Module and the PCIe conversion module are realized using FPGA internal logic resource；The USB interface uses USB3.0 interface；
The network interface uses 10,000,000,000 network interfaces；The PCIe interface uses PCIe X8 interface；The PC terminal uses desktop
Brain.
Detailed process of the embodiment of the present invention selects one of USB interface, network interface, PCIe interface by institute for the PC terminal
It states the first multi-channel digital processing module and the second multi-channel digital processing module operating mode is transmitted to the FPGA
Processor, and emissioning controling signal is transmitted to the FPGA by the USB conversion module by the USB interface and is handled
Device is transmitted to the FPGA processor by the network conversion module by the network interface, passes through the PCIe interface
The FPGA processor is transmitted to by the PCIe conversion module；The FPGA processor believes the transmitting transmitted by USB
Number analysis be the first transmitting baseband signal to the 4th transmitting baseband signal, the transmitting signal transmitted by 10,000,000,000 nets can also be analyzed
For the first transmitting baseband signal to the 4th transmitting baseband signal, the transmitting signal transmitted by PCIe can also be analyzed as the first hair
Baseband signal is penetrated to the 4th transmitting baseband signal；If the first multi-channel digital processing module operating mode is emission mode,
The FPGA processor is sent out the first transmitting baseband signal and second by controlling the first multi-channel digital processing module
It penetrates baseband signal and the first transmitting radar radiofrequency signal and the second transmitting is respectively converted by sampling, filtering, up-conversion, amplification
Radar radiofrequency signal passes through control described second if the second multi-channel digital processing module operating mode is emission mode
Multi-channel digital processing module by third transmitting baseband signal and the 4th transmitting baseband signal by sampling, filtering, up-conversion,
Amplification is respectively converted into third transmitting radar radiofrequency signal and the 4th transmitting radar radiofrequency signal, the first transmitting radar radio frequency letter
Number by first transmitting antenna emit, second transmitting radar radiofrequency signal by second transmitting antenna transmitting, third
Transmitting radar radiofrequency signal is emitted by the third transmitting antenna, and the 4th transmitting radar radiofrequency signal passes through the 4th transmitting
Antenna transmitting；If the first multi-channel digital processing module operating mode is reception pattern, the first receiving antenna connects first
Radar radio signal transmission is received to the first multi-channel digital processing module, the second receiving antenna receives radar radio frequency for second
Signal is transmitted to the first multi-channel digital processing module, and the FPGA controller is by controlling the first multichannel number
Word processing module by first receive radar radiofrequency signal and second receive radar radiofrequency signal by amplification, filtering, down coversion,
Sampling filter is respectively converted into the first reception baseband signal and second receives baseband signal, and first receives baseband signal and the
Two reception baseband signals control that the USB conversion module is converted to be transmitted to the USB interface by the FPGA processor, then
It is transmitted to the PC terminal, first, which receives baseband signal and the second reception baseband signal, controls institute by the FPGA processor
State that network conversion module is converted to be transmitted to the network interface, then be transmitted to the PC terminal, first receive baseband signal with
And second reception baseband signal control that the PCIe conversion module is converted to be transmitted to the PCIe by the FPGA processor
Interface, then it is transmitted to the PC terminal；The second multi-channel digital processing module operating mode is reception pattern, and third receives
Third is received radar radio signal transmission to the second multi-channel digital processing module by antenna, and the 4th receiving antenna is by the 4th
Radar radio signal transmission is received to the second multi-channel digital processing module, the FPGA controller is by controlling described the
Third is received radar radiofrequency signal to two multi-channel digital processing modules and the 4th reception radar radiofrequency signal passes through amplification, filter
Wave, down coversion, sampling filter are respectively converted into third and receive baseband signal and the 4th reception baseband signal, third reception base band
Described in signal and the 4th reception baseband signal are transmitted to by the way that the FPGA processor control USB conversion module is converted
USB interface, then be transmitted to the PC terminal, third receive baseband signal and the 4th receive baseband signal by the FPGA at
The reason device control network conversion module is converted to be transmitted to the network interface, then is transmitted to the PC terminal, and third receives
Baseband signal and the 4th reception baseband signal pass through the FPGA processor and control the converted transmission of PCIe conversion module
The extremely PCIe interface, then it is transmitted to the PC terminal.
Although it is a kind of multichannel active-passive integratedization that this specification, which has more used the technical solution of the utility model,
Radar Signal Processing System, it is characterised in that: connect including the first transmitting antenna, the first receiving antenna, the second transmitting antenna, second
Receive antenna, third transmitting antenna, third receiving antenna, the 4th transmitting antenna, the 4th receiving antenna, the processing of the first multi-channel digital
Module, the second multi-channel digital processing module, FPGA processor, GPS clock module, USB conversion module, USB interface, network
The terms such as conversion module, network interface, PCIe conversion module, PCIe interface and PC terminal, but be not precluded and use other arts
A possibility that language.The use of these items is only for more easily describing the essence of the utility model, it is construed as appointing
The additional limitation of what one kind is all contrary to the spirit of the present invention.
It should be understood that the part that this specification does not elaborate belongs to the prior art.
It should be understood that the above-mentioned description for preferred embodiment is more detailed, can not therefore be considered to this
The limitation of utility model patent protection scope, those skilled in the art are not departing under the enlightenment of the utility model
Under ambit protected by the claims of this utility model, replacement or deformation can also be made, the utility model is each fallen within
Within protection scope, the utility model is claimed range and should be determined by the appended claims.
Claims (2)
1. a kind of multichannel active-passive integratedization Radar Signal Processing System, it is characterised in that: including the first transmitting antenna, first
Receiving antenna, the second transmitting antenna, the second receiving antenna, third transmitting antenna, third receiving antenna, the 4th transmitting antenna,
Four receiving antennas, the first multi-channel digital processing module, the second multi-channel digital processing module, FPGA processor, GPS clock mould
Block, USB conversion module, USB interface, network conversion module, network interface, PCIe conversion module, PCIe interface and PC terminal；
First transmitting antenna is connect with the first multi-channel digital processing module by conducting wire；First receiving antenna
It is connect with the first multi-channel digital processing module by conducting wire；Second transmitting antenna and first multi-channel digital
Processing module is connected by conducting wire；Second receiving antenna and the first multi-channel digital processing module are connected by conducting wire
It connects；The third transmitting antenna is connect with the second multi-channel digital processing module by conducting wire；The third receiving antenna
It is connect with the second multi-channel digital processing module by conducting wire；4th transmitting antenna and second multi-channel digital
Processing module is connected by conducting wire；4th receiving antenna and the second multi-channel digital processing module are connected by conducting wire
It connects；The first multi-channel digital processing module is connect with the FPGA processor by conducting wire；Second multi-channel digital
Processing module is connect with the FPGA processor by conducting wire；The GPS clock module and the FPGA processor pass through conducting wire
Connection；The FPGA processor is connect with the USB conversion module by conducting wire；The USB interface passes through with the PC terminal
Conducting wire connection；The network interface is connect with the PC terminal by conducting wire；The PCIe interface is with the PC terminal by leading
Line connection.
2. multichannel active-passive integratedization Radar Signal Processing System according to claim 1, it is characterised in that: described
One transmitting antenna is for emitting the first radar emission radiofrequency signal；First receiving antenna is penetrated for receiving the reception of the first radar
Frequency signal；Second transmitting antenna is for emitting the second radar emission radiofrequency signal；Second receiving antenna is for receiving
Second radar receives radiofrequency signal；The third transmitting antenna is for emitting third radar emission radiofrequency signal；The third connects
It receives antenna and receives radiofrequency signal for receiving third radar；4th transmitting antenna is for emitting the 4th radar emission radio frequency letter
Number；4th receiving antenna receives radiofrequency signal for receiving the 4th radar；The first multi-channel digital processing module root
It is controlled according to the FPGA processor and the first transmitting baseband signal is converted into the first radar by sampling, filtering, up-conversion, amplification
Emit radiofrequency signal, the second transmitting baseband signal is passed through by sampling according to FPGA processor control, filtering, up-conversion, is put
The second radar emission radiofrequency signal is converted to greatly, is controlled according to the FPGA processor and passes through the first radar radio frequency receiving signal
Amplification, filtering, down coversion, sampling filter are converted to the first reception baseband signal, are controlled according to the FPGA processor by second
Radar radio frequency receiving signal is converted to the second reception baseband signal by amplification, filtering, down coversion, sampling filter；Described second
Multi-channel digital processing module be used for according to the FPGA processor control by third transmitting baseband signal by sampling, filtering,
Up-conversion, amplification are converted to third radar emission radiofrequency signal, are believed the 4th transmitting baseband according to FPGA processor control
Number the 4th radar emission radiofrequency signal is converted to by sampling, filtering, up-conversion, amplification, is controlled according to the FPGA processor
Third radar is received into radiofrequency signal, third reception baseband signal, root are converted to by amplification, filtering, down coversion, sampling filter
The 4th radar radiofrequency signal is received according to FPGA processor control to be converted to by amplification, filtering, down coversion, sampling filter
4th receives baseband signal；The GPS clock module carries out data biography according to GPS satellite time service clock source come calibration system clock
It is defeated；The FPGA processor obtains the first reception baseband signal and the by controlling the first multi-channel digital processing module
Two receive baseband signal, obtain third reception baseband signal and the 4th by controlling the second multi-channel digital processing module
Baseband signal is received, receives baseband signal, the second reception baseband signal, third for first by controlling the USB conversion module
It receives baseband signal and the 4th reception baseband signal is converted to the data-signal for meeting USB transport protocol, the data after conversion
Signal is transmitted to the PC terminal by the USB interface, receives base band letter for first by controlling the network conversion module
Number, second reception baseband signal, third receive baseband signal and the 4th reception baseband signal be converted to meet network transmission association
The data-signal of view, the data-signal after conversion is by the network interface transfers to the PC terminal, by described in control
PCIe conversion module receives baseband signal, the second reception baseband signal, third for first and receives baseband signal and the 4th reception
Baseband signal is converted to the data-signal for meeting PCIe transport protocol, and the data-signal after conversion passes through the network interface transfers
To the PC terminal；Emissioning controling signal is transmitted to the USB conversion module by USB interface and passes through institute by the PC terminal
It states FPGA processor control and carries out data conversion, the emissioning controling signal after conversion is by FPGA processor data analysis
First transmitting baseband signal, the second transmitting baseband signal, third transmitting baseband signal pass through network with the 4th transmitting baseband signal
Interface, which is transmitted to the network conversion module and is controlled by the FPGA processor, carries out data conversion, the transmitting control after conversion
Signal processed is the first transmitting baseband signal, the second transmitting baseband signal, third transmitting by FPGA processor data analysis
Baseband signal with the 4th transmitting baseband signal, by PCIe interface be transmitted to the PCIe conversion module and by the FPGA at
It manages device control and carries out data conversion, the emissioning controling signal after converting is analyzed by the FPGA processor data as the first transmitting
Baseband signal, the second transmitting baseband signal, third transmitting baseband signal are with the 4th transmitting baseband signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820880049.4U CN208224479U (en) | 2018-06-07 | 2018-06-07 | A kind of multichannel active-passive integratedization Radar Signal Processing System |
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| CN201820880049.4U CN208224479U (en) | 2018-06-07 | 2018-06-07 | A kind of multichannel active-passive integratedization Radar Signal Processing System |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110730134A (en) * | 2019-09-25 | 2020-01-24 | 恒大智慧科技有限公司 | Router and network connection system |
| CN113253226A (en) * | 2021-05-06 | 2021-08-13 | 中国电子科技集团公司第三十六研究所 | Method and equipment for acquiring and processing radar signals of external radiation source |
-
2018
- 2018-06-07 CN CN201820880049.4U patent/CN208224479U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110730134A (en) * | 2019-09-25 | 2020-01-24 | 恒大智慧科技有限公司 | Router and network connection system |
| CN113253226A (en) * | 2021-05-06 | 2021-08-13 | 中国电子科技集团公司第三十六研究所 | Method and equipment for acquiring and processing radar signals of external radiation source |
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