CN207966467U

CN207966467U - Pixel circuit and display panel

Info

Publication number: CN207966467U
Application number: CN201820332956.5U
Authority: CN
Inventors: 陈鹏; 王梓轩
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2018-03-12
Filing date: 2018-03-12
Publication date: 2018-10-12
Anticipated expiration: 2028-03-12

Abstract

A kind of pixel circuit and display panel, the pixel circuit include driving circuit, data write circuit, storage circuit, light-emitting component and biasing circuit.Driving circuit includes control terminal, first end and second end, and the luminous driving current of driving light-emitting component, the second end of the driving circuit receive the first voltage signal at first voltage end in order to control for configuration；Data write circuit is configured to the control terminal of data-signal write driver circuit in response to scanning signal；Storage circuit is configured to the data-signal of storage data write circuit write-in；Light-emitting component is configured to be shone according to driving current；Biasing circuit is configured in response to biasing enabling signal and applies bias voltage to the second end of light-emitting component with by light-emitting component reverse bias according to bias range signal.The pixel circuit can extend the service life of the OLED device of sub-pixel, and in the case where the pixel circuit is used for display panel, without increasing new signal for display panel, it is easy to accomplish.

Description

Pixel circuit and display panel

Technical Field

The embodiment of the disclosure relates to a pixel circuit and a display panel.

Background

Organic Light Emitting Diode (OLED) display devices are receiving much attention due to advantages of wide viewing angle, high contrast, fast response speed, higher Light Emitting brightness, lower driving voltage, and the like compared to inorganic Light Emitting display devices. Due to the characteristics, the Organic Light Emitting Diode (OLED) can be suitable for devices with display functions, such as mobile phones, displays, notebook computers, digital cameras, instruments and meters, and the like.

The pixel circuits in the OLED display device generally adopt a Matrix driving method, and are classified into Active Matrix (AM) driving and Passive Matrix (PM) driving according to whether a switching device is introduced into each pixel unit. Although the PMOLED has a simple process and a low cost, the PMOLED cannot meet the requirements of high-resolution large-size display due to the defects of cross-talk, high power consumption, low service life and the like. In contrast, the AMOLED integrates a set of thin film transistor and storage capacitor in the pixel circuit of each pixel, and the current flowing through the OLED is controlled by driving and controlling the thin film transistor and the storage capacitor, so that the OLED emits light as required. Compared with PMOLED, the AMOLED has the advantages of small driving current, low power consumption and longer service life, and can meet the large-size display requirements of high resolution and multi-gray scale. Meanwhile, the AMOLED has obvious advantages in the aspects of visual angle, color reduction, power consumption, response time and the like, and is suitable for display devices with high information content and high resolution.

SUMMERY OF THE UTILITY MODEL

At least one embodiment of the present disclosure provides a pixel circuit including: a drive circuit, a data write circuit, a memory circuit, a light emitting element, and a bias circuit; the driving circuit comprises a control end, a first end and a second end and is configured to control a driving current for driving the light-emitting element to emit light, and the second end of the driving circuit receives a first voltage signal of a first voltage end; the data writing circuit is connected with the control end of the driving circuit and is configured to write a data signal into the control end of the driving circuit in response to a scanning signal; the first end of the storage circuit is connected with the control end of the driving circuit, the second end of the storage circuit is connected with the first end of the driving circuit, and the storage circuit is configured to store the data signal written by the data writing circuit; the first end of the light-emitting element receives a second voltage signal of a second voltage end, and the second end of the light-emitting element is connected with the first end of the driving circuit and is configured to emit light according to the driving current; the bias circuit is connected with the second end of the light-emitting element and is configured to respond to a bias starting signal and apply a bias voltage to the second end of the light-emitting element according to a bias amplitude signal so as to reversely bias the light-emitting element.

For example, in a pixel circuit provided by an embodiment of the present disclosure, the bias circuit includes a first capacitor and a first transistor; a first electrode of the first capacitor is connected to the second end of the light emitting element, and a second electrode of the first capacitor is connected to the first electrode of the first transistor; the gate of the first transistor is configured to be connected to a bias enable line to receive the bias enable signal, and the second pole of the first transistor is configured to be connected to a bias magnitude line to receive the bias magnitude signal.

For example, in a pixel circuit provided in an embodiment of the present disclosure, the driving circuit includes a second transistor; the grid electrode of the second transistor is used as the control end of the driving circuit, the first pole of the second transistor is used as the first end of the driving circuit, and the second pole of the second transistor is used as the second end of the driving circuit.

For example, in a pixel circuit provided in an embodiment of the present disclosure, the data writing circuit includes a third transistor; the gate of the third transistor is configured to be connected to a scan line to receive the scan signal, the first pole of the third transistor is configured to be connected to a data line to receive the data signal, and the second pole of the third transistor is configured to be connected to the control terminal of the driving circuit.

For example, in a pixel circuit provided in an embodiment of the present disclosure, the storage circuit includes a second capacitor; the first pole of the second capacitor is used as the first end of the storage circuit, and the second pole of the second capacitor is used as the second end of the storage circuit.

For example, an embodiment of the present disclosure provides a pixel circuit including a reset circuit, wherein the reset circuit is connected to a control terminal of the driving circuit and configured to apply a reset voltage to the control terminal of the driving circuit in response to a reset signal.

For example, in a pixel circuit provided by an embodiment of the present disclosure, the reset circuit includes a fourth transistor; a gate of the fourth transistor is configured to be connected to a reset line to receive the reset signal, a first pole of the fourth transistor is configured to be connected to the control terminal of the driving circuit, and a second pole of the fourth transistor is configured to be connected to a first voltage terminal to receive the reset voltage.

For example, a pixel circuit provided in an embodiment of the present disclosure includes a light emission control circuit, wherein the light emission control circuit is connected to a first terminal of the light emitting element and configured to apply a second voltage signal of the second voltage terminal to the first terminal of the light emitting element in response to a light emission control signal.

For example, in a pixel circuit provided in an embodiment of the present disclosure, the light emission control circuit includes a fifth transistor; a gate of the fifth transistor is configured to be connected to a light emission control line to receive the light emission control signal, a first pole of the fifth transistor is configured to be connected to the second voltage terminal to receive the second voltage signal, and a second pole of the fifth transistor is configured to be connected to the first terminal of the light emitting element.

At least one embodiment of the present disclosure further provides a display panel, which includes a plurality of pixel units distributed in an array, where each pixel unit includes the pixel circuit according to any one of the embodiments of the present disclosure.

For example, the display panel provided in an embodiment of the present disclosure includes a plurality of scan lines, wherein the data writing circuit in the pixel circuit in the nth row is connected to the scan line in the nth row to receive the scan signal, the bias circuit in the pixel circuit in the nth row is connected to the scan line in the nth-1 row to receive the scan signal in the nth-1 row as the bias enable signal and/or the bias amplitude signal, and N is an integer greater than 1.

For example, in the display panel provided by one embodiment of the present disclosure, the reset circuit in the pixel circuit of the nth row is connected to the scan line of the nth-2 row to receive the scan signal of the nth-2 row as the reset signal, where N is an integer greater than 2.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic block diagram of another pixel circuit provided in an embodiment of the present disclosure;

FIG. 3 is a circuit diagram of one specific implementation example of the pixel circuit shown in FIG. 1;

FIG. 4 is a circuit diagram of one specific implementation example of the pixel circuit shown in FIG. 2;

fig. 5 is a signal timing diagram of a pixel circuit according to an embodiment of the disclosure;

FIGS. 6A to 6C are circuit diagrams of the pixel circuit shown in FIG. 3 corresponding to three stages in FIG. 5, respectively;

fig. 7 is a signal timing diagram of another pixel circuit according to an embodiment of the disclosure;

FIG. 8 is a circuit diagram of the pixel circuit shown in FIG. 4 corresponding to the fourth stage in FIG. 7;

fig. 9 is a schematic block diagram of a display panel provided in an embodiment of the present disclosure; and

fig. 10 is a schematic block diagram of another display panel provided in an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the display field and the illumination field, the service life of the OLED device has been a focus of attention of various manufacturers. Since the OLED is a self-luminous device, the OLED may be aged during a light emitting process, resulting in a decrease in brightness. The aging mechanism of OLEDs includes a variety of factors such as device intrinsic defects, OLED device degradation, and the like. In the field of AMOLED display, there are various types of pixel circuits for driving an OLED, such as a 2T1C circuit composed of 2 Thin-Film transistors (TFTs) and 1 Capacitor (C), or a 4T1C, 4T2C circuit having a threshold voltage compensation function, and the like. The aging problem of the OLED device cannot be improved by the pixel circuits, and the service life of the OLED device cannot be effectively prolonged.

At least one embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display panel. The pixel circuit can load reverse voltage difference to the OLED after the OLED emits light, promotes and eliminates the defect of accumulation of the OLED in a positive voltage stage, and accordingly can improve the aging problem of the OLED device, the service life of the OLED device is prolonged, and when the pixel circuit is used for a display panel, new signals do not need to be added to the display panel, the service life of the display panel can be prolonged, and the pixel circuit is easy to achieve.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

At least one embodiment of the present disclosure provides a pixel circuit including a driver circuit, a data writing circuit, a storage circuit, a light emitting element, and a bias circuit. The driving circuit comprises a control end, a first end and a second end and is configured to control a driving current for driving the light-emitting element to emit light, and the second end of the driving circuit receives a first voltage signal of a first voltage end; the data writing circuit is connected with the control end of the driving circuit and is configured to write a data signal into the control end of the driving circuit in response to a scanning signal; the first end of the storage circuit is connected with the control end of the driving circuit, the second end of the storage circuit is connected with the first end of the driving circuit, and the storage circuit is configured to store the data signal written by the data writing circuit; the first end of the light-emitting element receives a second voltage signal of a second voltage end, and the second end of the light-emitting element is connected with the first end of the driving circuit and is configured to emit light according to the driving current; the bias circuit is connected with the second end of the light-emitting element and is configured to respond to a bias starting signal and apply a bias voltage to the second end of the light-emitting element according to a bias amplitude signal so as to reversely bias the light-emitting element.

Fig. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure. Referring to fig. 1, a pixel circuit 10 includes a driver circuit 100, a data writing circuit 200, a memory circuit 300, a reset circuit 400, a light emitting element 500, and a bias circuit 600. The pixel circuit 10 is used for a sub-pixel of an OLED display device, for example.

For example, the driving circuit 100 includes a first terminal 110, a second terminal 120 and a control terminal 130, and is configured to control a driving current for driving the light emitting element 500 to emit light, and the second terminal 120 of the driving circuit 100 receives a first voltage signal of a first voltage terminal VSS. The control terminal 130 of the driving circuit 100 is connected to the first node N1, the first terminal 110 of the driving circuit 100 is connected to the second node N2, and the second terminal 120 of the driving circuit 100 is connected to the first voltage terminal VSS (the third node N3) to receive the first voltage signal. For example, the driving circuit 100 may supply a driving current to the light emitting element 500 to drive the light emitting element 500 to emit light, and may emit light in "gray scale" as needed. For example, the light emitting element 500 may employ an OLED and be configured to be connected to the second node N2 and the second voltage terminal VDD (e.g., a high level), and embodiments of the present disclosure include but are not limited thereto.

For example, the data writing circuit 200 is connected to the control terminal 130 (the first node N1) of the driving circuit 100, and is configured to write a data signal into the control terminal 130 of the driving circuit 100 in response to a scan signal. For example, the data writing circuit 200 is connected to a data line (data signal terminal Vdata), the first node N1, and a scan line (scan signal terminal Vscan (N)), respectively. For example, a scan signal from the scan signal terminal Vscan (n) is applied to the data writing circuit 200 to control whether the data writing circuit 200 is turned on or off. For example, in the data writing phase, the data writing circuit 200 may be turned on in response to the scan signal, so that the data signal may be written into the control terminal 130 (the first node N1) of the driving circuit 100, and then the data signal may be stored in the storage circuit 300 to generate the driving current for driving the light emitting element 500 to emit light according to the data signal.

For example, the first terminal 310 of the memory circuit 300 is connected to the control terminal 130 (the first node N1) of the driving circuit 100, and the second terminal 320 of the memory circuit 300 is connected to the first terminal 110 (the second node N2) of the driving circuit 100, and is configured to store the data signal written by the data writing circuit 200. For example, the memory circuit 300 may store the data signal and control the driving circuit 100 using the stored data signal.

For example, the reset circuit 400 is connected to the control terminal 130 (the first node N1) of the driving circuit 100, and is configured to apply a reset voltage to the control terminal 130 of the driving circuit 100 and the first terminal 310 of the memory circuit 300 in response to a reset signal. For example, the reset circuit 400 is connected to the first node N1, the first voltage terminal VSS (the third node N3), and the reset line (the reset terminal Rst), respectively. For example, the reset circuit 400 may be turned on in response to a reset signal, so that a reset voltage (here, a voltage for resetting is a first voltage signal) may be applied to the first node N1, the first terminal 310 of the memory circuit 300, and the control terminal 130 of the driving circuit 100, so that a reset operation may be performed on the memory circuit 300 and the driving circuit 100, eliminating the influence of the previous light emitting stage. For example, the reset voltage may be provided by the first voltage terminal VSS, and in other embodiments, may be provided by a reset voltage terminal independent of the first voltage terminal VSS, so that the reset circuit 400 is not connected to the first voltage terminal VSS (the third node N3) but connected to the reset voltage terminal, accordingly, and the embodiments of the present disclosure are not limited thereto. For example, the first voltage terminal VSS is a low voltage terminal, such as a ground terminal. For example, the reset circuit 400 may be omitted or integrated into other circuits depending on the specific circuit configuration.

For example, in a display device, when the pixel circuits 10 are arranged in an array, the data writing circuit 200 in the nth (N is an integer greater than 2) row is connected to the scan line (scan signal terminal Vscan (N)) in the nth row to receive the scan signal, and the reset circuit 400 in the nth row is connected to the scan line (scan signal terminal Vscan (N-2)) in the nth-2 row to receive the scan signal in the nth-2 row as the reset signal. Compared with the traditional display panel, the mode does not need to add new signals, and the circuit is simple in structure and easy to implement.

For example, the light emitting element 500 includes a first terminal 510 and a second terminal 520 configured to emit light according to a driving current provided by the driving circuit 100. The first terminal 510 of the light emitting device 500 is configured to receive the second voltage signal of the second voltage terminal VDD, and the second terminal 520 of the light emitting device 500 is configured to be connected to the first terminal 110 (the second node N2) of the driving circuit 100.

For example, the bias circuit 600 is connected to the second terminal 520 (second node N2) of the light emitting element 500, and is configured to apply a bias voltage to the second terminal 520 of the light emitting element 500 in response to a bias enable signal and according to a bias magnitude signal to reverse bias the light emitting element 500. For example, the bias circuit 600 is connected to the second node N2, a bias enable line (bias enable terminal Vb), and a bias amplitude line (bias amplitude terminal Vamp), respectively. For example, the bias circuit 600 may be turned on in response to a bias enable signal provided from the bias enable terminal Vb to apply a bias voltage to the second terminal 520 of the light emitting element 500 according to a bias amplitude signal provided from the bias amplitude terminal Vamp. For example, the bias voltage may not be equal to the bias magnitude signal. After the light emitting element 500 (e.g., OLED) emits light, a bias voltage is applied to the light emitting element to reverse bias the light emitting element, which can promote elimination of defects accumulated in the light emitting element 500 in a positive voltage stage (e.g., light emitting stage), thereby improving the aging problem of the light emitting element 500 itself and extending the service life of the light emitting element 500.

For example, the bias enable terminal Vb and the bias amplitude terminal Vamp may be connected to the same signal line, so that the bias enable signal and the bias amplitude signal are the same signal, which may simplify the circuit design. For example, in a display device, when the pixel circuits 10 are arranged in an array, the data writing circuit 200 in the nth (N is an integer greater than 1) row is connected to the scan line (scan signal terminal Vscan (N)) in the nth row to receive the scan signal, and the bias circuit 600 in the nth row is connected to the scan line (scan signal terminal Vscan (N-1)) in the nth row to receive the scan signal in the nth-1 row as the bias enable signal and/or the bias amplitude signal. Therefore, the scanning signals of the pixel circuit 10 can be utilized, and compared with the traditional display panel, the scanning display panel does not need to add new signals, and has simple circuit structure and easy realization.

Fig. 2 is a schematic block diagram of another pixel circuit provided in an embodiment of the present disclosure. Referring to fig. 2, the pixel circuit 10 may further include a light emission control circuit 700, and the other structure is substantially the same as the pixel circuit 10 shown in fig. 1. The light emission control circuit 700 is connected to the first terminal 510 of the light emitting element 500, and is configured to apply a second voltage signal of the second voltage terminal VDD to the first terminal 510 of the light emitting element 500 in response to the light emission control signal. For example, the light emission control circuit 700 is connected to the second voltage terminal VDD, the light emission control line (light emission control terminal Em), and the first terminal 510 of the light emitting element 500, respectively. For example, in the light emitting phase, the light emitting control circuit 700 is turned on in response to the light emitting control signal provided by the light emitting control terminal Em, so that the driving circuit 100 can apply a driving current to the light emitting element 500 through the light emitting control circuit 700 to cause it to emit light; in the non-light emitting stage, the light emitting control circuit 700 is turned off in response to the light emitting control signal, so that the current flowing through the light emitting element 500 is prevented from causing the light emitting element to emit light, and the contrast of the corresponding display device can be improved.

For example, in the case that the driving circuit 100 is implemented as a driving transistor, for example, a gate of the driving transistor may serve as the control terminal 130 (connected to the first node N1) of the driving circuit 100, a first pole (e.g., a source) may serve as the first terminal 110 (connected to the second node N2) of the driving circuit 100, and a second pole (e.g., a drain) may serve as the second terminal 120 (connected to the third node N3) of the driving circuit 100.

Note that, the first voltage terminal VSS in the embodiments of the present disclosure holds, for example, an input dc low level signal, and the dc low level signal is referred to as a first voltage (which may be used as a reset voltage); the second voltage terminal VDD holds, for example, an input dc high level signal, which is referred to as a second voltage and is higher than the first voltage. The following embodiments are the same and will not be described again.

Note that in the description of the embodiments of the present disclosure, the symbol Vdata may represent both the data signal terminal and the level of the data signal. Likewise, the symbol Rst may represent both the reset terminal and the level of the reset signal, the symbol VSS may represent both the first voltage terminal and the first voltage, the symbol VDD may represent both the second voltage terminal and the second voltage, the symbol Vb may represent both the bias enable terminal and the level of the bias enable signal, and the symbol Vamp may represent both the bias magnitude terminal and the level of the bias magnitude signal. The following embodiments are the same and will not be described again.

It should be noted that the pixel circuit 10 provided in the embodiments of the present disclosure may also include other circuit structures with compensation functions. The compensation function may be implemented by voltage compensation, current compensation or hybrid compensation, and the pixel circuit 10 having the compensation function may be a combination of a circuit such as 4T1C or 4T2C and the bias circuit 600, for example. For example, in the pixel circuit 10 having the compensation function, the data writing circuit 200 and the compensation circuit cooperate to write the voltage value carrying the data signal and the threshold voltage information of the driving transistor in the driving circuit 100 into the control terminal 130 of the driving circuit 100 and store it through the storage circuit 300. Examples of specific compensation circuits, which are not described in detail herein.

The pixel circuit 10 provided by the embodiment of the disclosure can apply a reverse voltage difference to the light-emitting element 500 after the light-emitting element 500 emits light, thereby promoting elimination of the defect accumulated by the light-emitting element 500 in the positive voltage stage, so that the problem of aging of the light-emitting element 500 itself can be improved, thereby achieving the effect of prolonging the service life of the light-emitting element 500, and in the case of using the pixel circuit 10 in a display panel, no new signal needs to be added for the display panel, and the implementation is easy.

Fig. 3 is a circuit diagram of a specific implementation example of the pixel circuit shown in fig. 1. Referring to fig. 3, the pixel circuit 10 includes first to fourth transistors T1, T2, T3, T4, and includes a first capacitor C1, a second capacitor C2, and a light emitting element L1. For example, the second transistor T2 is used as a driving transistor, and the other transistors are used as switching transistors. For example, the light emitting element L1 may be various types of OLEDs, such as top emission, bottom emission, double-side emission, and the like, and may emit red light, green light, blue light, or white light, and the like, which is not limited by the embodiments of the present disclosure.

For example, as shown in fig. 3, the bias circuit 600 may be implemented as a first capacitor C1 and a first transistor T1 in more detail. A first pole of the first capacitor C1 is configured to be connected to the second terminal 520 (the second node N2) of the light emitting element L1, and a second pole of the first capacitor C1 is configured to be connected to the first pole of the first transistor T1. The gate of the first transistor T1 is configured to be connected to a bias enable line (bias enable terminal Vb) to receive a bias enable signal, and the second pole of the first transistor T1 is configured to be connected to a bias amplitude line (bias amplitude terminal Vamp) to receive a bias amplitude signal. It should be noted that, without limitation, the bias circuit 600 may be a circuit composed of other components.

The driving circuit 100 may be implemented as the second transistor T2. The gate of the second transistor T2 is connected to the first node N1 as the control terminal 130 of the driving circuit 100; a first pole of the second transistor T2 is connected as the first terminal 110 of the driving circuit 100 to the second node N2; the second pole of the second transistor T2 is connected as the second terminal 120 of the driving circuit 100 to the third node N3. It should be noted that, without being limited thereto, the driving circuit 100 may also be a circuit composed of other components, for example, the driving circuit 100 may have two sets of driving transistors, for example, the two sets of driving transistors may be switched according to specific situations.

The data write circuit 200 may be implemented as a third transistor T3. The gate of the third transistor T3 is configured to be connected to a scan line (scan signal terminal Vscan (N)) to receive a scan signal, the first pole of the third transistor T3 is configured to be connected to a data line (data signal terminal Vdata) to receive a data signal, and the second pole of the third transistor T3 is configured to be connected to the first node N1. Note that, without being limited thereto, the data writing circuit 200 may be a circuit including other components.

The memory circuit 300 may be implemented as a second capacitor C2. A first pole of the second capacitor C2 is configured to be coupled to a first node N1 as the first terminal 310 of the memory circuit 300, and a second pole of the second capacitor C2 is configured to be coupled to a second node N2 as the second terminal 320 of the memory circuit 300. It should be noted that, without being limited thereto, the memory circuit 300 may also be a circuit composed of other components, for example, the memory circuit 300 may include two capacitors connected in parallel/series with each other.

The reset circuit 400 may be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is configured to be connected to the reset line (reset terminal Rst) to receive the reset signal, the first pole of the fourth transistor T4 is connected to the control terminal 130 (first node N1) of the driving circuit 100, and the second pole of the fourth transistor T4 is configured to be connected to the first voltage terminal VSS (third node N3) to receive the first voltage signal (which may be a reset voltage). It should be noted that, without limitation, the reset circuit 400 may also be a circuit composed of other components, for example, the reset circuit 400 may also be connected to the second terminal 520 of the light emitting element 500 for further resetting (but not biasing) the second terminal 520 of the light emitting element 500.

The light emitting element 500 may be implemented as a light emitting element L1 (e.g., OLED). A first terminal (here, an anode) of the light emitting element L1 is configured to be connected to the second voltage terminal VDD as the first terminal 510 of the light emitting element 500 to receive the second voltage signal, and a second terminal (here, a cathode) of the light emitting element L1 is connected to the second node N2 as the second terminal 520 of the light emitting element 500 and configured to receive the driving current from the first terminal 110 of the driving circuit 100. For example, the second voltage terminal VDD holds the input dc high level signal, i.e., VDD may be high level. For example, in a display panel, when the pixel circuits 10 are arranged in an array, the anodes of the light emitting elements L1 may be electrically connected to the same voltage terminal, i.e., a common anode connection mode is adopted.

Note that in the description of the present disclosure, the first node N1, the second node N2, and the third node N3 do not represent actually existing components, but represent junctions of relevant electrical connections in a circuit diagram.

Fig. 4 is a circuit diagram of a specific implementation example of the pixel circuit shown in fig. 2. The pixel circuit 10 shown in fig. 4 is substantially the same as the pixel circuit 10 shown in fig. 3, except that the pixel circuit 10 shown in fig. 4 further includes a fifth transistor T5 to realize a light emission control circuit 700.

For example, as shown in fig. 4, the light emission control circuit 700 may be implemented as a fifth transistor T5 in more detail. The gate of the fifth transistor T5 is configured to be connected to a light emission control line (light emission control terminal Em) to receive a light emission control signal, the first pole of the fifth transistor T5 is configured to be connected to the second voltage terminal VDD to receive a second voltage signal, and the second pole of the fifth transistor T5 is configured to be connected to the first terminal of the light emitting element L1. Note that, without being limited to this, the light emission control circuit 700 may be a circuit including other components.

Fig. 5 is a signal timing diagram of a pixel circuit according to an embodiment of the disclosure. The operation principle of the pixel circuit 10 shown in fig. 3 is described below with reference to a signal timing chart shown in fig. 5, and each transistor is an N-type transistor as an example, but the embodiment of the present disclosure is not limited thereto.

As shown in fig. 5, the display process of each frame image includes three stages, a reset stage 1, a bias stage 2, and a data write stage 3, which show the timing waveforms of the respective signals in each stage.

Fig. 6A to 6C are schematic diagrams of the pixel circuit 10 shown in fig. 3 at the three stages. Fig. 6A is a schematic diagram of the pixel circuit 10 shown in fig. 3 in a reset phase 1, fig. 6B is a schematic diagram of the pixel circuit 10 shown in fig. 3 in a bias phase 2, and fig. 6C is a schematic diagram of the pixel circuit 10 shown in fig. 3 in a data writing phase 3.

In addition, the transistors identified by dotted lines in fig. 6A to 6C each indicate an off state in the corresponding stage, and the dotted lines with arrows in fig. 6A to 6C indicate the direction of current flow in the pixel circuit in the corresponding stage. The transistors shown in fig. 6A to 6C are each illustrated as an N-type transistor, i.e., the gate of each transistor is turned on when a high level is turned on and is turned off when a low level is turned on. The following examples are the same and will not be described in detail.

In the reset phase 1, a reset signal (provided by the reset terminal Rst) is input to turn on the reset circuit 400, and the reset circuit 400 applies a reset voltage (provided by the first voltage terminal VSS) to the control terminal 130 of the driving circuit 100 and the first terminal 310 of the memory circuit 300 to reset the driving circuit 100 and the memory circuit 300.

As shown in fig. 5 and 6A, in the reset phase 1, the fourth transistor T4 is turned on by the high level of the reset signal; meanwhile, the first transistor T1 is turned off by the low level of the bias enable signal, the third transistor T3 is turned off by the low level of the scan signal, and the second transistor T2 is turned off by the low level of the first node N1.

As shown in fig. 6A, in the reset phase 1, a reset path (as shown by a dotted line with an arrow in fig. 6A) is formed, and since the fourth transistor T4 is turned on, a reset voltage may be applied to the gate (the first node N1) of the second transistor T2 and the first pole of the second capacitor C2. Since the reset voltage is a low signal (e.g., may be ground or other low signal), the second capacitor C2 discharges through the reset path, thereby resetting the second transistor T2 and the second capacitor C2. For example, in a display device, when the pixel circuits 10 are arranged in an array, the gate of the third transistor T3 of the nth row (N is an integer greater than 2) is connected to the scan line (scan signal terminal Vscan (N)) of the nth row to receive the scan signal, and the gate of the fourth transistor T4 of the nth row is connected to the scan line (scan signal terminal Vscan (N-2)) of the nth-2 row to receive the scan signal of the nth-2 row as the reset signal. Compared with the traditional display panel, the mode does not need to add new signals, and the circuit structure is simple and easy to realize.

After the reset phase 1, the potential of the first node N1 is the reset voltage. The second capacitor C2 is reset to discharge the charges stored in the second capacitor C2, so that the data signal in the subsequent stage can be stored in the second capacitor C2 more rapidly and reliably. Meanwhile, since the second transistor T2 is turned off, the light emitting element L1 is also reset, so that the light emitting element L1 can be made to display a black state without emitting light before the data writing stage 3, thereby improving display effects such as contrast of a display device using the pixel circuit 10.

In the bias phase 2, a bias enable signal (provided from the bias enable terminal Vb) is input to turn on the bias circuit 600, and the bias circuit 600 applies a bias voltage to the second terminal (the second node N2) of the light emitting element L1 according to the bias amplitude signal (provided from the bias amplitude terminal Vamp) to reverse-bias the light emitting element L1.

As shown in fig. 5 and 6B, in the bias phase 2, the first transistor T1 is turned on by the high level of the bias enable signal; meanwhile, the second transistor T2 is turned off by the low level of the first node N1, the third transistor T3 is turned off by the low level of the scan signal, and the fourth transistor T4 is turned off by the low level of the reset signal.

As shown in fig. 6B, in the bias stage 2, a bias path (as shown by the dotted line with an arrow in fig. 6B) is formed, and since the first transistor T1 is turned on, a bias amplitude signal can be applied to the second pole of the first capacitor C1. The first capacitor C1 is charged during the display period of the previous frame image, and the first pole (the second node N2) of the first capacitor C1 and the second pole of the first capacitor C1 reach the potential balance. When the bias amplitude signal is applied to the second pole of the first capacitor C1, the potential of the first pole (the second node N2) of the first capacitor C1 is raised due to the bootstrap effect of the first capacitor C1, so that the potential of the second node N2 is greater than VDD. Therefore, the application of the bias voltage to the light-emitting element L1 can promote the elimination of the defect accumulated in the light-emitting stage (positive voltage stage) of the light-emitting element L1 in the previous frame image, thereby improving the aging problem of the light-emitting element L1 itself and extending the service life of the light-emitting element L1. For example, in a display device, when the pixel circuits 10 are arranged in an array, the gate of the third transistor T3 of the nth row (N is an integer greater than 1) is connected to the scan line (scan signal terminal Vscan (N)) of the nth row to receive the scan signal, and the gate and/or the second pole of the first transistor T1 of the nth row is connected to the scan line (scan signal terminal Vscan (N-1)) of the nth row to receive the scan signal of the nth-1 row as the bias enable signal and/or the bias amplitude signal. Compared with the traditional display panel, the mode does not need to add new signals, and the circuit structure is simple and easy to realize.

After the bias phase 2, the potential of the second node N2 is a bias voltage. The light-emitting element L1 is reverse-biased, so that defects accumulated at the positive voltage stage can be eliminated, and the service life of the light-emitting element L1 can be effectively prolonged. Moreover, since the high level time of the bias enable signal is short and smaller than the resolution capability of human eyes, the display effect of the display device using the pixel circuit 10 is not affected.

In the data writing stage 3, a scan signal (supplied from the scan signal terminal Vscan (n)) and a data signal (supplied from the data signal terminal Vdata) are input to turn on the data writing circuit 200 and the driving circuit 100, the data writing circuit 200 writes the data signal into the driving circuit 100, the memory circuit 300 stores the data signal, and the light emitting element L1 emits light in accordance with the driving current.

As shown in fig. 5 and 6C, in the data write phase 3, the third transistor T3 is turned on by the high level of the scan signal, and the second transistor T2 is turned on by the high level of the first node N1; meanwhile, the first transistor T1 is turned off by the low level of the bias enable signal, and the fourth transistor T4 is turned off by the low level of the reset signal.

As shown in fig. 6C, in the data writing phase 3, a data writing path (as shown by the dotted line with an arrow in fig. 6C) is formed, and the data signal passes through the third transistor T3 to charge the second capacitor C2. When the voltage difference between the first node N1 and the second node N2 is greater than Vth, the second transistor T2 is turned on, so that the light emitting element L1 emits light by the driving current. It should be noted that Vth represents the threshold voltage of the second transistor T2, and since the second transistor T2 is an N-type transistor in this embodiment, the threshold voltage Vth may be a positive value here. In other embodiments, if the second transistor T2 is a P-type transistor, the threshold voltage Vth may be a negative value.

Specifically, the driving current I flowing through the light emitting element L1_L1The value of (d) can be obtained according to the following formula:

I_L1＝K(V_GS–Vth)²

in the above equation, Vth represents the threshold voltage of the second transistor T2, V_GSRepresenting the voltage between the gate and source (here the first pole) of the second transistor T2, K is a constant value associated with the second transistor T2 itself. From this, the driving current I flowing through the light emitting element L1 is shown_L1And V_GSIn this regard, the light emitting element L1 may emit light according to the data signal stored in the second capacitor C2.

After the data writing phase 3, the voltage information with the data signal is stored in the second capacitor C2, and the second transistor T2 supplies the driving current to the light emitting element L1 under the control of the voltage difference between the first node N1 and the second node N2, so that the light emitting element L1 emits light. In this embodiment, in the data writing stage 3, the pixel circuit 10 emits light while writing a data signal. In other embodiments, in combination with a specific circuit structure, data writing and light emitting may also be implemented in two stages, respectively, and the embodiments of the present disclosure are not limited thereto.

Fig. 7 is a signal timing diagram of another pixel circuit according to an embodiment of the disclosure. Referring to fig. 7, the signal timing is substantially the same as that shown in fig. 5 except that a light emitting stage 4 is further included. The operation principle of the pixel circuit 10 shown in fig. 4 will be described below with reference to the signal timing diagram shown in fig. 7, and each transistor is an N-type transistor as an example, but the embodiment of the present disclosure is not limited thereto.

Fig. 8 is a circuit diagram of the pixel circuit 10 shown in fig. 4 corresponding to the lighting phase 4 in fig. 7. The transistors identified by the dashed lines in fig. 8 each indicate an off state in the corresponding stage, and the dashed lines with arrows in fig. 8 indicate the direction of current flow in the pixel circuit 10 in the corresponding stage. The reset phase 1, the bias phase 2 and the data writing phase 3 are basically the same as the operation principle of the pixel circuit 10 shown in fig. 5 and fig. 6A to 6C, and are not described again here.

In the light-emitting phase 4, a light-emission control signal (supplied from the light-emission control terminal Em) is input to turn on the light-emission control circuit 700 and the drive circuit 100, and the light-emission control circuit 700 and the drive circuit 100 apply a drive current to the light-emitting element L1 to cause it to emit light.

As shown in fig. 7 and 8, in the lighting phase 4, the fifth transistor T5 is turned on by the high level of the lighting control signal, and the second transistor T2 is turned on by the high level of the first node N1; meanwhile, the first transistor T1 is turned off by the low level of the bias enable signal, the third transistor T3 is turned off by the low level of the scan signal, and the fourth transistor T4 is turned off by the low level of the reset signal.

As shown in fig. 8, in the light emitting stage 4, a driving light emitting path (as shown by a dotted line with an arrow in fig. 8) is formed, and since the fifth transistor T5 and the second transistor T2 are turned on, a driving current can be supplied to the light emitting element L1, and the light emitting element L1 emits light by the driving current.

In this embodiment, the light-emitting element L1 emits light only in the light-emitting phase 4, and does not emit light in the data writing phase 3. The data writing and the light emitting are respectively realized in two stages, which is beneficial to ensuring the integrity of the data writing and can improve the contrast of the corresponding display device.

Note that the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are used as examples in the embodiments of the present disclosure. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is directly described as a second pole.

In addition, the transistors in the pixel circuits 10 shown in fig. 3 and 4 are both illustrated as N-type transistors, and in this case, the first electrode may be a source electrode and the second electrode may be a drain electrode. The transistors in the pixel circuit 10 may also be only P-type transistors or a mixture of P-type transistors and N-type transistors, and only the port polarities of the selected transistors are connected according to the port polarities of the corresponding transistors in the embodiment of the present disclosure. When an N-type transistor is used, Indium Gallium Zinc Oxide (IGZO) may be used as an active layer of the thin film transistor, which may effectively reduce the size of the transistor and prevent leakage current, compared to using Low Temperature Polysilicon (LTPS) or amorphous Silicon (e.g., hydrogenated amorphous Silicon) as an active layer of the thin film transistor.

At least one embodiment of the present disclosure further provides a display panel, which includes a plurality of pixel units distributed in an array, where each pixel unit includes the pixel circuit according to any one of the embodiments of the present disclosure. The pixel circuit in the display panel can load reverse voltage difference to the OLED after the OLED emits light, so that the defect of accumulation of the OLED in a positive voltage stage is eliminated, the aging problem of the OLED device can be improved, the effect of prolonging the service life of the OLED device is achieved, and the display panel is easy to realize without adding new signals.

Fig. 9 is a schematic block diagram of a display panel according to an embodiment of the disclosure. Referring to fig. 9, the display panel 2000 is disposed in the display device 20 and is electrically connected to a gate driver 2010 and a data driver 2030. The display device 20 also includes a timing controller 2020. The display panel 2000 includes pixel cells P defined by intersections of a plurality of scan lines GL and a plurality of data lines DL; the gate driver 2010 is configured to drive a plurality of scanning lines GL; the data driver 2030 is for driving a plurality of data lines DL; the timing controller 2020 is configured to process image data RGB externally input from the display device 20, supply the processed image data RGB to the data driver 2030, and output a scan control signal GCS and a data control signal DCS to the gate driver 2010 and the data driver 2030 to control the gate driver 2010 and the data driver 2030.

For example, the display panel 2000 includes a plurality of pixel units P, and the pixel units P include the pixel circuit 10 provided in any of the above embodiments. For example, a pixel circuit 10 as shown in fig. 3 is included. For example, a pixel circuit as shown in fig. 4 may also be included. As shown in fig. 9, the display panel 2000 further includes a plurality of scan lines GL and a plurality of data lines DL. For example, the pixel unit P is disposed at an intersection region of the scan line GL and the data line DL. For example, each pixel unit P is connected to two scan lines GL (to which a scan signal and a light emission control signal are supplied, respectively), one data line DL, a first voltage line for supplying a first voltage signal, and a second voltage line for supplying a second voltage signal. For example, the first voltage line or the second voltage line may be replaced with a corresponding plate-shaped common electrode (e.g., a common anode or a common cathode). In fig. 9, only a part of the pixel unit P, the scanning line GL, and the data line DL is shown.

For example, the gate driver 2010 supplies a plurality of gate signals to the plurality of scan lines GL according to a plurality of scan control signals GCS from the timing controller 2020. The plurality of gate signals include a scan signal, a light emission control signal, and the like. These signals are supplied to each pixel unit P through a plurality of scanning lines GL.

For example, the data driver 2030 converts digital image data RGB input from the timing controller 2020 into data signals according to a plurality of data control signals DCS supplied from the timing controller 2020 using a reference gamma voltage. The data driver 2030 supplies the converted data signals to the plurality of data lines DL.

For example, the timing controller 2020 processes externally input image data RGB to match the size and resolution of the display panel 2000 and then supplies the processed image data to the data driver 2030. The timing controller 2020 generates a plurality of scan control signals GCS and a plurality of data control signals DCS using synchronization signals (e.g., a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) externally input from the display device 20. The timing controller 2020 provides the generated scan control signal GCS and the data control signal DCS to the gate driver 2010 and the data driver 2030, respectively, for control of the gate driver 2010 and the data driver 2030.

For example, the data driver 2030 may be connected with a plurality of data lines DL to supply data signals; and may be connected to the first voltage lines and the second voltage lines to supply the first voltage signal and the second voltage signal, respectively.

For example, the gate driver 2010 and the data driver 2030 may be implemented as a semiconductor chip. The display device 20 may further comprise other components, such as a signal decoding circuit, a voltage converting circuit, etc., which may be conventional components, for example, and will not be described in detail herein.

For example, the display panel 2000 may be applied to any product or component with a display function, such as an electronic book, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

Fig. 10 is a schematic block diagram of another display panel provided in an embodiment of the present disclosure. Referring to fig. 10, a plurality of pixel units P are arranged in a plurality of rows, and only a specific connection relationship of the pixel units P in the exemplary region 3000 is shown in the figure, and other pixel units P have a similar connection relationship.

For example, the data write circuit 200 in the pixel circuit 10 of the pixel unit P of the nth (N is an integer greater than 2) row (the pixel unit P in the exemplary region 3000) is connected to one scan lineTrace GL (i.e. S)_N) And the reset circuit 400 in the pixel circuits 10 of the pixel units P of the nth row is connected to the other scan line GL (i.e., S)_N-2). For example, the other scanning line GL (i.e. S)_N-2) And also to the data writing circuit 200 in the pixel circuit 10 of the pixel unit P of the N-2 th row. Here, the data writing circuit 200 is not specifically shown in the drawing. Through the mode of signal multiplexing, need not to increase new signal, circuit structure is simple, easily realizes.

For another example, as shown in fig. 10, the data writing circuit 200 in the pixel circuit 10 of the pixel unit P in the nth (N is an integer greater than 1) row is connected to one scanning line GL (i.e., S)_N) And the bias circuit 600 in the pixel circuits 10 of the pixel units P of the nth row is connected to the other scan line GL (i.e., S)_N-1). For example, the other scanning line GL (i.e. S)_N-1) And also connected to the data writing circuit 200 in the pixel circuit 10 of the pixel unit P of the N-1 th row.

For example, the data line DL (i.e., D) of each column_M、D_M-1、D_M-2) And the data writing circuit 200 in the present column of pixel circuits 10 to supply data signals.

At least one embodiment of the present disclosure also provides a driving method, which may be used to drive the pixel circuit 10 provided by the embodiment of the present disclosure. According to the driving method, after the OLED emits light, reverse pressure difference can be loaded on the OLED, the defect that the OLED accumulates in a positive pressure stage is eliminated, and therefore the aging problem of the OLED device can be improved, the service life of the OLED device is prolonged, a new signal does not need to be added for a display panel, and the driving method is easy to achieve.

For example, the driving method includes the operations of:

in the bias phase, a bias start signal is input to turn on the bias circuit 600, and the bias circuit 600 applies a bias voltage to the second terminal 520 of the light emitting element 500 according to the bias amplitude signal to reverse bias the light emitting element 500;

in the data writing stage, a scan signal and a data signal are input to turn on the data writing circuit 200 and the driving circuit 100, the data writing circuit 200 writes the data signal into the driving circuit 100, the storage circuit 300 stores the data signal, and the light emitting element 500 emits light according to the driving current.

For example, in the case where the pixel circuit 10 further includes the reset circuit 400, the driving method further includes a reset phase. In the reset phase, a reset signal is input to turn on the reset circuit 400, and the reset circuit 400 applies a reset voltage to the control terminal 130 of the driving circuit 100 and the first terminal 310 of the memory circuit 300 to reset the driving circuit 100 and the memory circuit 300.

For example, in the case where the pixel circuit 10 further includes the light emission control circuit 700, the driving method further includes a light emission phase. In the light emitting stage, a light emitting control signal is input to turn on the light emitting control circuit 700 and the driving circuit 100, and the light emitting control circuit 700 and the driving circuit 100 apply a driving current to the light emitting element 500 to emit light. For example, in the case where the pixel circuit 10 further includes the light emission control circuit 700, the light emitting element 500 does not emit light in the data writing phase.

It should be noted that, for a detailed description of the driving method, reference may be made to the description of the working principle of the pixel circuit 10 in the embodiment of the present disclosure, and details are not repeated here.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A pixel circuit, comprising: a drive circuit, a data write circuit, a memory circuit, a light emitting element, and a bias circuit; wherein,

the driving circuit comprises a control end, a first end and a second end and is configured to control a driving current for driving the light-emitting element to emit light, and the second end of the driving circuit receives a first voltage signal of a first voltage end;

the data writing circuit is connected with the control end of the driving circuit and is configured to write a data signal into the control end of the driving circuit in response to a scanning signal;

the first end of the storage circuit is connected with the control end of the driving circuit, the second end of the storage circuit is connected with the first end of the driving circuit, and the storage circuit is configured to store the data signal written by the data writing circuit;

the first end of the light-emitting element receives a second voltage signal of a second voltage end, and the second end of the light-emitting element is connected with the first end of the driving circuit and is configured to emit light according to the driving current;

the bias circuit is connected with the second end of the light-emitting element and is configured to respond to a bias starting signal and apply a bias voltage to the second end of the light-emitting element according to a bias amplitude signal so as to reversely bias the light-emitting element.

2. The pixel circuit according to claim 1, wherein the bias circuit comprises a first capacitor and a first transistor;

a first electrode of the first capacitor is connected to the second end of the light emitting element, and a second electrode of the first capacitor is connected to the first electrode of the first transistor;

the gate of the first transistor is configured to be connected to a bias enable line to receive the bias enable signal, and the second pole of the first transistor is configured to be connected to a bias magnitude line to receive the bias magnitude signal.

3. The pixel circuit according to claim 1, wherein the driver circuit comprises a second transistor;

the grid electrode of the second transistor is used as the control end of the driving circuit, the first pole of the second transistor is used as the first end of the driving circuit, and the second pole of the second transistor is used as the second end of the driving circuit.

4. The pixel circuit according to claim 1, wherein the data writing circuit comprises a third transistor;

the gate of the third transistor is configured to be connected to a scan line to receive the scan signal, the first pole of the third transistor is configured to be connected to a data line to receive the data signal, and the second pole of the third transistor is configured to be connected to the control terminal of the driving circuit.

5. The pixel circuit according to claim 1, wherein the storage circuit comprises a second capacitance;

the first pole of the second capacitor is used as the first end of the storage circuit, and the second pole of the second capacitor is used as the second end of the storage circuit.

6. The pixel circuit according to claim 1, further comprising a reset circuit,

the reset circuit is connected with the control terminal of the driving circuit and is configured to apply a reset voltage to the control terminal of the driving circuit in response to a reset signal.

7. The pixel circuit according to claim 6, wherein the reset circuit comprises a fourth transistor;

a gate of the fourth transistor is configured to be connected to a reset line to receive the reset signal, a first pole of the fourth transistor is configured to be connected to the control terminal of the driving circuit, and a second pole of the fourth transistor is configured to be connected to a first voltage terminal to receive the reset voltage.

8. The pixel circuit according to claim 1, further comprising a light emission control circuit,

the light emission control circuit is connected to the first terminal of the light emitting element and configured to apply a second voltage signal of the second voltage terminal to the first terminal of the light emitting element in response to a light emission control signal.

9. The pixel circuit according to claim 8, wherein the light emission control circuit comprises a fifth transistor;

a gate of the fifth transistor is configured to be connected to a light emission control line to receive the light emission control signal, a first pole of the fifth transistor is configured to be connected to the second voltage terminal to receive the second voltage signal, and a second pole of the fifth transistor is configured to be connected to the first terminal of the light emitting element.

10. A display panel comprising a plurality of pixel cells arranged in an array, the pixel cells comprising the pixel circuit of any one of claims 1-9.

11. The display panel according to claim 10, further comprising a plurality of scan lines, wherein the data writing circuit in the pixel circuit in the nth row is connected to the scan line in the nth row to receive the scan signal, the bias circuit in the pixel circuit in the nth row is connected to the scan line in the N-1 th row to receive the scan signal in the N-1 th row as the bias enable signal and/or the bias amplitude signal, and N is an integer greater than 1.

12. The display panel according to claim 11, wherein the reset circuit in the pixel circuit of the nth row is connected to the scan line of the N-2 nd row to receive the scan signal of the N-2 nd row as a reset signal, N being an integer greater than 2.