CN207946806U - A kind of debugger and debugging apparatus - Google Patents
A kind of debugger and debugging apparatus Download PDFInfo
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- CN207946806U CN207946806U CN201820161850.3U CN201820161850U CN207946806U CN 207946806 U CN207946806 U CN 207946806U CN 201820161850 U CN201820161850 U CN 201820161850U CN 207946806 U CN207946806 U CN 207946806U
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Abstract
The embodiment of the present application provides a kind of debugger and debugging apparatus, is related to technical field of electronic equipment.The embodiment of the present application in debugger by being arranged processor, and processor is connect with instruction input interface and debugging interface respectively, debugging interface is also connected with the debugging interface of mainboard, instruction input interface is also connected with the instruction output interface of terminal, processor can set the debugging interface of debugger to jtag interface or EJTAG interfaces, so that terminal debugs mainboard by jtag interface or EJTAG interfaces.By processor debugging interface is set to EJTAG patterns or JTAG mode, it can be achieved that debugger is to the EJTAG interfaces of mainboard or the access of jtag interface, and then realizes different debugging functions.
Description
Technical field
The utility model is related to technical field of electronic equipment, more particularly to a kind of debugger and debugging apparatus.
Background technology
Mainboard, during carrying out software debugging and fault location, it usually needs use JTAG (Joint Test
Action Group, joint test working group) interface and EJTAG (Enhanced Joint Test Action Group, enhancing
Joint test working group) interface；Wherein, it can scan to obtain what register included in processor stored by jtag interface
Value, to realize that the fault in-situ to processor is analyzed；Register included in processor can be carried out by EJTAG interfaces
Read-write operation, to realize software debugging and fault location.
As shown in Figure 1, USB can be passed through during carrying out software debugging and fault location to mainboard at present
(Universal Serial Bus, universal serial bus) EJTAG debuggers connect terminal and mainboard, USB EJTAG debuggers
The signal conversion being responsible between terminal and mainboard；Linux (operating system) is installed in the terminal, and dedicated debugging is installed
Software is responsible for debugging mainboard.
But existing USB EJTAG debuggers only have a kind of debugging interface, i.e. EJTAG interfaces, therefore can only also accomplish
It accesses to the EJTAG interfaces of mainboard, cannot achieve the access to the jtag interface of mainboard.
Utility model content
In view of the above problems, it is proposed that the embodiment of the present application overcoming the above problem or at least partly in order to provide one kind
A kind of debugger and debugging apparatus to solve the above problems, can only be accomplished with solving existing USB EJTAG debuggers to mainboard
EJTAG interfaces the problem of accessing, cannot achieve the access to the jtag interface of mainboard.
To solve the above-mentioned problems, the embodiment of the present application discloses a kind of debugger, including：Processor, debugging interface and
Instruction input interface；
The processor is connect with described instruction input interface and the debugging interface respectively, and the debugging interface is also connected with
The debugging interface of mainboard, described instruction input interface are also connected with the instruction output interface of terminal；
The processor, for setting the debugging interface of the debugger to joint test working group jtag interface or increasing
Strong joint test working group EJTAG interfaces so that the terminal by the jtag interface or the EJTAG interfaces to the master
Plate is debugged.
Optionally, the processor includes general I/O port GPIO (General Purpose Input
Output, general I/O port) interface, the processor is by the GPIO interface by the debugging interface of the debugger
It is set as jtag interface or EJTAG interfaces.
Optionally, the debugger further includes memory；
The memory, for loading BIOS (Basic Input Output System, basic input output system) system
System program, operating system program and application program, the application program include JTAG drivers and EJTAG drivers.
Optionally, the memory is Synchronous Dynamic Random Access Memory chip.
Optionally, described instruction input interface is any one in network interface, USB port, serial ports and parallel port.
Optionally, the debugging interface of the debugger is connect with the debugging interface of the mainboard by interface connecting line.
Optionally, the processor is MIPS (Microprocessor without interlocked piped
Stages, the microprocessor of no inner interlocked pipelining-stage) architecture processor.
To solve the above-mentioned problems, the embodiment of the present application also discloses a kind of debugging apparatus, including terminal and above-mentioned tune
Try device.
The embodiment of the present application includes the following advantages：
By the way that processor is arranged in debugger, and processor is connect with instruction input interface and debugging interface respectively, is adjusted
Mouth of trying is also connected with the debugging interface of mainboard, and instruction input interface is also connected with the instruction output interface of terminal, and processor can will be adjusted
Examination device debugging interface be set as jtag interface or EJTAG interfaces so that terminal by jtag interface or EJTAG interfaces to mainboard
It is debugged.When debugging interface is connected to the jtag interface of mainboard, the attribute of debugging interface is set by processor, will be debugged
Interface is set as jtag interface, it can be achieved that access of the debugger to the jtag interface of mainboard；When debugging interface is connected to mainboard
When EJTAG interfaces, the attribute of debugging interface is set by processor, sets debugging interface to EJTAG interfaces, it can be achieved that debugging
Access of the device to the EJTAG interfaces of mainboard, and then realize different debugging functions.
Description of the drawings
Fig. 1 shows the connection diagram of existing USB EJTAG debuggers；
Fig. 2 shows a kind of structural schematic diagrams of debugger of the embodiment of the present application；
Fig. 3 shows a kind of connection diagram of debugger of the embodiment of the present application；
Fig. 4 shows the structural schematic diagram of another debugger of the embodiment of the present application.
Specific implementation mode
In order to make the above objects, features, and advantages of the present application more apparent, below in conjunction with the accompanying drawings and it is specific real
Applying mode, the present application will be further described in detail.
Embodiment one
With reference to Fig. 2, a kind of structural schematic diagram of debugger of the embodiment of the present application is shown.
The embodiment of the present application provides a kind of debugger 20, including processor 21, debugging interface 22 and instruction input interface
23；Processor 21 is connect with instruction input interface 23 and debugging interface 22 respectively, and the debugging that debugging interface 22 is also connected with mainboard connects
Mouthful, instruction input interface 23 is also connected with the instruction output interface of terminal；Processor 21 is used for the debugging interface 22 of debugger 20
It is set as jtag interface or EJTAG interfaces, so that terminal debugs mainboard by jtag interface or EJTAG interfaces.
It should be noted that the jtag interface of debugger 20 is identical with the hardware configuration of EJTAG interfaces, there are five draw
Foot, including TCK pin, TDI pins, TDO pins, TMS pin and TRST pins therefore can be by jtag interfaces and EJTAG interfaces
Compatible is a debugging interface 22.Wherein, in jtag interface, TCK pin is used for the input of test clock, and TDI pins are used for
The input of test data, test data input jtag interface by TDI pins, and TDO pins are used for the output of test data, test
Data are exported by TDO pins from jtag interface, and TMS pin is selected for test pattern, certain is in for jtag interface is arranged
The specific test pattern of kind, TRST pins are used for test reset, are input pins, low level is effective；In EJTAG interfaces, TCK
Pin is used for the input of test clock, and TDI pins are used for the input of test data, and test data inputs EJTAG by TDI pins
Interface, TDO pins are used for the output of test data, and test data is exported by TDO pins from EJTAG interfaces, and TMS pin is used for
Test pattern selects, and for EJTAG interfaces are arranged in certain specific test pattern, TRST pins are used for test reset, are
Input pin, low level are effective.
With reference to Fig. 3, a kind of connection diagram of debugger of the embodiment of the present application is shown.
It is respectively arranged with jtag interface and EJTAG interfaces in mainboard 30, is additionally provided with processor certainly, passes through mainboard 30
EJTAG interfaces the register in processor can be written and read, to facilitate software debugging, fault recurrence and positioning, use
The jtag interface of mainboard 30, which can scan the value of all registers in processor, to be come, and is analyzed for fault in-situ.
When needing the EJTAG interfaces by mainboard 30 to debug mainboard 30, by the EJTAG interfaces of mainboard 30 and tune
The debugging interface 22 for trying device 20 connects, it is also necessary to by the instruction input interface 23 of the instruction output interface and debugger 20 of terminal 40
Connection, terminal 40 are referred to by instructing the processor 21 of output interface and instruction input interface 23 into debugger 20 to send operation
It enables, processor 21 sets debugging interface 22 to EJTAG interfaces, to be connect by EJTAG by the attribute of setting debugging interface 22
The existing access to mainboard 30 of cause for gossip, to be written and read to the register of the processor in mainboard 30, to facilitate software debugging, therefore
Barrier reappears and positioning.
When needing the jtag interface by mainboard 30 to debug mainboard 30, by the jtag interface of mainboard 30 and debugging
The debugging interface 22 of device 20 connects, and the instruction output interface of terminal 40 is connect with the instruction input interface 23 of debugger 20, eventually
End 40 is by instructing the processor 21 of output interface and instruction input interface 23 into debugger 20 to send operational order, processor
21 by be arranged debugging interface 22 attribute, set debugging interface 22 to jtag interface, with by jtag interface realize to master
The access of plate 30 carries out fault in-situ analysis to scan the value of all registers in the processor of mainboard 30.
Wherein, processor 21 includes GPIO interface, and processor 21 is by GPIO interface by the debugging interface 22 of debugger 20
It is set as jtag interface or EJTAG interfaces.
Specifically, be configured to the pin attribute in debugging interface 22 by the GPIO interface in processor 21, it will
Debugging interface 22 is set as jtag interface or EJTAG interfaces.
Wherein, the debugging interface 22 of debugger 20 is connect with the debugging interface of mainboard 30 by interface connecting line.Debugging connects
Mouth 22 can be connect with the jtag interface of mainboard 30 by interface connecting line, and debugging interface 22 also can be with the EJTAG interfaces of mainboard 30
It is connected by interface connecting line.
Instruction input interface 23 is any one in network interface, USB port, serial ports and parallel port, certainly, is also connect using other
Mouthful, as long as ensureing that interface can be communicated with terminal 40.
As shown in Figures 2 and 3, when instruction input interface 23 is network interface, debugger 20 can pass through network interface and terminal 40
Be attached, by network interface connection mode realize debugger 20 remote access and control, it can be achieved that terminal 40 to mainboard 30
Remote debugging；When instruction input interface 23 is USB port, debugger 20 can be attached by USB port and terminal 40, be passed through
Local IP access and the control of USB port connection type realization debugger 20 are, it can be achieved that terminal 40 debugs the local of mainboard 30.
Certainly, debugger 20 can be also attached by serial ports and terminal 40, and serial ports is also referred to as serial line interface, be using serial
The expansion interface of communication mode；Debugger 20 can also be attached by parallel port and terminal 40, and parallel port is also referred to as parallel interface, is
Using the expansion interface of parallel communication fashion.
With reference to Fig. 4, the structural schematic diagram of another debugger of the embodiment of the present application is shown.
On the basis of Fig. 2, the debugger 20 of the embodiment of the present application further includes memory 24；Memory is for loading BIOS
System program, operating system program and application program, application program include JTAG drivers and EJTAG drivers.
Wherein, BIOS system program includes self-check program and system self-starting journey after the program of basic input and output, booting
Sequence provides the bottom, most direct hardware setting and control for debugger 20, and BIOS system program is the booting power-up of debugger 20
First afterwards starts the program executed, can complete to carry out the work(such as Initialize installation and test to the hardware device in debugger 20
Can, it to ensure that debugger 20 can work normally, is stopped immediately if hardware device is abnormal, and the equipment of error is believed
Breath feeds back to user, to improve the reliability of debugger.
It is stored with operating system program in memory 24, it therefore, can installation operation system be (such as on debugger 20
Linux system), correspondingly, without installation operation system again in terminal 40, requiring nothing more than terminal 40 has network interface, USB port, serial ports
With any one in parallel port, shirtsleeve operation instruction can be sent to debugger 20.Therefore, it is installed on debugger 20
Operating system is not limited to linux system, and certain operating system can also be Windows systems etc., the requirement drop to terminal 40
It is low, as long as being equipped with terminal class application program in terminal 40, shirtsleeve operation instruction, the application can be sent to debugger 20
In debugger 20 the scope of application it is wider.
It is additionally provided with application program in memory 24, which includes JTAG drivers and EJTAG driving journeys
Sequence.It, can when setting debugging interface 22 to EJTAG interfaces when processor 21 needs the attribute to debugging interface 22 to be configured
The EJTAG drivers stored in memory 24 are transferred by processor 21, by running EJTAG drivers by debugging interface
22 are set as EJTAG interfaces；When processor 21 needs the attribute to debugging interface 22 to be configured, set debugging interface 22 to
When jtag interface, the JTAG drivers stored in memory 24 can be transferred by processor 21, and journey is driven by running JTAG
Sequence sets debugging interface 22 to jtag interface.
In the embodiment of the present application, debugger 20 can also include power module, power module respectively with processor 21, adjust
Try mouth 22 and instruction input interface 23 is electrically connected, for powering to processor 21, debugging interface 22 and instruction input interface 23.
Certainly, power module is also electrically connected with memory 24, for powering to memory 24.By the power supply function of power module, protect
Card debugger 20 can work normally.
Wherein, the processor 21 in debugger 20 is MIPS architecture processors, such as No. 1 processor of Godson, Godson-2 processing
Device etc. also uses the processor of other models, such as SOC (System On Chip, system level chip), FPGA (Field certainly
Programmable Gate Array, field programmable gate array) etc., the embodiment of the present application is without limitation.
Memory 24 in debugger 20 is Synchronous Dynamic Random Access Memory chip, alternatively referred to as SDRAM
(Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) chip.
In the embodiment of the present application, by being arranged processor in debugger, and processor respectively with instruction input interface
It is connected with debugging interface, debugging interface is also connected with the debugging interface of mainboard, and instruction input interface is also connected with the instruction output of terminal
Interface, processor can set the debugging interface of debugger to jtag interface or EJTAG interfaces, so that terminal passes through jtag interface
Or EJTAG interfaces debug mainboard.When debugging interface is connected to the jtag interface of mainboard, it is arranged by processor and is debugged
The attribute of interface sets debugging interface to jtag interface, it can be achieved that access of the debugger to the jtag interface of mainboard；Work as debugging
When interface is connected to the EJTAG interfaces of mainboard, the attribute of debugging interface is set by processor, sets debugging interface to
EJTAG interfaces realize different debugging functions, it can be achieved that access of the debugger to the EJTAG interfaces of mainboard.
Embodiment two
The embodiment of the present application also provides a kind of debugging apparatus, including terminal 40 and above-mentioned debugger 20.
The description of embodiment one is referred to about the specific descriptions of debugger 20, the embodiment of the present application is no longer superfluous to this
It states.
In the embodiment of the present application, by being arranged processor in debugger, and processor respectively with instruction input interface
It is connected with debugging interface, debugging interface is also connected with the debugging interface of mainboard, and instruction input interface is also connected with the instruction output of terminal
Interface, processor can set the debugging interface of debugger to jtag interface or EJTAG interfaces, so that terminal passes through jtag interface
Or EJTAG interfaces debug mainboard.When debugging interface is connected to the jtag interface of mainboard, it is arranged by processor and is debugged
The attribute of interface sets debugging interface to jtag interface, it can be achieved that access of the debugger to the jtag interface of mainboard；Work as debugging
When interface is connected to the EJTAG interfaces of mainboard, the attribute of debugging interface is set by processor, sets debugging interface to
EJTAG interfaces realize different debugging functions, it can be achieved that access of the debugger to the EJTAG interfaces of mainboard.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiment, the same or similar parts between the embodiments can be referred to each other.
Above to a kind of debugger provided by the utility model and debugging apparatus, it is described in detail, answers herein
The principles of the present invention and embodiment are expounded with specific case, the explanation of above example is only intended to sides
Assistant solves the method and its core concept of the utility model；Meanwhile for those of ordinary skill in the art, according to the application's
Thought, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as
Limitation to the application.
Claims (8)
1. a kind of debugger, which is characterized in that including：Processor, debugging interface and instruction input interface；
The processor is connect with described instruction input interface and the debugging interface respectively, and the debugging interface is also connected with mainboard
Debugging interface, described instruction input interface is also connected with the instruction output interface of terminal；
The processor, for setting the debugging interface of the debugger to joint test working group jtag interface or enhancing connection
Close test job group EJTAG interfaces so that the terminal by the jtag interface or the EJTAG interfaces to the mainboard into
Row debugging.
2. debugger according to claim 1, which is characterized in that the processor includes general I/O port GPIO
Interface, the processor sets the debugging interface of the debugger to jtag interface by the GPIO interface or EJTAG connects
Mouthful.
3. debugger according to claim 1, which is characterized in that the debugger further includes memory；
The memory, for loading basic input-output system BIOS system program, operating system program and application program, institute
It includes JTAG drivers and EJTAG drivers to state application program.
4. debugger according to claim 3, which is characterized in that the memory is Synchronous Dynamic Random Access Memory core
Piece.
5. debugger according to claim 1, which is characterized in that described instruction input interface is network interface, general serial is total
Any one in line USB port, serial ports and parallel port.
6. debugger according to claim 1, which is characterized in that the tune of the debugging interface of the debugger and the mainboard
Mouth of trying is connected by interface connecting line.
7. debugger according to claim 1, which is characterized in that the processor for no inner interlocked pipelining-stage micro- place
Manage device MIPS architecture processors.
8. a kind of debugging apparatus, which is characterized in that the debugger including terminal and as described in any one of claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820161850.3U CN207946806U (en) | 2018-01-30 | 2018-01-30 | A kind of debugger and debugging apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820161850.3U CN207946806U (en) | 2018-01-30 | 2018-01-30 | A kind of debugger and debugging apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207946806U true CN207946806U (en) | 2018-10-09 |
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| CN201820161850.3U Active CN207946806U (en) | 2018-01-30 | 2018-01-30 | A kind of debugger and debugging apparatus |
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Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |
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