CN2078942U - Microcomputer-type differential relay - Google Patents
Microcomputer-type differential relay Download PDFInfo
- Publication number
- CN2078942U CN2078942U CN 90220000 CN90220000U CN2078942U CN 2078942 U CN2078942 U CN 2078942U CN 90220000 CN90220000 CN 90220000 CN 90220000 U CN90220000 U CN 90220000U CN 2078942 U CN2078942 U CN 2078942U
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Abstract
The utility model relates to a microcomputer type differential relay for protecting power transformers, comprising a combined current and potential transformer, a ten-path low pass filter and the sampling holder thereof, an analogue/digital converter and a microcomputer processor. The microcomputer type differential relay is characterized in that the interior of the memory circuit of the microcomputer processor adopts an electrically erasable ROM to store setting values and is connected with a return circuit for rewriting the setting values, which makes the setting values able to be rewritten optionally at any time without any influence to the content of other memories. The utility model which can remove faults in 15 milliseconds has high sensitive rate, reliable performance and easy use, able to meet the requirements of safe operation in power systems.
Description
The utility model relates to a kind of microcomputer type differential relay that is used to protect power transformer.
Transformer differential relay had for four generations; (1) old-fashioned electromagnetic type differential relay; (2) old-fashioned rectification type differential relay; (3) transistor-type differential relay; (4) integrated circuit type differential relay.These four kinds of relay common features are that to adopt the simulation electric weight be that the actual value of the magnitude of current and voltage is moved comparison; preceding two kinds very outmoded; responsiveness is very slow; sensitivity is also very low; can not adapt to the requirement of high-pressure system tranformer protection, though back two kinds of existing obviously raisings on performance are still disliking not enough aspect responsiveness and the sensitivity; especially to superhigh pressure, jumbo power transformer, wish that the differential relay performance of protecting it not to be damaged is more superior better.In addition; domestic also have a kind of PC relay that the power transformer circuit is protected; the setting value of its inside is rewritten the loop and is all adopted read-only memory; though can preserve data well; but it is pretty troublesome to rewrite setting value; the ultraviolet equipment that needs configure dedicated to add; could rewrite after all wiping with ultraviolet ray; and execute-in-place; generally can't grasp, it is also shorter to rewrite the life-span, rewrites at most hundreds of times; and need often to adjust according to load variations by the current/voltage setting value of transformer or circuit, this is the insurmountable problem of this relay.
The purpose of this utility model is exactly in order to overcome above-mentioned shortcoming, and a kind of the 5th generation microcomputer type sudden change amount differential relay is provided, and its responsiveness and action sensitivity have all improved an order of magnitude, and setting value can be rewritten arbitrarily at any time.
Technical solution of the present utility model is as shown in the figure:
Fig. 1 is a theory diagram of the present utility model;
Fig. 2 is the utility model computer processor electrical schematic diagram;
Fig. 3 is the utility model low pass filter electrical schematic diagram.
Such as Fig. 1,2, the utility model is by current transformer B1、B
2、B
3, voltage transformer B4, auxiliary reactance transformer KH1~KH
7, auxiliary potential transformer YH1~YH
3, balancing, the anti-shock resistance circuit A that shoves1~A
10, No. ten low pass filter LF1~LF
10And sampling hold circuit SH1~SH
10, A/D converter A/O, computer processor and photoelectricity input, output control circuit I/O-1, I/O-2 form, and wherein computer processor is by frequency generator and frequency divider U9、U
14, central processor CPU (U5), buffer circuit U7、 U
8、U
22, logic control circuit U13, interrupt control circuit U21, serial interface circuit U17, parallel interface U26、U
36, clock circuit U4, the baud rate circuit U18, local logic control circuit U28Form with main memory circuit, it is characterized in that the main memory circuit of computer processor is by electrically erasable read-only memory U34,U
35, random access memory U32、U
33With read-only storage U30、U
31Consist of electrically erasable read-only memory U34Be even number sheet, U35Be odd number sheet, U34The data/address bus input be connected to the D of data/address bus0~D
7,U
35The data/address bus input be connected to the D of data/address bus8~D
15,U
34、U
35The address bus input all be connected to the A of address bus1~A
13On, random access memory U32Be even number sheet, U33Be the odd number sheet, read-only storage U30Be even number sheet, U31Be odd number sheet, random access memory U32、U
33With read-only storage U30、U
31Data/address bus input, address bus input and data/address bus, connected mode and the read-only storage U of electric erasable of address bus34、U
35Connected mode identical, read-only storage U30、U
31Gating end CE connect respectively and not gate U23、U
24Output, when with not gate U12Input A16~A
19With M ID
When entirely being high level, U12Output low level, then U23、U
24Respectively by the address bus AD and the central processor CPU (U that import5) the control signal BHE control sent, random access memory U32、U
33With electrically erasable read-only memory U34、U
35Gating end CE respectively corresponding and local logic control circuit U28Pulse signal output end O0a, O0b, Ota, O1b connect electrically erasable read-only memory U34、U
35The end WE that writes connect normally closed contact K by linked switch K1Connect the positive pole of capacitor C, the minus earth of C, simultaneously, U34、U
35Write the also normally opened contact K by linked switch K of end WE2Be connected electrically erasable read-only memory U with the write signal output WE of central processor CPU34、U
35Control end 1 pass through respectively resistance R18、R
19Meet+the 5V power supply U34、U
35Control end 1 also connect respectively and door U29Input 4,5, with door U29Output 6 and with door U '29Input 2 connect U '29Input 1 connect and not gate U19Output 12, with not gate U19, frequency divider U14With with not gate U15Form the stand-by period circuit for generating, it is given and door U '291 input scouring time of inserting about 500 μ s, U '29Output 3 be connected to oscillator U in frequency generator and the frequency divider9Preparation state end ROY1,U
9Preparation state end REAOY be connected preparation state end REAOY with central processor CPU and connect, make CPU be in wait state at 500 μ s in the insertion time, make electrically erasable read-only memory U34,U
35Can clean at this moment and fall old memory content; The normal opened contact K of linked switch K2At electrically erasable read-only memory U34、U
35Be in off-state when not writing new content, K2(this moment normally closed contact K during disconnection1Connection) makes U34、U
35The end WE that writes connect a unsettled line, capacitor C be used for preventing the electromagnetism on the unsettled line do anti-, to guarantee U34,U
35In content can stably preserve, as electrically erasable read-only memory U34、U
35In content need rewrite new content the time, the normally closed contact K of linked switch K1Disconnect normal opened contact K2Connect, make the write signal WR of central processing unit C PU can enter smoothly U34、U
35Write the end WE, this moment capacitor C be in disconnected Open position has been avoided the decay to CPU high frequency write signal WR.
As Fig. 1, when the utility model uses, from the both sides three-phase current access current transformer B of two circle power transformer T
1, B
2, the on high-tension side central point electric current of two circle power transformer T meets current transformer B
3, power transformer T high-voltage side bus three-phase electricity crimping voltage transformer B
4, having seven road electric currents and three road voltages, seven road current signals insert auxiliary reactance transformer KH
1~KH
7, three road voltage signals insert auxiliary potential transformer YH
1~YH
3, during power transformer T operation working properly, its low-pressure side electric current
(flow into power transformer
Electric current) should with its high voltage side current
(flowing out the electric current of power transformer T) size is identical, and according to B among Fig. 1
1, B
2The polarity connection, its direction is also identical, sets differential operating current in the utility model
Stalling current
When then power transformer T normally moves, differential operating current
Stalling current
Very big, so the utility model is not carried out action.The power supply of generator F passes through power transformer T to the load normal power supply; When power transformer T inside is short-circuited fault, because of the short dot current potential reduces, so the electric current of power transformer T high and low pressure both sides
All flow to power transformer T, at this moment, differential operating current
Very big, and stalling current
So the utility model action is serially connected in two circle power transformer T low-pressure sides and on high-tension side circuit breaker D through the trip signal excision takes place after the MICROCOMPUTER PROCESSING
1, D
2, protection power transformer T is unlikely to scaling loss, and makes the stabilization of power grids to the load power supply, and the concrete course of work of the utility model is that seven road electric currents and three road voltage signals are respectively through auxiliary reactance transformer KH
1~KH
7With auxiliary potential transformer YH
1~YH
3After the conversion, send into balancing, the anti-shock resistance circuit A that shoves
1~A
10Carry out preliminary treatment, No. ten low pass filter LF are sent in its output respectively
1~LF
10The filtering high order harmonic component.No. ten low pass filter circuits are all identical, its circuit as shown in Figure 3, it is by resistance R
3-3, R
3-4, potentiometer W
3-2, W
3-3, capacitor C
3-1, C
3-2, C
3-3With amplifier U
3-1Form, balancing, anti-ly shove the shock resistance circuit (by R
3-1, R
3-2, W
3-1, D
3-1~D
3-4, C
3-6Composition) output connecting resistance R
3-3With potentiometer W
3-2Serial connection branch road one end, this serial connection branch road other end with by W
3-3, R
3-4, C
3-2The input of the integrating circuit of forming connects, W
3-3, R
3-4, C
3-2The output termination amplifier U of the integrating circuit of forming
3-1In-phase input end 3, U
3-1Output 6 directly and U
3-1Inverting input 2 connect, and pass through capacitor C
3-1Be connected to potentiometer W
3-2, W
3-3Mid point, form positive feedback loop, during low pass filter work, R
3-3, W
3-2And C
3-1Form first order integral filter circuit, the output of first order integral filter circuit meets second level integrating circuit (W again
3-3, R
3-4, C
3-2) input, this two-stage integration filter circuit is tentatively with the high order harmonic component filtering, again through the amplifier U of high-amplification-factor
3-1Positive feedback effect, just strengthened their filter effect greatly, make the whole filterings of high order harmonic component that 300Hz is above, the sampling holder U of next stage is just sent in the output of low pass filter
3-2, U
3-2Have the very high linearity and stability, the energy inhibit signal is constant, guarantees A/D conversion accuracy.As Fig. 1, No. ten low pass filter LF
1~LF
10Output send ten road sampling holder SH respectively
1~SH
10, SH
1~SH
10According to by parallel interface U
26The 12 point sampling speed synchronized samplings of ripple weekly sent of PA mouth (Fig. 2), send into modulus converter A/D in order through variable connector MK and carry out analog-to-digital conversion, it is exported 12 position digital signals and carries out calculation process to computer processor.As Fig. 2, the computer processor course of work is that 12 position digital signals of being sent here by A/D deposit random asccess memory U in by data/address bus
32, U
33, central processor CPU is according to being solidificated in read-only memory U in advance
30, U
31Interior software program will deposit U in
32, U
33Data carry out calculation process, arithmetic speed is by the oscillator U in frequency generator and the frequency divider
9Control, U
9Producing 5MHz is the clock cycle of 200ns, and central processor CPU is just according to this clock cycle high speed operation, and produces differential operating current I by leaf-size class transformation of variables method in winning
DStalling current I
ZAmplitude, I
DAmplitude with pre-deposit electrically erasable read-only memory U
34, U
35In differential operating current standard value (being setting value) Is compare, if I
D>I
S, and I
D>I
Z, then computer processor is to parallel interface U
26, U
36The PB mouth send the tripping operation password, the photoelectric yield device I/O-2 by photoelectricity input, output control circuit sends high level, makes circuit breaker D
1, D
2Tripping operation, and send alarm signal, computer processor also passes through U
26, U
36The PC mouth start printer, the record relevant data is convenient to the operations staff and is checked analyzing failure cause; If I
D<I
S, or I
D<I
Z, show that power transformer T is in normal operating condition, then computer processor is not to parallel interface U
26, U
36Send the execution signal, continue to handle new data, so circulation constantly repeats work.Interrupt control circuit U among Fig. 2
21Be used for the multiple different function of the utility model is according to priority carried out Interrupt Process (multiple difference in functionality of the present utility model includes protection operational mode, printing operational mode, automatic detection mode and adjusts definite value working method etc.) by its important level.Serial interface circuit U
17Be to work when linking to each other with terminal (CRT) at the utility model, it is according to Baud rate generator U
18The work of baud rate of sending and terminal (CRT) coupling, be mainly used to as on-the-spot with terminal (CRT) to the utility model debug, Peripheral Interface when checking.Clock circuit U
4Be the programmable clock signal generator, main effect is to produce year, month, day, hour, min, the real-time clock of second, when this clock was accurately walked before 2000 automatically, influences the leap month of not being subjected to the leap year, and can print year, month, day, hour, min, second time.Baud rate generator U
18With frequency divider U
38Produce the 600Hz frequency by the U in the parallel interface
26The PA mouth give sampling holder SH of the present utility model
1~SH
10The sampling reference frequency of 12 in ripple is provided weekly.Logic control circuit U
13Produce control signal, control each circuit working, local logic control circuit U
28Produce gating signal, the work of control main memory circuit.In Fig. 1, the photoelectricity loader I/O-1 in the photoelectricity input/output control circuit is used to provide three road contact control signals, can make the utility model meet desired concrete operational mode according to the specific requirement at scene.Setting value is rewritten the loop by electrically erasable read-only memory U among keypad and Fig. 2
34, U
35Write end linked switch K that WE connected and capacitor C and form, when need are rewritten, the normal opened contact K of the K that closes
2(this moment normally closed contact K
1Disconnect), according to being solidificated in read-only memory U
30, U
31Interior setting value monitoring program operation keypad can arbitrarily be rewritten U at any time
34, U
35Interior setting value content, and do not influence other content.
The utility model be the 5th generation the latest model relay, it adopts sudden change amount current differential principle, realize the comparison of differential operating current and stalling current and setting value with microcomputer, arithmetic speed is very high, can excise fault in 15/1000ths seconds, and the existing relay of remolding sensitivity exceeds an order of magnitude, can reduce the degree of injury of power transformer to greatest extent, the utility model is a domestic initiation, has filled up the blank of China, is in the first place in the world.The utility model in computer processor owing to adopt electrically erasable read-only memory, make that the rewriting setting value is very convenient, can arbitrarily rewrite any one setting value according to field requirement at any time, rewriting number of times can reach hundreds thousand of times, useful life, big leap ahead and did not influence other memory content, and need not the ultraviolet optional equipment that special use adds, at the scene, the operation operations staff grasps easily.The utility model is owing to adopt second order positive feedback active low-pass filter, its superior performance, guaranteed the high-quality processing of sampling circuit to the input analog signal, be provided with balancing, the anti-shock resistance circuit that shoves at signal input port, external interface adopts the generating coupler to isolate, and does anti-performance so have good anti-electromagnetism.The utility model keypad adopts the man-machine conversation mode, and on-the-spot use is directly perceived, convenient, grasps easily.The utility model advanced technology, stable performance is good, can satisfy the needs of power system security reliability service.
Claims (3)
1, a kind of microcomputer type sudden change amount differential relay, it is by current transformer B
1, B
2, B
3, voltage transformer B
4, auxiliary reactance transformer KH
1~KH
7, auxiliary potential transformer YH
1~YH
3, balancing, the anti-shock resistance circuit A that shoves
1~A
10, No. ten low pass filter LF
1~LF
10And sampling hold circuit SH
1~SH
10, modulus converter A/D, computer processor and photoelectricity input/output control circuit I/O-1, I/O-2 form, and wherein computer processor is by frequency generator and frequency divider U
9, U
14, central processor CPU (U
5), buffer circuit U
7, U
8, U
22, logic control circuit U
13, interrupt control circuit U
21, serial interface circuit U
17, parallel interface U
26, U
36, clock circuit U
41The baud rate circuit U
18, local logic control circuit U
28With main memory circuit U
30~U
35Form, the main memory circuit that it is characterized in that computer processor is by electrically erasable read-only memory
34, U
35, random asccess memory U
32, U
33With read-only memory U
30, U
31Constitute electrically erasable read-only memory U
34Be even number sheet, U
35Be odd number sheet, U
34The data/address bus input be connected to the D of data/address bus
0~D
7, U
35The data/address bus input be connected to the D of data/address bus
8~D
15, U
34, U
35The address bus input all be connected to the A of address bus
1~A
13On, random asccess memory U
32Be even number sheet, U
33Be the odd number sheet, read-only memory U
30Be even number sheet, U
31Be odd number sheet, U
32, U
33And U
30, U
31Data/address bus input, address bus input and data/address bus, the connected mode and the U of address bus
34, U
35Connected mode identical, U
30, U
31Gating end CE meet NAND gate U respectively
23, U
24Output, U
23, U
24The control signal BHE control sent by address bus and central processor CPU of input, U
32, U
33And U
34, U
35Gating end CE respectively corresponding with local logic control circuit U
28Pulse signal output end O0a, O0b, O1a, O1b connect electrically erasable read-only memory U
34, U
35The end WE that writes connect normally closed contact K by linked switch K
1Connect the positive pole of capacitor C, the minus earth of C, simultaneously, U
34, U
35Write the also normal opened contact K by linked switch K of end WE
2Be connected U with the write signal output WR of central processor CPU
34, U
35Control end 1 pass through resistance R respectively
18, R
19Meet+the 5V power supply U
34, U
35Control end 1 also connect respectively with the door U
29Input 4,5, with door U
29Output 6 and with door U '
29Input 2 connect U '
29Input 1 meet NAND gate U
19Output 12, NAND gate U
19, frequency divider U
14With NAND gate U
15Form stand-by period generation circuit, it is given and door U '
291 input scouring time of inserting about 500 μ s, U '
29Output 3 be connected to oscillator U in frequency generator and the frequency divider
9Standby condition end RDY1, U
9Standby condition end READY and the standby condition end READY of central processor CPU be connected.
2, by the described microcomputer type real variable of claim 1 differential relay, it is characterized in that low pass filter is by resistance R
3-3, R
3-4, potentiometer W
3-2, W
3-3, capacitor C
3-1, C
3-2, C
3-3With amplifier U
3-1Form the output connecting resistance R of balancing, the anti-shock resistance circuit that shoves
3-3With potentiometer W
3-2An end of serial connection branch road, this serial connection branch road other end with by W
3-3, R
3-4, C
3-2The input of the integrating circuit of forming connects, integrating circuit W
3-3, R
3-4, C
3-2Output termination amplifier U
3-1In-phase input end 3, U
3-1Output 6 directly and U
3-1Inverting input 2 connect, and pass through capacitor C
3-1Be connected to potentiometer W
3-2, W
3-3Mid point, form positive feedback loop.
3, by the described microcomputer type sudden change of claim 1 amount differential relay, it is characterized in that current transformer B
1, B
2Connect the three-phase current end of two circle power transformer T both sides, current transformer B
3Connect two circle power transformer T high-pressure sides central point current terminal, voltage transformer B
4Connect two circle power transformer T high-voltage side bus three-phase electricity pressure sides; Low-pressure side, two ends, high-pressure side at two circle power transformer T respectively are connected in series a circuit breaker D
1, D
2
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 90220000 CN2078942U (en) | 1990-12-01 | 1990-12-01 | Microcomputer-type differential relay |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 90220000 CN2078942U (en) | 1990-12-01 | 1990-12-01 | Microcomputer-type differential relay |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2078942U true CN2078942U (en) | 1991-06-12 |
Family
ID=4898626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 90220000 Withdrawn CN2078942U (en) | 1990-12-01 | 1990-12-01 | Microcomputer-type differential relay |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN2078942U (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1037392C (en) * | 1995-11-24 | 1998-02-11 | 孙志杰 | Transformer differential protection of wave mode symmetrical method |
CN100440666C (en) * | 2002-05-08 | 2008-12-03 | 西门子公司 | Electric power switch with an electronic memory unit for parameters and conversion factors |
CN1302465B (en) * | 1999-05-05 | 2010-05-26 | 通用电气公司 | Adaptive sampling rate based on power system frequency |
CN109599850A (en) * | 2018-12-05 | 2019-04-09 | 合肥能安科技有限公司 | A kind of safe early warning type intelligent breaker |
-
1990
- 1990-12-01 CN CN 90220000 patent/CN2078942U/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1037392C (en) * | 1995-11-24 | 1998-02-11 | 孙志杰 | Transformer differential protection of wave mode symmetrical method |
CN1302465B (en) * | 1999-05-05 | 2010-05-26 | 通用电气公司 | Adaptive sampling rate based on power system frequency |
CN100440666C (en) * | 2002-05-08 | 2008-12-03 | 西门子公司 | Electric power switch with an electronic memory unit for parameters and conversion factors |
CN109599850A (en) * | 2018-12-05 | 2019-04-09 | 合肥能安科技有限公司 | A kind of safe early warning type intelligent breaker |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C19 | Lapse of patent right due to non-payment of the annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |