Background technology
Switching Power Supply is a kind of voltage conversion circuit, is mainly used in boosting and is depressured, and is widely used in hyundai electronicses production
In product.Such as light emitting diode (LED) light source generally uses Switching Power Supply as its power supply.
Decompression (Buck) constant current driving is the LED type of drive of current main flow.This type of drive has simple in construction, life
Produce the advantages that cost is low, easy to process.Traditional voltage-dropping type critical conduction mode (the Boundary Conduction of Fig. 1 examples
Mode, BCM) LED constant current drive system schematic diagram.As shown in figure 1, constant current driving system 100 is by an input rectifier
110th, a decompression constant current driving stage 120 and the three parts of output loading 130 are formed.Input rectifier 110 by diode D1, D2,
D3 and D4 compositions.Constant current driving stage 120 is depressured by 121, an input capacitance Cin, constant-current controller supplying resistances
R1, a power supply capacitor Cc, a current sampling resistor Rs, a power switch M1, a sustained diode x, a work(
Rate inductance L and an output capacitance Co are formed.Constant-current controller 121 includes power source generator 1211, a reference source 1212, current limliting
Comparator 1213, zero-crossing detector 1214 and PWM logics 1215.
As shown in figure 1, (AC) input voltage is exchanged first by the rectification of input rectifier 110, and by input capacitance Cin
The input voltage of voltage-dropping type constant current driving stage 120 is formed after filtering.Constant-current controller 121 is by controlling power switch M1 to realize energy
Measure to output loading transmission.Current sampling resistor Rs sample streams overpower inductance L peak point current, to control power switch M1's
Shut-off, so as to controlling stream overpower inductance L peak point current;And power switch pipe M1 leakage (Drain) terminal voltage, by its own
Gate-drain parasitic capacitances Cgd sampled, and the zero crossing of inductive current is detected to control power by zero-crossing detector 1214
Switch M1 conducting.Therefore, this control mode causes decompression constant current driving stage 120 to be operated in BCM patterns, i.e. inductive current
(and flowing through the electric current of output loading 130) from cyclically-varying between a peak value set in advance and zero, so as to realize perseverance
Flow the purpose of output.
Fig. 2 illustrates the timing diagram of above-mentioned current constant control mode.As shown in Fig. 2 when pwm signal is changed into high level, power
M1 conductings are switched, power inductance L starts excitation, and its electric current gradually rises.When the sampled voltage Vcs on current sampling resistor Rs reaches
To Current-Limiting Comparator 1213 threshold value Vth when, Current-Limiting Comparator 1213 exports peak detection signal OCP to PWM logics 1215, controls
Pwm signal step-down processed, power switch M1 cut-offs.After power switch M1 cut-offs, power inductance L starts to demagnetize, and its electric current gradually subtracts
It is small.At the end of demagnetization, power inductance L electric current is reduced to zero, and power switch M1 drain terminal voltage starts resonance.Such as Fig. 2 institutes
Show, in the zero crossing of inductive current, slope mutation occurs in drain terminal voltage, and the voltage signal is by the grid leak of power switch M1 in Fig. 1
Parasitic capacitance Cgd is sampled, and the voltage sampling signal inputs constant-current controller 121 by the GATE pins of constant-current controller 121
Internal zero-crossing detector 1214.Zero-crossing detector 1214 detects inductive current zero crossing, and exports a zero passage detection letter
Number ZCS to PWM logics 1215, the M1 conductings of control power switch.In summary, under this control mode, inductive current is at peak
Mechanical periodicity between value Ip and zero, system are operated in BCM patterns, and output average current is equal to the 1/2 of peak point current Ip, wherein peak
It is worth electric current Ip and is equal to the threshold voltage vt h of the Current-Limiting Comparator 1213 divided by resistance Rs of current sampling resistor.
The mode of being controlled as described above is the constant current drive control mode of current main flow, such as the limited public affairs of Shanghai Lay lion semiconductor technologies
The constant-current driven chip LIS8411B, LIS8411C of department are to employ the constant current driving that above-mentioned control mode realizes LED.
In LED illumination System, this type of drive of the above mainly includes there is also there is some intrinsic weak points:
1st, peak point current is bigger, causes power switch conduction loss higher;2nd, the ripple current of inductance is big, therefore LED load needs
Parallel filtering electric capacity is wanted, to reduce current ripples, therefore adds extra cost;3rd, constant-current controller needs special power supply
Electric capacity, also increase system cost.
In addition to the constant current driving system of above-mentioned BCM patterns, also there are some to use continuous conduction mode (Continuous
Conduction Mode, CCM) constant current driving system, for example, the chip HV9921/2/3 of MICROCHIP companies, China Resources silicon
The chip PT4207 of micro- scientific and technological (Shanghai) Co., Ltd. may be used to control CCM constant current driving system.
By taking HV9921/2/3 chips as an example, as shown in figure 3, when its control mode used is power switch M1 shut-off
Between be defined as steady state value, power inductance L peak point current is defined as steady state value.It is appropriate to choose under this control mode
Power inductance L sensibility reciprocal, and can make circuit work in ccm mode under constant output voltage, and obtain a fixation
Output current.Its output current is:
Wherein, IPIt is the constant peak current that current constant control switch chip 321 is set, Δ I is the width of inductance ripple current
Degree, Vo are output voltages, and L is the sensibility reciprocal of inductance, ToffIt is fixed shut-off (Off) time that chip 321 is set.From above formula,
In order to reach output constant current, output voltage and inductance sensibility reciprocal must keep constant.But in actual applications, the sensibility reciprocal of inductance
Certain deviation is often had, and output voltage is fixed and also strongly limit application.
For this reason, it may be necessary to seek a kind of more advanced CCM mode constant currents control method to avoid the above-mentioned fixed turn-off time
(Toff) the defects of control mode is present.
Utility model content
The technical problems to be solved in the utility model is to provide one kind and is continuously turned on current-mode constant-current control circuit, can
The automatic adjusument turn-off time.
In order to solve the above technical problems, the utility model, which provides one kind, is continuously turned on current-mode constant current drive control system
System, including input rectifier, voltage-dropping type constant current driving stage and the output loading being sequentially connected, it is characterised in that the voltage-dropping type is permanent
Stream driving stage includes constant-current controller, current sampling resistor, power switch, fly-wheel diode and power inductance, the constant current control
Utensil processed has the first power end, second source end, sampling end and drive end, and the drive end connects the control terminal of power switch, should
Fly-wheel diode is connected between first power end and the first end of the power switch, and the current sampling resistor is connected to the work(
Between the second end and the second source end of rate switch, the sampling end connects the second end of the power switch, the power inductance with
The output loading is connected, and the constant-current controller includes power source generator, a reference source, controlled oscillator, PWM generator, PWM
Driver and Heising modulation device.Power source generator connects first power end, and the power source generator provides power supply.A reference source
The first reference voltage and the second reference voltage are produced, first reference voltage is higher than second reference voltage.Controlled oscillator root
Clock signal is produced according to PWM postpones signals.PWM generator produces pwm signal according to the clock signal and peak detection signal, its
In the peak detection signal triggering PWM signals trailing edge.Pwm driver produces drive signal according to the pwm signal and provided
To the drive end.Heising modulation device connects the sampling end, and the Heising modulation device is according to the inductance excitation on current sampling resistor
The comparative result of current sample voltage and first reference voltage produces the peak detection signal, and according to inductance excitation electricity
The comparative result of stream sampled voltage and second reference voltage produces the PWM postpones signals.
In an embodiment of the present utility model, the power source generator produces the first power supply and the second power supply,
First power supply is supplied to a reference source, PWM generator, controlled oscillator and Heising modulation device, second power supply
It is supplied to the pwm driver.
In an embodiment of the present utility model, the Heising modulation device includes peak comparator, latched comparator, burst pulse
Generator, NAND gate, phase inverter and nor gate.The first input end of peak comparator inputs first reference voltage, and second is defeated
Enter end and input the inductance exciting current sampled voltage, output end exports the peak detection signal.First input of latched comparator
End inputs the inductance exciting current sampled voltage, and the second input inputs second reference voltage, and latched comparator is in the power
Switch conduction moment compares the inductance exciting current sampled voltage and second reference voltage, and compares letter from output end output
Number.The input of narrow-pulse generator inputs the pwm signal, and the narrow-pulse generator produces burst pulse according to the pwm signal to be believed
Number.The first input end of NAND gate inputs the comparison signal, and the second input inputs the narrow pulse signal.The input of phase inverter
Input the narrow pulse signal.The first input end of nor gate inputs the comparison signal, and the second input connects the defeated of the phase inverter
Go out end.The first input end of pip integrator connects the output end of the NAND gate, and the second input connects the output of the nor gate
End.The input of delay controller inputs the pwm signal, and its control terminal connects the output end of the pip integrator, the delay control
Device processed produces the PWM postpones signals under the control of the output signal of the pip integrator.
In an embodiment of the present utility model, the controlled oscillator includes nor gate, inverting delay unit and even number
Individual phase inverter, the first input end of the nor gate connect the PWM postpones signals, and the output end of the nor gate connects the inverting delay
The input of unit, the output end of the inverting delay unit be sequentially connected the even number phase inverter, wherein odd number phase inverter
Output end connects the second input of the nor gate, and the output end of even number phase inverter exports the clock signal.
In an embodiment of the present utility model, when the low level that the inverting delay unit sets the clock signal continues
Between.
In an embodiment of the present utility model, the PWM generator includes d type flip flop, and the D inputs of the d type flip flop are defeated
Enter logic " 1 " signal, input end of clock inputs the clock signal, and clear input inputs the peak detection signal, and output end is defeated
Go out the pwm signal.
In an embodiment of the present utility model, the power source generator includes control level power supply and driving level power supply, the control
Level power supply processed provides first supply voltage, and the driving level power supply provides second supply voltage.
The utility model is allowed to compared with prior art, have following remarkable advantage due to using above technical scheme:
1st, the control mode of current-mode is continuously turned on as a result of voltage-dropping type, with traditional critical current pattern phase
Than, the peak value of power inductor current is reduced, so as to reduce the conduction loss of power switch pipe, therefore can under same power
To use smaller power switch pipe;
2nd, the control mode of current-mode is continuously turned on as a result of voltage-dropping type, reduces output current ripple, so as to
Necessary output filter capacitor in traditional critical conduction mode is eliminated, greatly reduced system cost;
3rd, the voltage-dropping type as a result of turn-off time automatic adjusument is continuously turned on the control mode of current-mode, with biography
The control mode that the fixation turn-off time voltage-dropping type of system is continuously turned on current-mode is compared, in inductance sensibility reciprocal and output loading pressure drop
The output of constant current can still be ensured during change;
4th, as a result of special power-supply service, supplying resistance and the confession of constant-current controller in traditional structure are eliminated
Electric capacity, simplify system design and reduce system cost.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, below in conjunction with accompanying drawing to this practicality
New embodiment elaborates.
Many details are elaborated in the following description in order to fully understand the utility model, but this practicality is new
Type can also be different from other manner described here to implement using other, therefore the utility model is not by following public tool
The limitation of body embodiment.
Fig. 4 is the principle for being continuously turned on current-mode (CCM) constant current driving control system of the embodiment of the utility model one
Figure.With reference to shown in figure 4, constant current driving system 400 includes an input rectifier 410, decompression (Buck) constant current driving stage
420 and output loading 430.Input rectifier 410 is made up of diode D1, D2, D3 and D4.Decompression constant current driving stage 420 includes
One constant-current controller, 421, supplying resistance R1, a power supply capacitor Cc, a current sampling resistor Rs, a power
Switch M1, a sustained diode x and a power inductance L.Compared with the conventional buck driver in Fig. 1, the present embodiment
CCM mode constant currents drive system 400 at least eliminate output capacitance Co.As shown in figure 4, ac input signal is by input
Voltage-dropping type constant current driving stage 420 is inputted after the rectification of rectifier 410.Constant-current controller 421 controls power switch M1 conductings and closed
It is disconnected, energy is delivered to output loading 430, and ensure that system is operated in CCM patterns, and the electric current for flowing through LED load keeps permanent
It is fixed.
Further, constant-current controller 421 has the first power end HV, second source end VSS, sampling end CS and drive end
GATE.Drive end GATE connection power switch M1 control terminal.Sustained diode x one end is by supplying resistance R1 connections the
One power end HV, the other end connect the first end (such as drain terminal) of power switch.Current sampling resistor Rs is connected to power switch M1
The second end (such as source) and second source end VSS between.Sampling end CS connection power switch M1 the second end.Power inductance L
It is connected between power switch M1 first end and output loading 430, is connected with output loading 430.Constant-current controller 421 includes
Power source generator 4211, a reference source 4212, controlled oscillator 4213, PWM generator 4214, Heising modulation device 4215 and PWM drive
Dynamic device 4216.Power source generator 4211 connects the first power end HV, there is provided power supply VDD.A reference source 4212 is according to power supply electricity
Source VDD produces the first reference voltage VH and the second reference voltage VL, VH and is higher than VL.Heising modulation device 4215 is adopted according in electric current
The comparative result of inductance exciting current sampled voltage Vcs and the second reference voltage VL on sample resistance Rs produce PWM postpones signals
PWMD.Controlled oscillator 4213 produces clock signal clk according to PWM postpones signals PWMD.Heising modulation device 4215 is always according to electricity
The comparative result for feeling exciting current sampled voltage Vcs and the first reference voltage VH produces peak detection signal OCP.PWM generator
4214 produce pwm signal according to clock signal clk and peak detection signal OCP, and wherein peak detection signal triggers pwm signal
Trailing edge.PWM drivers 4216 produce drive signal according to pwm signal and provided to drive end GATE.
The details that whole constant-current controller 421 works is described further below.When the GATE signals of constant-current controller 421
For high level, power switch M1 conductings, power inductance L enters the excitation stage.Inductive current passes through power switch M1 inflow currents
Sampling resistor Rs, and form inductive current sampled voltage Vcs.Heising modulation in sampled voltage Vcs input constant-current controllers 421
Device 4215.Inside constant-current controller 421, two reference voltages VH, VL also enter into Heising modulation caused by a reference source 4212
Device 4215.Pwm signal also inputs Heising modulation device 4215 caused by PWM generators 4214.Sampling on current sampling resistor Rs
Reference voltage signal VH caused by voltage Vcs and a reference source 4212, which compares, to be produced peak detection signal OCP and is input to PWM
Device 4214.As shown in figure 4, OCP signals trigger pwm signal by high step-down, so as to be switched by the switch-off power of pwm driver 4216
M1.On the other hand, sampled voltage Vcs is in reference voltage signal VL ratios caused by the inside of PWM generator 4214 and a reference source 4212
Compared with comparative result controls the delay of pwm signal by controlling Heising modulation device 4215, and produces PWM postpones signal
PWMD.PWMD signals input controlled oscillator 4213, and produce clock signal clk.Clock signal clk and Heising modulation device 4215
Caused OCP signals are input to PWM generator 4214 and produce pwm signal.Pwm signal input pwm driver 4216 produces work(
Rate switchs M1 drive signal GATE.
Fig. 5 is the timing diagram of constant current driving control system shown in Fig. 4.It can be seen that the trailing edge triggering of CLK signal
Pwm signal is uprised by low, turns on power switch M1, and power inductance L starts excitation.In the excitation stage, the sampling of inductive current
Voltage Vcs raises with the increase of inductive current, when sampled voltage Vcs voltage reaches the peak inside Heising modulation device 421
When being worth the threshold voltage VH of comparator 702, Heising modulation device 421 exports peak detection signal OCP, and signal OCP makes pwm signal
Step-down, and switch-off power switch M1, make inductance enter demagnetization phase.In addition, pwm signal is also entered into Heising modulation device 421,
And the trailing edge of PWM postpones signal PWMD, PWMD trailing edge triggering clock signal clk is produced, and CLK trailing edge
The rising edge of pwm signal is triggered, turns on power switch M1.Therefore, the trailing edge of PWMD signals declines relative to pwm signal
The delay period t on edgedIt is exactly the power inductance L demagnetization time.Delay period tdBy inductance exciting current sampled signal
Vcs and Heising modulation device 4216 input signal VL control in excitation starting point result of the comparison.If for example, originated in excitation
Point (pwm signal becomes high level moment) Vcs voltages are less than threshold voltage VL, then this cycle pwm signal delay period td
It is a small amount of that a single order can be reduced, this causes time reduction of demagnetizing, so next cycle excitation initial current can raise one one
Rank is a small amount of;When the Vcs sampled voltages of excitation starting point are more than threshold voltage VL, it is small that delay period td can increase a single order
Amount, causes next cycle excitation initial current to reduce a single order a small amount of.Finally, the Vcs voltages of excitation starting point can be received
Hold back near threshold voltage VL, and delay period td can also converge to some regular time section.As shown in figure 5, the 1st,
2,3 PWM cycles, the Vcs voltages of excitation starting point are both less than threshold voltage VL, therefore delay period td is gradually shortened, and moves back
The magnetic time reduces, and is gradually risen so as to the Vcs voltages of excitation starting point;In the 4th PWM cycle, the Vcs voltages of excitation starting point
More than threshold voltage VL, so that one single order of demagnetization period increase in this cycle is a small amount of, the 5th PWM cycle is caused to be encouraged
The Vcs voltages of magnetic starting point are reduced under threshold voltage VL again;By that analogy, the Vcs of the 6th PWM cycle excitation starting point
Voltage be increased to again threshold voltage VL it.Finally, the Vcs voltages of excitation voltage starting point converge to threshold voltage VL.
In summary describe, the controlled oscillator 4213, PWM generator 4214 and Heising modulation device 4215 in Fig. 4 are common
Form a negative feedback loop.By the control of this negative feedback loop, output current Io finally converge to one it is constant
Value, and system is operated in CCM patterns.Output constant current Io is represented by:
Wherein, IHAnd ILIt is the bound of output current, it is as caused by a reference source 4212 inside constant-current controller 421
Threshold voltage VH, VL and current sampling resistor Rs settings.
Fig. 6 is the original for being continuously turned on current-mode (CCM) constant current driving control system of another embodiment of the utility model
Reason figure.With reference to shown in figure 6, constant current driving control system 600 includes 610, decompression constant current driving stages of an input rectifier
620 and output loading 630.Be depressured constant current driving stage 620 include 621, sampling resistor Rs of a constant current switch chip, one
A sustained diode x and power inductance L.Constant current switch chip 621 include power source generator 6211, a reference source 6212, by
Control oscillator 6213, PWM generators 6214, Heising modulation device 6215, pwm driver 6216 and power switch pipe M1.In this reality
Apply in example, the power source generator 6212 of constant-current controller 421 produces duplex feeding power vd D and VDDG, and wherein VDD gives chip control
Level (including a reference source 6212, PWM generator 6214, controlled oscillator 6213 and Heising modulation device 6215) power supply processed, and VDDG
Only powered to pwm driver 6216.Because duplex feeding will not interfere, therefore VDD externally fed electric capacity can be saved.
Compared with the constant current driving control system 400 in Fig. 4, the constant-current controller 421 and power of the system 600 of the present embodiment Fig. 4
Switch M1 is integrated into a chip 621, and eliminates supplying resistance R1 and power supply capacitor Cc.
As shown in fig. 6, ac input signal inputs voltage-dropping type constant current driving stage 620 after the rectification of input rectifier 610.
The conducting and shut-off of constant current switch control electric current, make energy be delivered to output loading 630, and ensure that system is operated in CCM patterns,
And flow through the constant current hold of LED load.The details of the present embodiment refers to previous embodiment, not reinflated herein.
Fig. 7 shows the circuit diagram of the Heising modulation device of the embodiment of the utility model one.With reference to shown in figure 7, Heising modulation device
6215 include the 703, pulse integrations of narrow-pulse generator of peak comparator 702, one of latched comparator 701, one
The 706, NAND gates 707 of the phase inverter of delay controller 705, one of device 704, one and a nor gate 708.Peakedness ratio compared with
The first input end of device 702 inputs the first reference voltage VH, the second input input inductance exciting current sampled voltage Vcs, defeated
Go out end output peak detection signal OCP.The first input end input inductance exciting current sampled voltage Vcs of latched comparator 701,
Second input inputs the second reference voltage VL, the output end output comparison signal DLT of latched comparator 701.Burst pulse occurs
The input input pwm signal of device 703, narrow-pulse generator produce narrow pulse signal PST according to pwm signal and exported.NAND gate
707 first input end input comparison signal DLT, the second input input narrow pulse signal PST.The input of phase inverter 706
Input narrow pulse signal PST, the first input end input comparison signal DLT of nor gate 708, the second input connection phase inverter
706 output end.The output end of the first input end connection NAND gate 707 of pip integrator 704, the connection or non-of the second input
The output end of door 708.The input input pwm signal of delay controller 705, its control terminal connect the defeated of pip integrator 704
Go out end, delay controller 705 produces PWM postpones signals PWMD under the output signal VCH of pip integrator 704 control.
Fig. 8 shows the timing diagram of the Heising modulation device of embodiment illustrated in fig. 7.Heising modulation device is described with reference to Fig. 8
6215 course of work.The receiving power inductance L of Heising modulation device 6215 exciting current sampled signal Vcs, as shown in figure 4, should
Sampled signal Vcs is the pressure drop that inductance exciting current is formed on current sampling resistor Rs when power switch M1 is turned on.Sampling
Signal Vcs inputs peak comparator 702 and latched comparator 701 respectively.Sampled signal Vcs and peak comparator 702 threshold value
VH compares, and works as Vcs>VH, then the peak detection signal OCP shown in Fig. 8, signal triggering pwm signal step-down are produced, and then closed
Power switch M1, therefore peak point current is limited by threshold value VH.Sampled signal Vcs simultaneously and latched comparator 701 threshold value VL
Compare, the relatively moment is latched comparator 701 and is set as that pwm signal uprises moment by low, i.e. power tube conducting moment, compares
As a result it is latched comparator 701 to latch, refreshes until by the fiducial value at next relatively moment, what latched comparator 701 exported
Comparison signal is DLT.Narrow pulse signal caused by DLT signals and narrow-pulse generator 703 carries out logical operation, produces pulse
The control signal SH and SL of integrator 704.Pwm signal inputs narrow-pulse generator 703 as input signal respectively and delay is controlled
Device 705 processed.As shown in figure 8, narrow pulse signal PST caused by narrow-pulse generator 703 is triggered by the trailing edge of PWM signals.
PST signals do logical operation with DLT signals, obtain control signal SH, SL of pip integrator 704.Pwm signal input delay
After controller 705, under the output signal VCH of pip integrator 704 control, the postpones signal PWMD of pwm signal is produced.Such as
Shown in Fig. 8, VCH is a voltage integrating meter signal, and VCH voltage is higher, and PWMD is longer relative to the time delay of pwm signal.After
Shown in continuous reference chart 8, pip integrator 704 is controlled by signal SH and SL, and when DLT is low level, SH signals occur one
Individual positive burst pulse, makes the output signal VCH of pip integrator 704 reduce a small amount of Δ V of a single orderCH;And when DLT is high level
When, there is a negative sense burst pulse in SL signals, the output signal VCH of pip integrator 704 is raised a small amount of Δ V of a single orderCH。
With VCH reduction, PWMD time delay td is shorter and shorter, it means that and the inductance L demagnetization time is also shorter and shorter, because
This, in ccm mode, inductance demagnetization end point, while be also excitation starting point electric current gradually increase, when inductance exciting current
Sampled signal Vcs after the magnitude of voltage of excitation starting point reaches the threshold voltage VL of latched comparator 701, output current Io will
Converge on IHAnd ILBetween:
Wherein, IHAnd ILIt is the bound of output current, it latches (Latch) ratio by the threshold value VH of peak comparator 702
Threshold value VL and current sampling resistor Rs compared with device are set.
Fig. 9 shows the controlled oscillator circuit diagram of the embodiment of the utility model one.With reference to shown in figure 9, controlled concussion utensil
There are control terminal PWMD and output end CLK, and include 4 phase inverter INV1, INV2, INV3, INV4, nor gate NOR, Yi Jiyou
Current source Ib, the inverting delay unit 901 that PMOS M1, M2, NMOS tube M3 and delay electric capacity Cd are formed.The of nor gate NOR
One input connects PWM postpones signals, the input of the output end connection inverting delay unit 901 of nor gate, inverting delay list
The output end of member 901 is sequentially connected 4 phase inverters, wherein the output end connection nor gate NOR of the 3rd phase inverter the second input
End, the output end output clock signal clk of the 4th phase inverter.It is appreciated that the quantity of phase inverter can change, still
The signal for feeding back to nor gate NOR the second input is always the paraphase of clock signal clk.When PWMD is low level, by
It is exactly a typical 5 rank loop oscillator to control oscillator.Example as shown in Figure 5, CLK signal are a square-wave signals, its low level
Duration TLIt is a constant, it is set as by the inverting delay unit 901 in Fig. 9:
Wherein, IM2It is PMOS M2 drain current, Cd is delay electric capacity, and Vt is INV1 turn threshold.
As seen from Figure 5, the trailing edge of the trailing edge triggering CLK signal of PWMD signals, i.e. PWMD signal decidings CLK signal
High level lasting time.
Figure 10 illustrates the PWM generator in the constant-current controller of the embodiment of the utility model one.With reference to shown in figure 10,
PWM generator is made up of a d type flip flop DFF." D " input input logic " 1 " signal of d type flip flop, " CLK " input are defeated
Enter clock signal " CLK ", the peak detection signal " OCP " of " CLR " input input power inductive current, the output of " Q " output end
Pulse-modulated signal PWM.Return to shown in Fig. 5, the trailing edge triggering pwm signal of CLK signal is changed into logical one from logical zero;And
OCP signals make pwm signal become logical zero by logical one.Pwm signal further inputs pwm driver, and produces power and open
Drive signal is closed, when pwm signal is logical one, power switch drive signal is high level, and power switch turns on;Pwm signal is
During logical zero, power switch drive signal is low level, and power switch ends.
Figure 11 is the power source generator and pwm driver of the utility model embodiment.Knot based on this power source generator
Structure, constant current switch chip can be made to save power supply capacitor.As shown in figure 11, power source generator includes a technotron
JF1, a diode D1, a control level power supply 1101 and a driving level power supply 1102.Level power supply 1102 is driven to include one
Individual diode D2 and an electric capacity CB, its output voltage are:
VDDG=Vp- Δs Vp-VD (5)
Wherein Vp is technotron JF1 pinch-off voltage, and Δ Vp is JF1 overdrive voltage, and VD is diode D2
Forward voltage drop;
Level power supply 1101 is controlled to be made up of an operational amplifier (OPA), two resistance and a filter capacitor C1, its
Output voltage is:
Wherein Vref is reference voltage caused by chip internal a reference source, and R1, R2 are a pair of divider resistances.
The conventional power source controller core that the power supply of power supply and driving stage for internal control level is combined into one
Piece, when power switch turns on moment, chip needs to provide gate charges of the very big immediate current to power switch, and in chip
Portion can not integrate big filter capacitor again, and therefore, if not having externally fed electric capacity, the internal electric source of whole chip can be rapid
Drag down, and then make the operation irregularity of chip controls level.Therefore, the feeder ear of traditional power-supply controller of electric chip needs to be brought out,
And Large Copacity power supply capacitor is connected outside piece, to ensure that the internal electric source of chip is not pulled low.
In the constant current switch chip of the utility model embodiment exemplified by Figure 11, power supply is divided into driving level power supply 1102
With control two parts of level power supply 1101, powered respectively to driving stage and controlled stage.The feeder ear of driving stage is VDDG, controlled stage
Feeder ear is VDD.As shown in figure 12, when pwm signal uprises moment by low, the upper driving tube MP of pwm driver is switched on, Figure 11
The voltage VDDG of on-chip capacitance CB in middle driving level power supply 1102 is dragged down rapidly, technotron JF1 source S in figure
Also decrease, due to diode D1 barrier, electric current can't be extracted from control level power supply 1101, therefore controlled stage is powered
Voltage VDD (voltage on piece on decoupling capacitance C1) amplitude of variation is much smaller than the amplitude of variation of VDDG voltages, therefore, even if
The outer power supply capacitor of big piece is saved, the controlled stage of chip can also normal work.Figure 12 illustrates turns on moment, power in PWM
Pipe Gate, VDD, VDDG voltage change.Shown in Figure 12, when PWM uprises moment, for the grid capacitance to power switch
Charging, VDDG voltage dragged down rapidly, but due to diode D1 reverse iris action, VDD change is much smaller,
Chip controls level work will not be caused abnormal, thus the power supply capacitor of outside can be saved.
Constant current driving control system of the present utility model described above is used for the example for driving LED.But this constant current is driven
Autocontrol system can also be used to drive other load.Figure 13 is that another embodiment of the present utility model is used for drive magnetic valve
The CCM patterns decompression constant current driving system of load, its difference with system shown in Figure 4 is that output loading 1330 is a line solenoid valve
Circle, the load equivalent is in the series connection of an inductance and a resistance.Also, the inductance of voltage-dropping type constant current driving stage 1320 is moved to
Output stage, the part as magnetic valve load.Shown in the operation principle and mode of operation and Fig. 4 of system shown in Figure 13
LED constant current drive system is identical.Here be noted that the utility model proposes constant current driving method as shown in Figure 4
And system is equally applicable to the constant current to magnetic valve load and driven.
Figure 14 is the CCM mode constant current drive control method flow diagrams of the embodiment of the utility model one.The side of the present embodiment
Method can be implemented in circuit shown in Fig. 4 or Fig. 6 or its change case.Especially, the method for the present embodiment can with Fig. 4, Fig. 6
Implement in different constant-current controllers.With reference to shown in figure 14, comprise the following steps:
Step 1401, produce the first reference voltage and the second reference voltage, the first reference voltage are higher than the second reference voltage;
Step 1402, according to the inductance exciting current sampled voltage and the ratio of the second reference voltage on current sampling resistor
Relatively result produces PWM postpones signals;
Step 1403, clock signal is produced according to PWM postpones signals;
Step 1404, peak value inspection is produced according to the comparative result of inductance exciting current sampled voltage and first reference voltage
Survey signal;
Step 1405, pwm signal is produced according to clock signal and peak detection signal, wherein peak detection signal triggers
The trailing edge of pwm signal;
Step 1406, drive signal is produced according to pwm signal and provided to drive end.
Although the utility model describes with reference to current specific embodiment, ordinary skill in the art
Personnel are it should be appreciated that the embodiment of the above is intended merely to illustrate the utility model, without departing from the utility model spirit
In the case of can also make various equivalent change or replacement, therefore, as long as to upper in spirit of the present utility model
State the change of embodiment, modification will all fall in the range of following claims.