CN205596095U - Serializer based on half rate clock recovery circuit - Google Patents
Serializer based on half rate clock recovery circuit Download PDFInfo
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- CN205596095U CN205596095U CN201620089990.5U CN201620089990U CN205596095U CN 205596095 U CN205596095 U CN 205596095U CN 201620089990 U CN201620089990 U CN 201620089990U CN 205596095 U CN205596095 U CN 205596095U
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Abstract
The utility model provides a serializer based on half rate clock recovery circuit, the utility model relates to a signal conversion field, it aims at solving current serializer and has in the same serializer different clock generator and gather clock frequency and mismatch and lead to the output data error great, coexists the logic circuit output level burr, technical problem such as clock jitter and data distortion. This structure mainly includes the the first clock generator: output first clock signal for found the signal acquisition time window, a multiplex circuit: its sampling clock port receives the the first clock signal of the first clock generator output, and parallel source signal and output composite signal are received to the input, feedback clock generator, the 2nd multiplex circuit, the phase discriminator. The utility model is used for the high speed serialization of signal.
Description
Technical field
The present invention relates to signal conversion art, be specifically related to a kind of serializer based on half rate clock restoring circuit.
Background technology
Serializer receives parallel data and is converted into serial bit stream；Input signal is usually 8 bit parallel data, generally also can utilize certain encoding scheme that 8 bit data are converted into 10 bit data when upper serial output link transmits.Deserializer is then a contrary process.It receives serial data, is decoded if desired, is reconverted into the data of parallel form.Deserializer data clock to be recovered, and clock is transmitted to follow-up element together with data.In SerDes, these 2 complementary elements provide and a kind of original parallel data are converted into serial data thus carry out the effective means of high efficiency of transmission；Also having phaselocked loop (PLL) module in SerDes, it receives System Clock Reference, and by its frequency multiplication to corresponding data rate.The serial data that the clock lock using this frequency multiplication to cross is inputted by independent sampler module.
Existing serializer, particularly, uses some optocouplers in integrated circuit, have impact on operating rate, and power consumption also can rise；And optocoupler serial line unit is the longest for service life, easily cause card；There is clock jitter and data dithering；Lack detection check interface.
Summary of the invention
For above-mentioned prior art, present invention aim at providing a kind of serializer based on half rate clock restoring circuit, it aims to solve the problem that existing serializer exists clock generator collection clock frequencies different in identical serializer and do not mates and cause output error in data bigger, there is logic circuit output level burr, the technical problem such as clock jitter and data distortion simultaneously.
For reaching above-mentioned purpose, the technical solution used in the present invention is as follows:
A kind of serializer based on half rate clock restoring circuit, including parallel source signal, also includes the first clock generator: export the first clock signal, is used for building signals collecting time window；First multiplex electronics: its sampling clock port receives the first clock signal of the first clock generator output, input receives parallel source signal and outfan output mixed signal；Feedback clock generator: receive first clock generator output the first clock signal to obtain reference clock, output feedback clock signal, be used for building time delayed signal acquisition time window；Second multiplex electronics: its sampling clock port receives the feedback clock signal of feedback clock generator output, input receives mixed signal and the outfan output serial signal of the first multiplex electronics output；Second clock generator: output second clock signal, is used for building recovery signals collecting time window；Clock data recovery circuit: have Semi-digital inside and outside ring structure, its inner ring road receives the second clock signal of second clock generator output and receives serial signal, exports the parallel signal relative to serial signal half frequency.
In such scheme, it is preferable that described clock data recovery circuit, including inner ring road: including phaselocked loop, phaselocked loop output multi-phase clock signal；The outer ring being connected with phaselocked loop: including the phase discriminator of composition clock recovery loop, digital filter and phase interpolator, serial signal is inputted by phase discriminator input and multi-phase clock signal is inputted by phase interpolator.Serial signal is converted into the parallel data of two after the clock sampling of half rate, then compares generation phase place discriminative information through phase discriminator.Phase place discriminative information is simultaneously sent to ratio and the integral element of digital filter, finally produces phase control information and gives phase interpolator.The parallel signal of half frequency is the sign of serial signal, it is achieved that the feedback of output signal and detection.
Described phase discriminator, triggers circuit, decision circuit, double edge triggering circuit including sample circuit；Sample circuit trigger circuit respectively the most orthogonal clock pulses clk0 in four roads, clk90, clk180, clk270 control under to sampling input data, the sampled data under the sampled data under output clock pulses clk0, the sampled data under clock pulses clk90, the sampled data under clock pulses clk180, clock pulses clk270 respectively；The rising edge of described clock pulses clk90 postpones T/4 relative to clock pulses clk0 and arrives, the rising edge of described clock pulses clk180 postpones T/4 relative to clock pulses clk90 and arrives, the rising edge of described clock pulses clk270 postpones T/4 relative to clock pulses clk180 and arrives, and T is the cycle of clock pulses clk0, clk90, clk180, clk270；
Described phase discriminator, also include that re-synchronization triggers circuit, sample circuit triggers under clock pulses clk180 controls the sampled data under clock pulses clk0 that circuit exports, the sampled data under clock pulses clk90 carries out synchronism output, and the sampled data under clock pulses clk 180 under the control of clock pulses clk0, sample circuit being triggered circuit output, the sampled data under clock pulses clk270 carry out synchronism output；Sampled data under clock pulses clk0 after re-synchronization triggers processing of circuit is carried out XOR with the sampled data under clock pulses clk90 by decision circuit, the sampled data that sampled data under clock pulses clk90 from synchronous trigger circuit again and sample circuit trigger under clock pulses clk180 that circuit directly exports is carried out XOR, sampled data under clock pulses clk180 after re-synchronization triggers processing of circuit is carried out XOR with the sampled data under clock pulses clk270, sampled data under clock pulses clk270 from synchronous trigger circuit again is carried out XOR with the sampled data under clock pulses clk0 from sample circuit triggering circuit, respectively obtain judgement indication signal Up1, Up2, Dn1, Dn2；Double along triggering, circuit receives judgement indication signal Up1, Up2 enables double along triggering circuit output UP signal, and judgement indication signal Dn1, Dn2 enable double along triggering circuit output DN signal；Double under clock pulses clk270 controls along triggering, circuit receives judgement indication signal Up1, judgement indication signal Dn1 enables double along triggering circuit synchronization output matching UP signal and DN signal, and double under clock pulses clk90 controls along triggering, circuit receives judgement indication signal Up2, judgement indication signal Dn2 enables double along triggering circuit synchronization output matching UP signal and DN signal.
In such scheme, the 3rd multiplex electronics: its sampling clock port receives the feedback clock signal of feedback clock generator output, input receives high low logic level and outfan output differential signal.Can there is bigger loss during generating in feedback clock signal, input signal is clamped down on and difference by the 3rd multiplexer so that feedback clock signal has higher resolution for the next circuit, increases device response speed.
In such scheme, described feedback clock generator, including phase detecting circuit: receive and compare the first the most reverse clock signal and differential signal, exporting the first comparison signal；Voltage boosting-reducing circuit: receive the first comparison signal, output controls voltage signal；Reset circuit: output switching signal is to voltage boosting-reducing circuit；Frequency dividing circuit: receive the first clock signal, exports the first clock signal of half frequency；Delay circuit: reception control voltage signal is to adjust delay time, and receives the clock signal that frequency dividing circuit exports, and exports feedback clock signal.Phase detecting circuit is by the first clock signal comparison the 3rd multiplex electronics outfan differential signal of the reversion in a phase place, specifically, by the rising edge of the first clock signal of reversion and the edge of the differential signal of the 3rd multiplex electronics.When the comparison signal of phase detecting circuit output is logic high, i.e. illustrate that the first clock signal of reversion is not mated with the differential signal of the 3rd multiplex electronics.The reference time delay of delay circuit can impact controlling voltage range, specifically, reduces the order of delay circuit, reduces delay time scope, it is possible to reduces circuit complexity and electric quantity consumption, and reduces noise and shake further；After shake reduces, by increasing capacitance it is possible to increase the acquisition time window applying multiplex electronics, data more can pass through more quickly switching device.
In such scheme, it is preferable that described reset circuit, including the first comparator: export the second comparison signal；Second comparator: output the 3rd comparison signal；First or door: receive the first comparison signal and the second comparison signal；The first phase inverter being sequentially connected in series with first or door, the second phase inverter and buffer；Second or door: its input connects first or the outfan of door and the outfan of the second phase inverter；3rd phase inverter: its input connection second or the outfan of door；First audion: base stage connects the outfan of the 3rd phase inverter, emitter stage connects circuit height electricity end；Second audion: base stage connection second or the outfan of door, emitter stage connects circuit low electricity end；Primary nodal point is the outfan of first or door, is connected to delay circuit；Secondary nodal point is the outfan of buffer, is connected to the outfan of voltage boosting-reducing circuit；3rd node is the collector potential end of the first audion, is connected to the 3rd multiplex electronics；Fourth node is reference voltage potential point.The control voltage levvl that the switching signal of reset circuit output exports based on voltage boosting-reducing circuit.Voltage boosting-reducing circuit has high threshold voltage and low threshold voltage, when controlling voltage levvl less than low threshold voltage and higher than high threshold voltage, reset circuit closes voltage boosting-reducing circuit, and control voltage levvl is reset between low threshold voltage and high threshold voltage, specifically, the 50% of supply voltage is reset to.High threshold voltage scope and low threshold voltage scope are respectively supply voltage 0 to 30% and 85% to 100%.The reset circuit control to delay circuit, it is possible to control further to window the sampling of the first multiplex electronics the time, the system that improves is to the identification of data waveform and judgement speed.
In such scheme, it is preferable that second clock signal rate is 1/2nd of the first clock signal.The system clock of clock data recovery circuit is provided；Described orthogonal clock pulses, is produced by voltage controlled oscillator or is produced by the signal generator that can produce the orthogonal clock pulse each other of four roads.
Compared with prior art, the invention have the benefit that and be modulated controlling acquisition window width to gathering clock by data signal self feed back, it is thus achieved that more reasonably parallel signal turns serial signal self feed back modulation circuit structure；Data waveform rising time and trailing edge time significantly reduce；It is inherently eliminated the situation producing mistake pairing, substantially reduces the burr that pure combination logic produces.
Accompanying drawing explanation
Fig. 1 is module annexation schematic diagram of the present invention；
Fig. 2 is the embodiment of reset circuit of the present invention；
Fig. 3 is the embodiment of delay circuit of the present invention；
Fig. 4 is the embodiment of phase discriminator of the present invention.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, except mutually exclusive feature, beyond step, all can combine by any way.
The present invention will be further described below in conjunction with the accompanying drawings:
Fig. 1 is module annexation schematic diagram of the present invention, a kind of serializer based on half rate clock restoring circuit, and the first clock generator and second clock generator, it is considered to be embodied as environment can use the calibration pulse outfan of processor in electronic system to replace.During signal conversion operation, the first clock signal and serial signal are locked in the equivalent delay locked loop of feedback clock generator, and serial signal clock rate is the half of the first clock signal clock speed of the first clock signal clock speed or reversion.
Embodiment 1
Fig. 2 is the embodiment of reset circuit of the present invention, and in the present embodiment, phase inverter U4 and phase inverter U5 is the simplest time delay device, can be selected for described delay circuit and replaces phase inverter U4 and phase inverter U5 to obtain more preferable function of initializing.After replacement, fourth node is reference voltage input node, its size depends on comparator and the required threshold voltage set of comparator selected, or door U3 the second comparison signal based on comparator U1 and comparator U2 output, the 3rd comparison signal, generate the first control signal, or the first control signal of door U3 output sends to primary nodal point.Delay circuit is by the first control signal time delay, and the reference voltage that fourth node inputs is depended in time delay interval, and specifically, delay time depends on that reference voltage extent that fourth node inputs and reference voltage difference are loaded in the first control signal the time used.
Embodiment 2
Fig. 3 is the embodiment of delay circuit of the present invention, the buffer U9-U12 of series connection, and classification time is access in tunable capacitor C1-C3；5th node and the 7th node are input node, and the 6th node is output node；7th node accesses voltage boosting-reducing circuit, and voltage boosting-reducing circuit controls the capacitance of tunable capacitor, and buffer U9-U12 produces Phase delay.
Embodiment 3
Described voltage boosting-reducing circuit, i.e. BOOST circuit, can carry out reducing replacement according to spatial volume situation shared by actually used circuit；As, when needing less circuit space volume, can change and elect electric charge pump as.Electric charge pump, its energy storage device can be electric capacity, and outfan is multiple series connection and the collector and emitter of the complementary audion of raceway groove about outfan symmetry, and input is the base stage of multiple audion, the logic realized as required adds certain gate in base stage, it is achieved electric charge pump；Relative to BOOST circuit, electric charge pump cloth plate bulk is relatively small, and circuit structure need not inductance, and response speed is exceedingly fast.
Embodiment 4
Fig. 4 is the embodiment of phase discriminator of the present invention, sampled data D0 under clock pulses clk0, sampled data D90 under clock pulses clk90, sampled data D180 under clock pulses clk180 is the data sample point of continuous sampling three times, in like manner sampled data D180 under clock pulses clk180, sampled data D270 under clock pulses clk270, sampled data D0 under clock pulses clk0 is also for the data sample point (D0 now is D360) of continuous sampling three times.Because (i.e. equal to two data cycles) in the half rate clock cycle, there is a data sample point of two groups of continuous samplings three times: (D0, D90, and (D180 D180), D270, D0), explain the subsequent treatment situation of these two groups of data sample points the most separately below, thus be easier to understand the operation principle of phase discriminator.
The data sample point that first group of continuous sampling is three times: D0, D90, D180.Clock pulses clk0, clk90 and clk180 acts on trigger 301 ~ 303, continuous three sampling input data data successively, therefore creates three data sample point D0, D90, D180.Wherein D0 and D90 carries out xor operation generation judgement indication signal Up1；D90 and D180 carries out xor operation and produces judgement indication signal Dn1.To make signal Up1 and Dn1 in synchronization output and effectively, then requiring D0, D90 and D180 in synchronization output and effectively, therefore the necessary re-synchronization of D0, D90 and D180 is in a clock signal.The present invention uses clk180 to act on trigger 311 and 312, D0 and D90 of re-synchronization, produces signal D0_1 and D90_1 after re-synchronization respectively, in conjunction with D180, by XOR gate 321 and 322, creates judgement indication signal Up1 and Dn1 respectively.Next clock after clk180 is along being clk270, and therefore to use clk270 to act on double along trigger 331 and 332 for the present invention, resynchronisation once judgement indication signal Up1 and Dn1, thus produce final UP and DN signal.
The data sample point that second group of continuous sampling is three times: D180, D270, D0.In like manner, clock pulses clk180, clk270 and clk0(clk0 now is clk360) act on trigger 303 successively, 304 and 301, continuous three sampling input data data, therefore create three data sample point D180, D270, D0(D0 now is D360).Wherein D180 and D270 carries out xor operation generation signal Up2；D270 and D0 carries out xor operation and produces signal Dn2.To make signal Up2 and Dn2 in synchronization output and effectively, then requiring D180, D270 and D0 in synchronization output and effectively, therefore the necessary re-synchronization of D180, D270 and D0 is in a clock signal.The present invention uses clk0 to act on trigger 313 and 314, D180 and D270 of re-synchronization, produces D180_1 and D270_1 respectively, is D360 in conjunction with D0(D0 now), by XOR gate 323 and 324, create Up2 and Dn2 signal respectively.Clk0(clk0 now is clk360) after next clock along being clk90, therefore to use clk90 to act on double along trigger 331 and 332 for the present invention, resynchronize a Up2 and Dn2 signal, thus produce final UP and DN signal.
The above; being only the detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, any those skilled in the art of belonging to are in the technical scope that the invention discloses; the change that can readily occur in or replacement, all should contain within protection scope of the present invention.
Claims (4)
1. a serializer based on half rate clock restoring circuit, including parallel source signal, it is characterised in that also include
First clock generator: export the first clock signal, is used for building signals collecting time window；
First multiplex electronics: its sampling clock port receives the first clock signal of the first clock generator output, input receives parallel source signal and outfan output mixed signal；
Feedback clock generator: receive first clock generator output the first clock signal to obtain reference clock, output feedback clock signal, be used for building time delayed signal acquisition time window；
Second multiplex electronics: its sampling clock port receives the feedback clock signal of feedback clock generator output, input receives mixed signal and the outfan output serial signal of the first multiplex electronics output；
Second clock generator: output second clock signal, is used for building recovery signals collecting time window；
Clock data recovery circuit: have Semi-digital inside and outside ring structure, its inner ring road receives the second clock signal of second clock generator output and receives serial signal, exports the parallel signal relative to serial signal half frequency；
Described clock data recovery circuit, its inner ring road: including phaselocked loop, phaselocked loop output multi-phase clock signal, the outer ring being connected with phaselocked loop: including the phase discriminator constituting clock recovery loop, digital filter and phase interpolator, serial signal is inputted by phase discriminator input and multi-phase clock signal is inputted by phase interpolator；
Described phase discriminator, triggers circuit, decision circuit including sample circuit, double triggers circuit along triggering circuit and re-synchronization, sample circuit trigger circuit respectively under the control of the most orthogonal clock pulses in four roads to sampling input data.
A kind of serializer based on half rate clock restoring circuit the most according to claim 1, it is characterised in that also include
3rd multiplex electronics: its sampling clock port receives the feedback clock signal of feedback clock generator output, input receives high low logic level and outfan output differential signal.
A kind of serializer based on half rate clock restoring circuit the most according to claim 1, it is characterised in that described feedback clock generator, including
Phase detecting circuit: receive and compare the first the most reverse clock signal and differential signal, exporting the first comparison signal；
Voltage boosting-reducing circuit: receive the first comparison signal, output controls voltage signal；
Reset circuit: output switching signal is to voltage boosting-reducing circuit；
Frequency dividing circuit: receive the first clock signal, exports the first clock signal of half frequency；
Delay circuit: reception control voltage signal is to adjust delay time, and receives the clock signal that frequency dividing circuit exports, and exports feedback clock signal.
A kind of serializer based on half rate clock restoring circuit the most according to claim 1, it is characterised in that described orthogonal clock pulses, is produced by voltage controlled oscillator or is produced by the signal generator that can produce the orthogonal clock pulse each other of four roads.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620089990.5U CN205596095U (en) | 2016-01-29 | 2016-01-29 | Serializer based on half rate clock recovery circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620089990.5U CN205596095U (en) | 2016-01-29 | 2016-01-29 | Serializer based on half rate clock recovery circuit |
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| CN205596095U true CN205596095U (en) | 2016-09-21 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553470A (en) * | 2016-01-29 | 2016-05-04 | 成都科创谷科技有限公司 | Serializer based on half rate clock recovery circuit |
| CN111092714A (en) * | 2019-12-10 | 2020-05-01 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
-
2016
- 2016-01-29 CN CN201620089990.5U patent/CN205596095U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553470A (en) * | 2016-01-29 | 2016-05-04 | 成都科创谷科技有限公司 | Serializer based on half rate clock recovery circuit |
| CN105553470B (en) * | 2016-01-29 | 2018-08-03 | 成都科创谷科技有限公司 | A kind of serializer based on half rate clock restoring circuit |
| CN111092714A (en) * | 2019-12-10 | 2020-05-01 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
| CN111092714B (en) * | 2019-12-10 | 2022-05-06 | 中国科学院微电子研究所 | High-speed signal clock recovery method and device |
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Granted publication date: 20160921 Termination date: 20170129 |