CN205193786U - Towards two redundant assembly linies of selfreparing of SPARC V8 treater - Google Patents
Towards two redundant assembly linies of selfreparing of SPARC V8 treater Download PDFInfo
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- CN205193786U CN205193786U CN201520998896.7U CN201520998896U CN205193786U CN 205193786 U CN205193786 U CN 205193786U CN 201520998896 U CN201520998896 U CN 201520998896U CN 205193786 U CN205193786 U CN 205193786U
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Abstract
The utility model provides a towards two redundant assembly linies of selfreparing of SPARC V8 treater which characterized in that: the two redundant assembly linies of selfreparing include assembly line A, assembly line B, instructions cache (301), self -check module, comparison logic (501), assembly line recovery module (601), data buffering (701), register file (801), the two redundant assembly linies of selfreparing adopt and set up the comparator carry out fault detection to the assembly line unit between two assembly linies, utilize self -check pair of module interstage register to carry out the check -up and orient the failure flow waterline, carry out the method recovered to the assembly line according to comparative result and self -check error message, carry on fault -tolerantly to SEU, SET and the MBU trouble of single event effect initiation.
Description
Technical field
The utility model relates to a kind of detect and recovery device of microprocessor pipeline mistake, particularly relates to the detect and recovery device of streamline mistake in a kind of SPARCV8 processor.
Background technology
Single-particle inversion (SingleEventUpset, SEU) be under the applied environment of space, because single-particle incidence causes the event of storage unit generation Data flipping mistake in integrated circuit, be that under space environment, electronic system breaks down and one of the major incentive of operation irregularity.Along with the fast development of semiconductor process techniques, the size of chip is in continuous reduction, and processor working frequency improves constantly, and the reduction of node operating voltage makes single-particle inversion phenomenon more and more serious.Research is pointed out, in nanoscale chip, long numeric data upset (MBU) probability that single-particle inversion causes, also in rapid raising, can cause maximum 8 random data upset mistake, produce larger harm to the electronic system of space application.In microprocessor and electronic system, take reinforcement measure to carry out to SEU fault the technological means that fault-tolerant design become important.
As the important component part of Modern microprocessor, the instruction stream that streamline mainly completes program code performs, and execution result is write data storage and register file.If the misdata that single-particle bombarding stream waterline causes grade inter-register to occur to overturn or single-event transients (SET) causes is latched, streamline execution result will be caused incorrect, when not having pipeline unit to carry out fault-tolerant reinforcing, the execution result of mistake will be diffused into the instruction stream of data storage and register file or execution error, and then causes much more uncontrollable mistakes to produce.Therefore, for the highly reliable microprocessor of space application, the fault-tolerant design carrying out pipelined units has great importance.
The existing reinforcement technique to space microprocessor has following three kinds of schemes: adopt time-based fault-tolerance approach, can effectively solve MBU problem, but processor performance reduces greatly; Adopt the fault-tolerance approach based on coding, can only the correctness of effective verification computation part, and different coded systems can not all process for different single-particle faults, and fault-tolerant ability is limited; Adopt the scheme based on hardware redundancy, when adopting register stage triplication redundancy as shown in Figure 1, MBU fault cannot be tackled; When adopting pipeline stages triplication redundancy as shown in Figure 2, although can orient failure flow waterline, the expenses such as hardware resource power consumption are larger; Pipeline stages duplication redundancy can tackle MBU fault, but cannot locate, do not have the effect of shielding fault, all carry out streamline rollback at every turn and significantly can increase track performance expense, especially bulk treatment speed can be caused obviously to reduce when single-particle fault is day by day common.In a word, prior art cannot realize one with low area overhead and can fault detect, location, shielding fault successfully manage the CPU Scheme of Strengthening of MBU fault.
Summary of the invention
The purpose of this utility model is to design a kind of two redundancy flowing water of selfreparing of the processor towards SPARCV8, effectively can shield single-particle inversion (SEU), long numeric data upset fault that single-ion transient state (SET) causes system architecture.
For achieving the above object, the technical scheme that the utility model adopts is:
The two redundancy streamline of selfreparing towards SPARCV8 processor, is characterized in that: the two redundancy streamline of described selfreparing comprises assembly line A, streamline B, instruction buffer (301), self checking module, Compare Logic (501), streamline recovery module (601), data buffer storage (701), register file (801), described assembly line A comprises fetching (101), decoding (102), perform (103), memory access (104), write back (105) five flowing water sections, described streamline B comprises fetching (201), decoding (202), perform (203), memory access (204), write back (205) five flowing water sections, between assembly line A and each flowing water section of streamline B, a grade inter-register is set respectively, data buffer storage (701) and register file (801) are shared by assembly line A and streamline B, the execution result of assembly line A is entered for the default write when performing instruction stream, when assembly line A execution error, the execution result of write streamline B, described instruction buffer (301) performs the code of instruction for storage flow waterline, gives the instruction fetching component of assembly line A and streamline B, described self checking module comprises self checking (401), self checking (402), self checking (403), self checking (404) and self checking (405), self checking is carried out for the level inter-register in assembly line A and streamline B, producing check errors information, sending into Compare Logic (501) for locating the streamline that single-particle fault occurs, described Compare Logic (501) is arranged between assembly line A and streamline B, for comparing the output information of two pipelined units, detects the mistake of streamline, described streamline recovers module (601) for after streamline mistake appears in Compare Logic (501) and the detection of self checking module, according to location of mistake result, by fast quick-recovery or overall reset mode, the state to the streamline of mistake or two streamlines is recovered, the data that described data buffer storage (701) exports for storage flow waterline, co-current flow waterline provides arithmetic operation number, the data that described register file (801) exports for storage flow waterline, co-current flow waterline provides arithmetic operation number.
The two redundancy streamline of the selfreparing towards SPARCV8 processor that the utility model realizes, adopt the thought of hardware redundancy, traditional pipeline stages dual modular redundancy is improved, at key node, comparer is set, prevent misdata from flowing out outside structure (high-speed cache, register file), pipeline level inter-register increases self checking module simultaneously, can quick position failure flow waterline according to check results, startup separator mask pattern, SET, SEU of being caused by single-particle for solution and day by day serious MBU provide technical guarantee.
Accompanying drawing explanation
Fig. 1 is register stage triplication redundancy structural drawing;
Fig. 2 is pipeline stages triplication redundancy structural drawing;
Fig. 3 is LEON2 processor pipeline cellular construction figure;
Fig. 4 is the structural drawing according to the two redundancy streamline of selfreparing of the present utility model.
Embodiment
Streamline (Self-RecoveryDualPipeline, SRDP) in the two redundancy of selfreparing, be a kind of with LEON2 processor for platform, the pipelined units towards RISC framework carries out the apparatus and method of reinforcing.LEON2 is the flush bonding processor based on SPARCV8 architecture, adopts the RISC framework of 32, and its pipelined units is classical five-stage pipeline.
Pipelined units in LEON2 processor comprises fetching (IF), decoding (ID), performs (EX), memory access (ME), writes back (WR) five combinatorial logic unit, and level inter-register IF, IF/ID, ID/EX, EX/ME, ME/WR of arranging between each flowing water section, as shown in Figure 3.The combinational logic part of single-particle bombarding stream waterline, produce burr and may be occurred SET fault by inter-stage registers latch, register can be directly caused to occur SEU or MBU fault during bombardment level inter-register, the key message that combinational logic produces is deposited and in inter-stage transmission by level inter-register, the execution result that the level inter-register depositing error message can lead to errors, and error result can be written into data-carrier store or register file in ME or WR section.
In order to effectively tackle the single-particle soft error that radiation causes, especially MBU problem.Consider each scheme Time and place expense, based on the thought of hardware redundancy, adopt the pipeline stages dual modular redundancy that resource overhead is less, the instruction stream that executed in parallel is identical, at key node, the information that comparer compares two streamlines is set, once streamline is subject to single-particle bombardment and breaks down, comparer will detect mistake, and (two streamline occurs that identical probability of malfunction is very little in execution instruction process, here ignore), stop error result to flow out; Meanwhile, in order to realize fault location function, pipeline level inter-register increases self checking module, detects the correctness of inter-stage registered data, when particle bombardment streamline causes register to overturn, then and this streamline rub-out signal position of set; Last comparing result is different, judge problem streamline, the current state of correct streamline is then utilized to replace error pipeline, consume a clock period, realize fast quick-recovery, when occurring that SET mistake is latched, level inter-register self checking module cannot judge mistake, the mode then adopting two streamline rollbacks to recover, ensures the normal operation of streamline.This kind of mechanism can effectively reduce the performance cost that streamline recovers to cause, and the concrete recovery scheme of the two redundancy streamline of selfreparing is as shown in table 1.The correctness of all functions element in SRDP structure verification streamline, ensure that streamline normally runs, comparator signal contrast is identical, then pipeline data is spread out of external unit (register file, storer etc.).
Table 1 streamline recovery scheme
Based on above-mentioned ultimate principle and setting, a kind of embodiment that the embedded microprocessor pipelined units towards SPARCV8 architecture of the present utility model is reinforced is as follows:
In the flush bonding processor of SPARCV8, pipelined units is arranged to as shown in Figure 4, mainly comprises assembly line A, streamline B, Instruction Register (301), self checking module, Compare Logic (501), streamline recovery module (601), data buffer storage (701), register file (801).
Assembly line A and streamline B comprise fetching (IF), decoding (ID), perform (EX), memory access (ME), write back (WR) combinatorial logic unit, and the level inter-register (IF, IF/ID, ID/EX, EX/ME, ME/WR) arranged between each pipelining-stage, article two, streamline has a set of data path separately, share data storage, instruction storage and register file simultaneously, when executed in parallel same instructions stream, the execution result of acquiescence assembly line A carries out data interaction with outside storage unit and register file, and streamline B is backup units.
The code that instruction buffer (301) performs for storage flow waterline, carries out data interaction with IF section in assembly line A, and assembly line A is distributed to two streamlines and performs after taking out instruction.
Self checking module is divided into Code And Decode two parts, comprise self checking (401), self checking (402), self checking (403), self checking (404) and self checking (405), level inter-register in pipeline A and streamline B carries out self checking, providing error message, sending into Compare Logic for locating the streamline that single-particle fault occurs.
Compare Logic (501) is arranged between assembly line A and streamline B, the information mutual with processor miscellaneous part is needed to compare for pipelined units, because fetching section needs to take out instruction according to instruction address from command memory, decoding section needs to obtain operand from register file, execution section and memory access Duan Junhui produce the mutual information of and instruction storer, data can be write register file by the section of writing back, the interactive information of five pipelining-stages is needed to compare, avoid streamline generation common mode mistake or misdata write in data storage and register file.
Streamline recovers module (601) must ensure that RS state can not be changed by improper value, provide information according to self checking module and Compare Logic and be divided into quick reset mode and overall reset mode, if comparative result is identical, show do not have mistake or inter-stage mistake not to affect instruction results, continuation performs by instruction; Otherwise, the streamline broken down is oriented in the error message of query level inter-register, quick reset mode is then adopted to recover pipeline state with low expense, play fault masking effect, continue to perform instruction, if failure flow waterline cannot be oriented, then adopt overall reset mode, with the overall reset mode amendment streamline mistake that relative time expense is higher, ensure reliability.
The data that data buffer storage (701) and register file (801) need for storage flow pipeline units, pipelined units can carry out read-write operation to register file and data buffer according to instruction word, the information provided with assembly line A is carried out alternately, execution result is write register file and data buffer by assembly line A, or therefrom sense data is distributed to two stream line operations.
The two redundancy streamline of the described selfreparing towards SPARCV8 processor adopts the misdata in following steps and method pipeline to carry out detecting and processing:
(1) fetching section, self checking module can carry out self checking, generation error information to the fetching section level inter-register of two streamlines, and Compare Logic is sent in error message, is deposited with decoding section level inter-register simultaneously; After the decoding section section of two streamlines provides the interactive information of and instruction buffer memory, Compare Logic can compare it, if comparative result is identical, failure flow waterline, by instruction fetching streamline, if comparative result is not identical, is oriented according to the error message that self checking module provides in the address then provided with assembly line A, enable quick recovery scheme, replace error pipeline with correct streamline, consume a clock period, re-start current operation at following clock cycle; If cannot orient error pipeline, then two streamlines enter trap;
(2) decoding section, self checking module can carry out self checking to the decoding section level inter-register of two streamlines, generation error information bit, this error message position can be carried out with the error message position of depositing in decoding section level inter-register or computing send into Compare Logic, performs section simultaneously and is deposited with a grade inter-register; After the interactive information that the decoding section of two streamlines provides with register file, Compare Logic can compare it, if comparative result is identical, then from register file, take out source operand by the output information of assembly line A, and be distributed to two stream line operations, if comparative result is not identical, orient failure flow waterline according to self checking module, enable quick recovery scheme, replace error pipeline with correct streamline, consume a clock period, re-start current operation at following clock cycle; If failure flow waterline cannot be oriented, then provide the id signal needing to carry out streamline rollback, give two streamlines by this signal feedback, and be deposited with to perform in section level inter-register and flow to next pipelining-stage;
(3) section is performed, self checking module can carry out self checking to the execution section level inter-register of two streamlines, generation error information bit, this error message position can be carried out with the error message position performing section level inter-register or computing send into Compare Logic, is deposited with memory access section level inter-register simultaneously, the execution section of two streamlines provide with the interactive information of a data buffer storage part after, Compare Logic can compare it, if comparative result is identical, then the output information of assembly line A is sent into data buffer storage, if comparative result is not identical, failure flow waterline is oriented according to self checking module, enable quick recovery scheme, error pipeline is replaced with correct streamline, consume a clock period, current operation is re-started at following clock cycle, if failure flow waterline cannot be oriented, then provide the id signal needing to carry out streamline rollback, two streamlines are given by this signal feedback, and be deposited with in memory access section level inter-register and flow to next pipelining-stage,
(4) memory access section, self checking module can carry out self checking generation error information bit to the memory access section level inter-register of two streamlines, this error message position can be carried out with the error message position of memory access section level inter-register or computing send into Compare Logic, is deposited with the section of writing back level inter-register simultaneously, provide and data buffer storage another part interactive information at two streamlines, comparison module can compare it, if comparative result is identical, the information exported by assembly line A sends into data buffer storage, if comparative result is not identical, the write enable signal of forbidden data buffer memory, orient failure flow waterline according to self checking module simultaneously, enable quick recovery scheme, error pipeline is replaced with correct streamline, consume a clock period, current operation is re-started at following clock cycle, if failure flow waterline cannot be oriented, then provide the id signal needing to carry out streamline rollback, two streamlines are given by this signal feedback, and be deposited with in the section of writing back level inter-register and flow to next pipelining-stage,
(5) section of writing back, self checking module can carry out self checking generation error information bit to the section of the writing back level inter-register of two streamlines, and this error message position can be carried out with the error message position of the section of writing back level inter-register or send into Compare Logic after computing, two streamline sections of writing back provide with register file reading writing information after, Compare Logic can compare it, if comparative result is identical, by the write information of assembly line A send into register file, if comparative result is not identical, the write enable signal of disable register heap, orient failure flow waterline according to self checking module simultaneously, enable quick recovery scheme, error pipeline is replaced with correct streamline, consume a clock period, current operation is re-started at following clock cycle, if cannot error pipeline be oriented, then provide the id signal needing to carry out streamline rollback, this id signal is fed back to two streamlines, rollback id signal and the rollback id signal in the section of writing back level inter-register are done or computing, if two the section of the writing back instruction of streamline needs to carry out rollback, then enable the overall reset mode of streamline, streamline is emptied, from instruction buffer, take out the instruction of breaking down re-execute, consume five clock period, causing SET fault to single-particle carries out fault-tolerant.
In the scope not departing from the utility model spirit, the utility model can have various deformation, as: the flowing water progression of streamline, the method for self checking, the selection etc. of comparison signal, all can change in different enforcement.These distortion are also contained within the utility model scope required for protection.
Claims (1)
1. towards the two redundancy streamline of selfreparing of SPARCV8 processor, it is characterized in that: the two redundancy streamline of described selfreparing comprises assembly line A, streamline B, instruction buffer (301), self checking module, Compare Logic (501), streamline recovery module (601), data buffer storage (701), register file (801), described assembly line A comprises fetching (101), decoding (102), perform (103), memory access (104), write back (105) five flowing water sections, described streamline B comprises fetching (201), decoding (202), perform (203), memory access (204), write back (205) five flowing water sections, between assembly line A and each flowing water section of streamline B, a grade inter-register is set respectively, data buffer storage (701) and register file (801) are shared by assembly line A and streamline B, the execution result of assembly line A is entered for the default write when performing instruction stream, when assembly line A execution error, the execution result of write streamline B, described instruction buffer (301) performs the code of instruction for storage flow waterline, gives the instruction fetching component of assembly line A and streamline B, described self checking module comprises self checking (401), self checking (402), self checking (403), self checking (404) and self checking (405), self checking is carried out for the level inter-register in assembly line A and streamline B, producing check errors information, sending into Compare Logic (501) for locating the streamline that single-particle fault occurs, described Compare Logic (501) is arranged between assembly line A and streamline B, for comparing the output information of two pipelined units, detects the mistake of streamline, described streamline recovers module (601) for after streamline mistake appears in Compare Logic (501) and the detection of self checking module, according to location of mistake result, by fast quick-recovery or overall reset mode, the state to the streamline of mistake or two streamlines is recovered, the data that described data buffer storage (701) exports for storage flow waterline, co-current flow waterline provides arithmetic operation number, the data that described register file (801) exports for storage flow waterline, co-current flow waterline provides arithmetic operation number.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105320579A (en) * | 2015-10-27 | 2016-02-10 | 首都师范大学 | Self-repairing dual-redundancy assembly line oriented to SPARC V8 processor and fault-tolerant method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105320579A (en) * | 2015-10-27 | 2016-02-10 | 首都师范大学 | Self-repairing dual-redundancy assembly line oriented to SPARC V8 processor and fault-tolerant method |
| CN105320579B (en) * | 2015-10-27 | 2018-03-23 | 首都师范大学 | Towards the selfreparing dual redundant streamline and fault-tolerance approach of SPARC V8 processors |
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Granted publication date: 20160427 Effective date of abandoning: 20180323 |