CN204964957U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN204964957U CN204964957U CN201520756091.1U CN201520756091U CN204964957U CN 204964957 U CN204964957 U CN 204964957U CN 201520756091 U CN201520756091 U CN 201520756091U CN 204964957 U CN204964957 U CN 204964957U
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- base palte
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Abstract
The present disclosure provides an array substrate, including many grid lines, with many criss -cross data lines of grid line, per two grid lines and the pixel of data line definition who corresponds, each pixel includes thin film transistor, the grid insulating layer, passivation layer on arranging on one side of the grid insulating layer, the pixel electrode and NULL, wherein thin film transistor's source electrode and drain electrode are arranged between passivation layer and the grid insulating layer, NULL arranges on the opposite side of the grid insulating layer relative with the passivation layer, the pixel electrode arranges on the passivation layer. This openly still provides a display device.
Description
Technical field
The disclosure relates generally to display technique field.More specifically, the disclosure relates to a kind of array base palte and display device.
Background technology
Along with the development of Thin Film Transistor (TFT) liquid crystal display (TFT-LCD) technology and the progress of industrial technology, the production cost of liquid crystal display continues to reduce and manufacturing process is day by day perfect, thus replaces cathode-ray tube display and becomes the mainstream technology in flat display field.Advantages such as the volume that TFT-LCD display has because of itself is little, low in energy consumption, radiationless and become desirable display device.
At present, TFT-LCD can be divided into according to display mode: twisted-nematic (TN, TwistedNematic) type, plane conversion (IPS, InPlaneSwitching) type and senior super dimension field switch (ADS, AdvancedSuperDimensionSwitch) type.Wherein, the electric field that the electric field that ADS type TFT-LCD is produced by gap electrode edge in same plane usually and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, to make between the gap electrode in liquid crystal cell and all aligned liquid-crystal molecules directly over electrode can both produce rotation, thus improve liquid crystal work efficiency and increase light transmission efficiency.ADS technology can improve the picture quality of TFT-LCD product, make display device have high resolving power, high permeability, low-power consumption, wide viewing angle, high aperture, low aberration, without advantages such as water of compaction ripples (pushMura).
Fig. 1 illustrates the cross sectional representation of prior art ADS type array base palte.As shown in Figure 1, from bottom to up, array base palte comprises pixel electrode 3, the grid of thin film transistor (TFT) and public electrode line graph (not shown) that same layer arranges, gate insulator 7, passivation layer 8, the source electrode of thin film transistor (TFT), drain electrode and data line figure 5 successively, and public electrode 2.Correspondingly, the method for making of existing ADS type array base palte generally comprises: form the pixel electrode of same layer layout, the grid of thin film transistor (TFT) and public electrode line graph on the transparent substrate; Form gate insulator; Form active layer pattern; Form the source electrode of thin film transistor (TFT), drain electrode and data line figure; Form passivation layer; And square one-tenth public electrode over the passivation layer.
Problem existing in array base palte shown in Fig. 1 is, as shown in Figure 2, both the public electrode wire 4 arranged with layer from the grid 1 of thin film transistor (TFT) and pixel electrode 3 connect different signal wires, therefore need to there is certain intervals d to ensure not having crosstalk between the signal in public electrode wire 4 and pixel electrode 3 between.Interval between public electrode wire 4 and pixel electrode 3 reduces the work efficiency of the liquid crystal of corresponding part, and then reduces the transmitance of pixel.
Utility model content
An object of the present disclosure is to provide a kind of array base palte be used in ADS type TFT-LED and preparation method thereof, and it can alleviate or eliminate problem existing in prior art at least in part.
According to first aspect of the present disclosure, provide a kind of array base palte, comprise many grid lines, the a plurality of data lines of intersecting with many grid lines and intersect the multiple pixel cells defined by many grid lines and a plurality of data lines, each pixel cell comprises thin film transistor (TFT), gate insulator, be arranged in the passivation layer on gate insulator side, pixel electrode and public electrode, wherein the source electrode of thin film transistor (TFT) and drain electrode are arranged between passivation layer and gate insulator, public electrode is arranged on the opposite side of the gate insulator relative with passivation layer, pixel electrode is arranged over the passivation layer.
Compared to above-mentioned array base palte of the prior art, in the array base palte that the disclosure provides, by the location swap by pixel electrode and public electrode, pixel electrode and public electrode wire are no longer arranged with layer, arrange interval to ensure not have the needs of crosstalk therebetween because this eliminating between pixel electrode and public electrode wire.The elimination at described interval improves the work efficiency of liquid crystal, and then improves the transmitance of pixel.
According to an embodiment, above-mentioned array base palte can also comprise to be arranged with layer with pixel electrode and to be positioned at the guarded electrode above data line.
Under executing alive situation to data line, the electric field produced by data line can cause the liquid crystal molecule of above data line and both sides effectively to deflect, thus causes the problem of light leak.In order to address this problem, can square one-tenth guarded electrode on the data line, for the electric field that shadow data line produces, thus prevent effective deflection of this electric field influence liquid crystal molecule.Inventor has been found that when there is guarded electrode, the width of black matrix can be reduced to 6-8 μm, thus greatly improves the aperture opening ratio of display device compared at least 18-28 when not having guarded electrode μm of wide black matrix.
According to another embodiment, public electrode can have matrix structure, and described public electrode comprises multiple sub-public electrode, and each pixel cell corresponds to a sub-public electrode.Alternatively, the matrix structure of public electrode is being connected by public electrode wire perpendicular on the direction of data line, and public electrode directly contacts electrical connection with public electrode wire.And alternatively, the matrix structure of public electrode is connected by connecting electrode on the direction being parallel to data line, and described connecting electrode and public electrode are arranged at different layers, and described connecting electrode is connected by via hole with adjacent sub-public electrode respectively.Particularly, described via hole is produced in gate insulator and passivation layer.
According to an embodiment, guarded electrode is being interconnected by guarded electrode connecting line perpendicular on the direction of data line, and wherein guarded electrode and guarded electrode connecting line are formed by same material.
According to another embodiment, guarded electrode can be connected identical public electrode wire with public electrode.Alternatively, guarded electrode can be connected different public electrode wires with public electrode, and the signal on different public electrode wire can be identical or different.When signal on different public electrode wire is different, the signal in guarded electrode and public electrode can be made slightly different by adding small-signal input.
According to embodiment, guarded electrode and public electrode can electrically insulated from one another, and connect different public electrode wires, and now public electrode is by the impact of the stray capacitance between guarded electrode and data line.
According to an embodiment again, owing to usually adopting the ITO with larger resistivity to make pixel electrode, therefore for preventing signal in pixel electrode from producing bad due to the large resistance of ITO, array base palte can also comprise the pixel metal electrode corresponding with pixel electrode, insulation course can be there is between pixel electrode and pixel metal electrode, and the two is interconnected by the via hole in insulation course.
According to other embodiment, pixel electrode is gap electrode, and public electrode is plate electrode.Thus, the electric field produced at gap electrode edge and the electric field produced between gap electrode layer and plate electrode layer can form multi-dimensional electric field, to make between the gap electrode in liquid crystal cell and all aligned liquid-crystal molecules directly over electrode can both produce rotation, thus improve liquid crystal work efficiency and increase light transmission efficiency.
According to second aspect of the present disclosure, provide a kind of display device comprising array base palte as described above.By the location swap by pixel electrode and public electrode, pixel electrode and public electrode wire are no longer arranged with layer, arrange interval to ensure not have the needs of crosstalk therebetween because this eliminating between pixel electrode and public electrode wire.The elimination at described interval improves the work efficiency of liquid crystal, and then improves the transmitance of pixel.
According to the third aspect of the present disclosure, provide a kind of method making array base palte as described above, comprise the following steps: the figure forming grid, public electrode and the public electrode wire comprising thin film transistor (TFT) on underlay substrate; Form gate insulator; Form the active layer of thin film transistor (TFT); Form the figure comprising the source electrode of thin film transistor (TFT), drain electrode and data line; Form passivation layer, wherein the source electrode of thin film transistor (TFT) and drain electrode are arranged between passivation layer and gate insulator; And form pixel electrode over the passivation layer.
According to embodiment of the present disclosure, said method can also comprise and forms guarded electrode over the passivation layer, and wherein guarded electrode and pixel electrode are arranged with layer, and are positioned at above data line.Guarded electrode can the electric field that produces of shadow data line, thus prevents effective deflection of this electric field influence liquid crystal molecule.
According to another embodiment of the present disclosure, said method can also be included in above pixel electrode and form pixel metal electrode, there is insulation course between pixel electrode and pixel metal electrode, and pixel electrode is connected by the via hole in insulation course with pixel metal electrode.Owing to usually adopting the ITO with larger resistivity to make pixel electrode, therefore add pixel metal electrode and can prevent signal in pixel electrode from producing bad due to the large resistance of ITO.
Accompanying drawing explanation
These and other side of the present disclosure are apparent from embodiment described below, and set forth these and other side of the present disclosure with reference to embodiment described below.In the accompanying drawings,
Fig. 1 schematically illustrates the viewgraph of cross-section of prior art array base palte;
Fig. 2 schematically illustrates the top view of array base palte of the prior art;
Fig. 3 schematically illustrates the viewgraph of cross-section of the array base palte according to embodiment of the present disclosure;
Fig. 4 schematically illustrates the top view of the array base palte according to embodiment of the present disclosure;
Fig. 5 schematically illustrates the viewgraph of cross-section of the array base palte according to another embodiment of the present disclosure;
Fig. 6 schematically illustrates and designs according to the matrix structure of the public electrode of embodiment of the present disclosure;
Fig. 7 schematically illustrates the structural design of the guarded electrode according to embodiment of the present disclosure;
Fig. 8 illustrates the analog result of the crosstalk analysis between pixel electrode and guarded electrode; And
Fig. 9 is the process flow diagram of the method for making array base palte according to embodiment of the present disclosure.
Embodiment
Fig. 3 and Fig. 4 respectively illustrates viewgraph of cross-section according to the array base palte of embodiment of the present disclosure and top view.Many grid lines are comprised according to the array base palte of embodiment of the present disclosure, the a plurality of data lines of intersecting with many grid lines and intersect the multiple pixel cells defined by many grid lines and a plurality of data lines, each pixel cell comprises thin film transistor (TFT), gate insulator 7, be arranged in the passivation layer 8 on gate insulator 7 side, pixel electrode 3 and public electrode 2, wherein the source electrode of thin film transistor (TFT) and drain electrode 5 are arranged between passivation layers 8 and gate insulator 7, public electrode 2 is arranged on the opposite side of the gate insulator 7 relative with passivation layer 8, pixel electrode 3 is arranged on passivation layer 8.
Compared to the array base palte of the prior art shown in Fig. 1, in above-mentioned array base palte, by the location swap by pixel electrode 3 and public electrode 2, namely as shown in Figure 3, pixel electrode 3 is arranged in above passivation layer 8, public electrode 2 is arranged in below gate insulator 7 (this with Fig. 1 that pixel electrode 3 is arranged in the layout be arranged in above passivation layer 8 by public electrode 2 below gate insulator 7 is contrary), pixel electrode 3 and public electrode wire 4 are no longer arranged with layer, between pixel electrode 3 and public electrode wire 4, interval is set to ensure not have the needs of crosstalk therebetween because this eliminating.As shown in Figure 4, can not there is interval between public electrode 2 and public electrode wire 4, even the two can be overlapped.The elimination at described interval thus improve the work efficiency of liquid crystal, and then improve the transmitance of pixel.
Fig. 5 illustrates the viewgraph of cross-section of the array base palte according to another embodiment of the present disclosure.The difference of Fig. 5 and Fig. 3 is, array base palte also comprises to be arranged with layer with pixel electrode 3 and to be positioned at the guarded electrode 9 above data line 5.
Being positioned at guarded electrode 9 above data line 5 can the electric field that produces of shadow data line 5, thus prevents effective deflection of this electric field influence liquid crystal molecule.When not having guarded electrode 9, the width of black matrix is at least 18-28 μm, and when having guarded electrode 9, the width of black matrix can be reduced to 6-8 μm, therefore greatly improves the aperture opening ratio of display device.
According to embodiment, public electrode can have matrix structure, and public electrode comprises multiple sub-public electrode, and each pixel cell corresponds to a sub-public electrode.Fig. 6 and Fig. 7 respectively illustrates the structural design of public electrode according to an embodiment and guarded electrode.As shown in Figure 6, the matrix of public electrode 2 is being connected by public electrode wire 4 perpendicular on the direction of data line, public electrode 2 directly contacts electrical connection with public electrode wire 4, the direction being parallel to data line is connected by connecting electrode 10, this connecting electrode 10 is arranged at different layers with public electrode 2, and connecting electrode 10 is connected by via hole 6 with adjacent sub-public electrode respectively.Particularly, connecting electrode 10 is connected with adjacent sub-public electrode with the via hole 6 in passivation layer by being produced on gate insulator.
Similarly, as shown in Figure 7, guarded electrode 9 is being interconnected by guarded electrode connecting line perpendicular on the direction of data line, and guarded electrode 9 and guarded electrode connecting line are formed by same material (such as tin indium oxide (ITO)).
In the array base palte that the disclosure proposes, guarded electrode can be connected identical public electrode wire with public electrode.Alternatively, guarded electrode can be connected different public electrode wires with public electrode, and the signal on different public electrode wire can be identical or different.When signal on different public electrode wire is different, the signal in guarded electrode and public electrode can be made slightly different by adding small-signal input.
According to embodiment, guarded electrode and public electrode can electrically insulated from one another, and connect different public electrode wires, and now public electrode is by the impact of the stray capacitance between guarded electrode and data line.
According to an embodiment, owing to usually adopting the ITO with larger resistivity to make pixel electrode, therefore for preventing signal in pixel electrode from producing bad due to the large resistance of ITO, array base palte can also comprise the pixel metal electrode corresponding with pixel electrode, insulation course can be there is between pixel electrode and pixel metal electrode, and pixel electrode and pixel metal electrode are interconnected by the via hole in insulation course.
As shown in Figure 3 and Figure 5, pixel electrode 3 is gap electrode, and public electrode 2 is plate electrode.Thus, the electric field produced at gap electrode edge and the electric field produced between gap electrode layer and plate electrode layer can form multi-dimensional electric field, to make between the gap electrode in liquid crystal cell and all aligned liquid-crystal molecules directly over electrode can both produce rotation, thus improve liquid crystal work efficiency and increase light transmission efficiency.
In the array base palte that the disclosure proposes, pixel electrode and guarded electrode are arranged with layer, and the two is connected to different signal wires.For proving to there is not crosstalk between pixel electrode and the signal of guarded electrode, thus can not cause light leak and colour mixture, the array base palte shown in Fig. 5 is simulated.Analog result as shown in Figure 8.Fig. 8 is the longitudinal cross-section view of pixel map.As seen from Figure 8, when lighting the part on the left of square frame, in Blocked portion, there is not the phenomenon of colour mixture and light leak, therefore pixel electrode and guarded electrode being arranged the crosstalk that can not cause between signal with layer, can not cause light leak and colour mixture yet.
The disclosure additionally provides a kind of display device comprising array base palte as described above.By the location swap by pixel electrode and public electrode, pixel electrode and public electrode wire are no longer arranged with layer, arrange interval to ensure not have the needs of crosstalk therebetween because this eliminating between pixel electrode and public electrode wire.The elimination at described interval improves the work efficiency of liquid crystal, and then improves the transmitance of pixel.
The display device that the disclosure provides can be the liquid crystal indicator of any pattern such as TN, ADS, IPS, LTPS.This display device can be any product or its assemblies with Presentation Function such as liquid crystal panel, LCD TV, display, mobile phone, navigating instrument.
Fig. 9 illustrates the process flow diagram of the method according to the making of embodiment of the present disclosure array base palte as described above.Particularly, said method comprising the steps of:
At S100 place, underlay substrate forms the figure of grid, public electrode and the public electrode wire comprising thin film transistor (TFT); At S102 place, form gate insulator; At S104 place, form the active layer of thin film transistor (TFT); At S106 place, form the figure comprising the source electrode of thin film transistor (TFT), drain electrode and data line; At S108 place, form passivation layer, wherein the source electrode of thin film transistor (TFT) and drain electrode are arranged between passivation layer and gate insulator; And at S110 place, form pixel electrode over the passivation layer.
Particularly, step S100 can comprise and first on underlay substrate, forms metal level, carries out patterning to described metal level, thus forms the figure comprising grid, public electrode and public electrode wire.Underlay substrate is transparency carrier, such as glass substrate, quartz base plate and organic resin substrate etc.Can adopt method depositing metal layers on underlay substrate of sputtering or thermal evaporation, wherein gate metal layer can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, the alloy of the metals such as Ta, W and these metals, and metal level can be single layer structure or such as Cu Mo, Ti Cu Ti, Mo Al the sandwich construction of Mo etc. and so on.The method of patterning comprises photoetching, wet etching and dry etching etc.Public electrode also can be made by depositing indium-tin-oxide (ITO) material.
In step s 102, the material of gate insulator can be selected from oxide, nitride or oxides of nitrogen, and can be individual layer, bilayer or sandwich construction.Particularly, the material of gate insulator can be SiNx, SiOx or Si (ON) x.
Step S104 can specifically comprise formation semiconductor layer, carries out patterning to described semiconductor layer, to form the active layer pattern of thin film transistor (TFT).The material of active layer can be silicon semiconductor or metal-oxide semiconductor (MOS).
Step S106 can specifically comprise, and the underlay substrate of completing steps S104 forms metal level, carries out patterning to described metal level, thus forms the figure comprising the source electrode of thin film transistor (TFT), drain electrode and data line.
In step S108, the material of passivation layer can be selected from oxide, nitride or oxides of nitrogen, and can be individual layer, bilayer or sandwich construction.Such as, the material of passivation layer can be SiNx, SiOx or Si (ON) x.
In step s 110, pixel electrode can be made by depositing indium-tin-oxide (ITO) material.
According to embodiment of the present disclosure, said method can also comprise and forms guarded electrode over the passivation layer, and wherein guarded electrode is positioned at above data line.Guarded electrode can the electric field that produces of shadow data line, thus prevents effective deflection of this electric field influence liquid crystal molecule.
Although illustrate in detail in accompanying drawing and aforementioned description and describe the disclosure, such diagram and description will be regarded as illustrative or exemplary and nonrestrictive; The disclosure is not limited to the disclosed embodiments.Those skilled in the art, when putting into practice invention required for protection, by research accompanying drawing, disclosure and claim of enclosing, can understand and realize other modification to the disclosed embodiments.Such as, method described above does not require to realize closing the result expected with the order of described certain order or order.Other step can be provided, or can from described method removing step, and other assembly can add described device to or remove from described device.Other embodiment can in the scope of the present disclosure.
Claims (10)
1. an array base palte, comprise many grid lines, the a plurality of data lines of intersecting with many grid lines, and intersect by many grid lines and a plurality of data lines the multiple pixel cells defined, each pixel cell comprises thin film transistor (TFT), gate insulator, be arranged in the passivation layer on gate insulator side, pixel electrode and public electrode, wherein the source electrode of thin film transistor (TFT) and drain electrode are arranged between passivation layer and gate insulator, public electrode is arranged on the opposite side of the gate insulator relative with passivation layer, pixel electrode is arranged over the passivation layer, wherein said array base palte also comprises to be arranged with layer with pixel electrode and to be positioned at the guarded electrode above data line.
2. array base palte as claimed in claim 1, wherein public electrode has matrix structure, and described public electrode comprises multiple sub-public electrode, and each pixel cell corresponds to a sub-public electrode.
3. array base palte as claimed in claim 2, wherein the matrix structure of public electrode is being connected by public electrode wire perpendicular on the direction of data line, and public electrode directly contacts electrical connection with public electrode wire.
4. array base palte as claimed in claim 3, wherein the matrix structure of public electrode is connected by connecting electrode on the direction being parallel to data line, described connecting electrode and described public electrode are arranged at different layers, and described connecting electrode is connected by via hole with adjacent sub-public electrode respectively.
5. array base palte as claimed in claim 1, wherein guarded electrode is perpendicular on the direction of data line, is interconnected by guarded electrode connecting line, and wherein guarded electrode and guarded electrode connecting line are formed by same material.
6. array base palte as claimed in claim 1, wherein guarded electrode is connected identical public electrode wire with public electrode.
7. array base palte, wherein guarded electrode and public electrode electrically insulated from one another as claimed in claim 1, and connect different public electrode wires.
8. array base palte as claimed in claim 1, wherein array base palte also comprises the pixel metal electrode corresponding with pixel electrode, between pixel electrode and pixel metal electrode, there is insulation course, and pixel electrode and pixel metal electrode are interconnected by the via hole in insulation course.
9. array base palte as claimed in claim 1, wherein pixel electrode is gap electrode, and public electrode is plate electrode.
10. a display device, comprises array base palte as claimed in any one of claims 1-9 wherein.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520756091.1U CN204964957U (en) | 2015-09-28 | 2015-09-28 | Array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520756091.1U CN204964957U (en) | 2015-09-28 | 2015-09-28 | Array substrate and display device |
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| CN204964957U true CN204964957U (en) | 2016-01-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185791A (en) * | 2015-09-28 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185791A (en) * | 2015-09-28 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| WO2017054394A1 (en) * | 2015-09-28 | 2017-04-06 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device |
| US10325933B2 (en) | 2015-09-28 | 2019-06-18 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display device |
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Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Address before: Beijing economic and Technological Development Zone 100176 Beijing Zelu 9 Patentee before: BOE TECHNOLOGY GROUP Co.,Ltd. |
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Granted publication date: 20160113 Termination date: 20210928 |
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