Nothing Special   »   [go: up one dir, main page]

CN204517770U - Multi-mode configurable filter - Google Patents

Multi-mode configurable filter Download PDF

Info

Publication number
CN204517770U
CN204517770U CN201520173441.1U CN201520173441U CN204517770U CN 204517770 U CN204517770 U CN 204517770U CN 201520173441 U CN201520173441 U CN 201520173441U CN 204517770 U CN204517770 U CN 204517770U
Authority
CN
China
Prior art keywords
filter
mode
memory register
center
hysteresis comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201520173441.1U
Other languages
Chinese (zh)
Inventor
胡兴志
王纪坤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
North China Institute of Science and Technology
Original Assignee
North China Institute of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by North China Institute of Science and Technology filed Critical North China Institute of Science and Technology
Priority to CN201520173441.1U priority Critical patent/CN204517770U/en
Application granted granted Critical
Publication of CN204517770U publication Critical patent/CN204517770U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

The utility model discloses a kind of multi-mode configurable filter, it is made up of analog center, digital control center and reference voltage current source, analog center leads to multiplex filter, hysteresis comparator, input stage and output stage by lower passband and forms, and digital control center is made up of SPI, clock module, logic control element, sampling clock selected cell, counter and memory register.A kind of multi-mode configurable filter that the utility model provides, digital control center is adopted to be configured filter mode, filter can be made to be operated in the logical and adaptive model of bypass mode, low pass, band, hysteresis comparator and memory register is adopted to improve antijamming capability, functional.

Description

Multi-mode configurable filter
Technical field
The utility model relates to a kind of filter, especially a kind of multi-mode configurable filter.
Background technology
Filter is one of most important module in analog circuit, and the application in telecommunication apparatus and all kinds of control system is very extensive.The quality of a product, often depends on this product circuit median filter performance.
At present, integrated circuit filter mainly uses continuous time filter and switching capacity filter these two kinds.Wherein, continuous time, analog filter can be applied to higher frequency, and its transfer function coefficient is decided by mutual conductance and capacitance, precision and the linearity bad, zero pole point controls complicated, large by technogenic influence; And switching capacity filter transfer function depends on capacity ratio, have nothing to do with technological parameter, transfer function precision is high, and realizes large resistance by smaller capacitive, saves area, is beneficial to integrated, meets the design directions such as high integration, high accuracy, low-power consumption.Configurable multi-mode filter, relative to general filter, having can by controlling to make same circuit working in low pass, the advantage being with different modes such as leading to.
Existing configurable multi-mode filter, can only lead to work at simple low pass, band by configuration effort, its mode of operation is very single.
Utility model content
For the deficiencies in the prior art, the purpose of this utility model is to provide a kind of multi-mode configurable filter, solves existing configurable multi-mode filter, can only configuration effort in the deficiency of the single mode of operation such as simple low pass, band are logical.
In order to achieve the above object, the utility model is by the following technical solutions:
A kind of multi-mode configurable filter, described configurable multi-mode filter is made up of analog center, digital control center and reference voltage current source, described analog center leads to multiplex filter, hysteresis comparator, input stage and output stage by lower passband and forms, and described lower passband leads to multiplex filter and is connected with hysteresis comparator, input stage and output stage; Described digital control center is made up of SPI, clock module, logic control element, sampling clock selected cell, counter and memory register, described logic control element is connected with SPI, sampling clock selected cell and memory register, described sampling clock selected cell and logic control element all lead to multiplex filter with lower passband in the heart in analog and are connected, described clock module is connected with counter and memory register, and described counter is connected with hysteresis comparator in the heart in memory register and analog.
Preferably, described lower passband leads to multiplex filter is by the quadravalence Butterworth filter of two low reactance-resistance ratio second order switched-capacitor circuits cascade.
Preferably, be provided with positive and negative two feedback networks in described hysteresis comparator, when positive feedback coefficient is greater than degeneration factor, hysteresis voltage just produces.
Preferably, described input stage adopts two sampling structure design, for erase amplifier offset influence and reduction 1/f noise.
Preferably, described output stage is an AB class operational amplifier, and its quiescent current is insensitive to technique change.
Preferably, be provided with a sluggish comparison value in described memory register, when counter results variation is less than this value, judgement is caused by ambient noise, keeps configuration multi-mode filter operating state constant; When count results variation is greater than sluggish comparison value, judges that change is changed by input signal fundamental frequency and cause, configuration multi-mode filter is followed change input signal fundamental frequency adaptively and is changed operating state.
The configurable multi-mode filter of the utility model has two kinds of mode of operations and fixed mode and adaptive model, and it is configured by SPI:
(1) when being operated in fixed mode, the one of the band pass filter that configurable multi-mode filter can be configured to bypass operating mode, low pass filter, the band pass filter of Q=2 and Q=4 totally four kinds of patterns, the bandwidth of filter or centre frequency can be configured to 8kHz by SPI as required, 10kHz, 12.A kind of frequency of 5kHz, 16kHz, 20kHz, 25kHz, 32kHz and 40kHz.Input signal V inbe input to multi-mode filter by input stage, process is direct afterwards exports V by output stage out.
(2) when being operated in adaptive model, suitable low pass or band pass filter can be selected to process input signal according to the frequency of input signal, now, input signal V inby input stage to multi-mode filter, output signal V outexported by output stage, the live feedback loop be simultaneously made up of hysteresis comparator, counter, memory register feeds back to logic control element, low pass or band is selected to lead to, follow cut-off frequency or the band pass filter centre frequency of input signal pitch variation self adaptation low pass, come low-frequency noise and the high-frequency noise of filtered signal.
The beneficial effects of the utility model are:
Adopt digital control center to be configured filter mode, filter can be made to be operated in the logical and adaptive model of bypass mode, low pass, band, adopt hysteresis comparator and memory register to improve antijamming capability, functional.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of configurable multi-mode filter of the present utility model;
Fig. 2 is the circuit diagram that lower passband of the present utility model leads to multiplex filter;
Fig. 3 is the circuit diagram of hysteresis comparator of the present utility model;
Fig. 4 is the circuit diagram of input stage of the present utility model;
Fig. 5 is the circuit diagram of output stage of the present utility model.
Number in the figure is: 1-analog center, and 11-lower passband leads to multiplex filter, 12-hysteresis comparator, 13-input stage, 14-output stage, the digital control center of 2-, 21-SPI, 22-clock module, 23-logic control element, 24-sampling clock selected cell, 25-counter, 26-memory register, 3-reference voltage current source.
Embodiment
Below by embodiment, the utility model will be further described by reference to the accompanying drawings.
A kind of multi-mode configurable filter, as shown in Figure 1, described configurable multi-mode filter is made up of analog center 1, digital control center 2 and reference voltage current source 3, described analog center 1 leads to multiplex filter 11, hysteresis comparator 12, input stage 13 and output stage 14 by lower passband and forms, and described lower passband leads to multiplex filter 11 and is connected with hysteresis comparator 12, input stage 13 and output stage 14, described digital control center 2 is by SPI 21, clock module 22, logic control element 23, sampling clock selected cell 24, counter 25 and memory register 26 are formed, described logic control element 23 is connected with SPI 21, sampling clock selected cell 24 and memory register 26, described sampling clock selected cell 24 and logic control element 23 all lead to multiplex filter 11 with the lower passband in analog center 1 and are connected, described clock module 22 is connected with counter 25 and memory register 26, described counter 25 is connected with the hysteresis comparator 12 in memory register 26 and analog center 2.
It is by the quadravalence Butterworth filter of two low reactance-resistance ratio second order switched-capacitor circuits cascade that described lower passband leads to multiplex filter 11, as shown in Figure 2.Switch P 0 in figure, P1 and P2 control to select sampling capacitance and feedback capacity, realize electric capacity multiplexing, make filter be operated in three kinds of different filter patterns: the band of low pass, Q=2 leads to and the band of Q=4 leads to.Amplifier in filter is the telescopic fully-differential amplifier based on switched-capacitor CMFB, provides the high open-loop gain needed for filter and high input resistance.Simultaneously by increasing the input of amplifier to the offset voltage of the technology reduction amplifiers such as pipe area.
Be provided with positive and negative two feedback networks in described hysteresis comparator 12, as shown in Figure 3, when positive feedback coefficient is greater than degeneration factor, hysteresis voltage just produces.In figure, M6 and M7 structure is identical, has the series electric circuit negative feedback that two feedback network: M5 introduce; The voltage parallel positive feedback that M6, M7 produce.Only have as β 6/ β 3>1, hysteresis voltage just produces and can adjust with the size of signal noise by hysteresis voltage, improves antijamming capability.
Described input stage 13 adopts two sampling structure design, as shown in Figure 4, for erase amplifier offset influence and reduction 1/f noise.Input stage realizes two functions: single ended signal is converted to differential signal; Regulate common-mode voltage, adapt to low pass filter common mode input scope.Output signal is only relevant with input signal, has nothing to do with offset voltage of amplifier, because this eliminating the impact of imbalance on amplifier performance.
Described output stage 14 is AB class operational amplifiers, and as shown in Figure 5, M0 ~ M4 forms first order differential input stage; M5 ~ M10 forms second level in-phase amplifier, and wherein the M11 (M13) that is connected using grid leak end of the inverting amplifier that forms of M7 (M9) is as load, forms second level in-phase amplifier with prime M6 together with M5; M11 ~ M14 forms AB class output stage.The M11 (M13) be connected due to grid leak end can regard diode load as, less equivalent resistance reduces the gain of second level in-phase amplifier, the voltage that A (B) puts is less with the change of technique, and therefore its quiescent current is insensitive to technique change.
Be provided with a sluggish comparison value in described memory register 26, when counter results variation is less than this value, judgement is caused by ambient noise, keeps configuration multi-mode filter operating state constant; When count results variation is greater than sluggish comparison value, judges that change is changed by input signal fundamental frequency and cause, configuration multi-mode filter is followed change input signal fundamental frequency adaptively and is changed operating state.

Claims (5)

1. a multi-mode configurable filter, it is characterized in that: described configurable multi-mode filter is made up of analog center (1), digital control center (2) and reference voltage current source (3), described analog center (1) is led to multiplex filter (11), hysteresis comparator (12), input stage (13) and output stage (14) by lower passband and is formed, and described lower passband leads to multiplex filter (11) and is connected with hysteresis comparator (12), input stage (13) and output stage (14), described digital control center (2) is by SPI (21), clock module (22), logic control element (23), sampling clock selected cell (24), counter (25) and memory register (26) are formed, described logic control element (23) is connected with SPI (21), sampling clock selected cell (24) and memory register (26), described sampling clock selected cell (24) and logic control element (23) all lead to multiplex filter (11) with the lower passband in analog center (1) and are connected, described clock module (22) is connected with counter (25) and memory register (26), described counter (25) is connected with the hysteresis comparator (12) in memory register (26) and analog center (1).
2. multi-mode configurable filter according to claim 1, is characterized in that: it is by the quadravalence Butterworth filter of two low reactance-resistance ratio second order switched-capacitor circuits cascade that described lower passband leads to multiplex filter (11).
3. multi-mode configurable filter according to claim 1, is characterized in that: be provided with positive and negative two feedback networks in described hysteresis comparator (12), when positive feedback coefficient is greater than degeneration factor, hysteresis voltage just produces.
4. multi-mode configurable filter according to claim 1, is characterized in that: described input stage (13) adopts two sampling structure design, for erase amplifier offset influence and reduction 1/f noise.
5. multi-mode configurable filter according to claim 1, it is characterized in that: in described memory register (26), be provided with a sluggish comparison value, when counter results variation is less than this value, judgement is caused by ambient noise, keeps configuration multi-mode filter operating state constant; When count results variation is greater than sluggish comparison value, judges that change is changed by input signal fundamental frequency and cause, configuration multi-mode filter is followed change input signal fundamental frequency adaptively and is changed operating state.
CN201520173441.1U 2015-03-26 2015-03-26 Multi-mode configurable filter Expired - Fee Related CN204517770U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520173441.1U CN204517770U (en) 2015-03-26 2015-03-26 Multi-mode configurable filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520173441.1U CN204517770U (en) 2015-03-26 2015-03-26 Multi-mode configurable filter

Publications (1)

Publication Number Publication Date
CN204517770U true CN204517770U (en) 2015-07-29

Family

ID=53715698

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520173441.1U Expired - Fee Related CN204517770U (en) 2015-03-26 2015-03-26 Multi-mode configurable filter

Country Status (1)

Country Link
CN (1) CN204517770U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106374880A (en) * 2016-08-31 2017-02-01 安徽赛福电子有限公司 Self-adaptive bandwidth filter based on switch capacitor
CN106452387A (en) * 2016-08-31 2017-02-22 安徽赛福电子有限公司 Configurable multi-mode filter based on switched capacitor
CN109885154A (en) * 2019-02-28 2019-06-14 西安理工大学 A kind of low-power consumption register with bypass channel

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106374880A (en) * 2016-08-31 2017-02-01 安徽赛福电子有限公司 Self-adaptive bandwidth filter based on switch capacitor
CN106452387A (en) * 2016-08-31 2017-02-22 安徽赛福电子有限公司 Configurable multi-mode filter based on switched capacitor
CN109885154A (en) * 2019-02-28 2019-06-14 西安理工大学 A kind of low-power consumption register with bypass channel

Similar Documents

Publication Publication Date Title
CN103051298A (en) Programmable Gain Amplifier Circuit and Programmable Gain Amplifier
CN102201792A (en) Automatic gain control circuit of audio power amplifier
CN204517770U (en) Multi-mode configurable filter
CN104375551B (en) Band gap voltage generative circuit
CN106385240A (en) Radio frequency front end circuit with continuously adjustable gain
CN107134984A (en) Offset voltage eliminates circuit
CN104935342B (en) A kind of dynamic over-sampling A/D converter and its design method
CN108540102B (en) Programmable gain amplifier
CN103051299A (en) Programmable gain amplifier applied to transmitting end of communication system
CN103457553A (en) Gain and slew rate enhancement type amplifier
CN111030645A (en) Digital control wide-range clock duty ratio adjusting system
CN105743454A (en) Binary weighted linear-in-dB switch resistor type CMOS programmable gain amplifier
CN201674469U (en) Audio-frequency power amplifier circuit with automatic gain control circuit
CN103107791B (en) Gain linear variable gain amplifier with constant bandwidth
CN202488406U (en) Highly stable programmable gain amplifier structure
CN103944571A (en) High-speed configurable assembly line analog-to-digital converter
CN106452387A (en) Configurable multi-mode filter based on switched capacitor
CN103944570A (en) Programmable gain digital-analog unit and analog-to-digital converter
CN104135243B (en) A kind of programmable gain amplifier
CN204314764U (en) Band gap voltage generative circuit
CN106559058A (en) A kind of complex filter and its automatic frequency tuning circuit
CN206790445U (en) Offset voltage eliminates circuit
CN103107789A (en) Variable gain amplifier shared by common mode feedback resistors
CN104682946B (en) Differential signal-to-single-ended signal conversion circuit
CN103338028B (en) Triple oscillatory feedback Weak Signal Processing circuit

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150729

Termination date: 20160326

CF01 Termination of patent right due to non-payment of annual fee