CN204376711U

CN204376711U - Step-up and step-down switch power converter, control circuit and mode switching control unit

Info

Publication number: CN204376711U
Application number: CN201420832949.3U
Authority: CN
Inventors: 张健
Original assignee: Chengdu Monolithic Power Systems Co Ltd
Current assignee: Chengdu Monolithic Power Systems Co Ltd
Priority date: 2014-12-24
Filing date: 2014-12-24
Publication date: 2015-06-03
Anticipated expiration: 2024-12-24

Abstract

A step-up and step-down switching power converter, a mode switching control unit suitable for the step-up and step-down switching power converter and a related control circuit are provided. The mode switching control unit according to embodiments of the present disclosure includes a step-down duty detection and comparison circuit and a step-up duty detection and comparison circuit. The buck duty cycle detection and comparison circuit is used for comparing a signal representing a buck duty cycle with a signal representing a buck duty cycle threshold to provide a first mode switching control signal, so that the boost and buck switching power converter is controlled to automatically and smoothly switch between a buck mode switching mode and a boost-buck mode. The boost duty cycle detection and comparison circuit is used for comparing a signal representing the boost duty cycle with a signal representing a boost duty cycle threshold value to provide a second mode switching control signal so as to control the boost buck-boost switching power converter to automatically and smoothly switch between the boost mode and the boost-buck mode.

Description

Voltage raising and reducing switching power converter, control circuit and pattern switch control unit

Technical field

Embodiment of the present disclosure relates to power inverter, particularly relates to voltage raising and reducing type switching power converter and pattern control switching circuit thereof.

Background technology

Voltage raising and reducing type switching power converter input voltage can be converted to higher than, be equal to or less than the output voltage of this input voltage, can be operated in wider change range of input voltage.Therefore be widely applied in field of power supplies.

Fig. 1 shows the topological structure 10 of the power switch in a kind of common voltage raising and reducing type switching power converter.The topological structure 10 of this power switch comprises four power switchs SWA, SWB, SWC and SWD.First power switch SWA and the second power switch SWB coupled in series are between input IN and reference ground GND, and the public of the first power switch SWA and the second power switch SWB couples end formation first switching node SW1.3rd power switch SWC and the 4th power switch SWD coupled in series are between output OUT and reference ground GND, and the public end that couples of the 3rd power switch SWC and the 4th power switch SWD forms second switch node SW2.Inductance L is coupled between first switching node SW1 and second switch node SW2.Voltage raising and reducing type switching power converter also comprises control circuit usually; for providing control signal for control end GA, GB, GC and the GD of power switch SWA, SWB, SWC and the SWD in topological structure 10; switch to control each switch turn-on and turn-off separately, thus input voltage vin is converted to suitable output voltage Vo.

For the voltage raising and reducing type switching power converter adopting topological structure 10 shown in Fig. 1, if input voltage vin is higher than output voltage Vo, then this voltage raising and reducing type switching power converter works in decompression mode, if input voltage vin is close or equal output voltage Vo, then this voltage raising and reducing type switching power converter works in voltage boosting-reducing pattern, if input voltage vin is lower than output voltage Vo, then this voltage raising and reducing type switching power converter works in boost mode.At decompression mode, 4th power switch SWD continues to keep conducting, the 3rd power switch SWC continues to keep turning off, first power switch SWA and the second power switch SWB carries out complementally turn-on and turn-off and switches, that is: during the first power switch SWA conducting, second power switch SWB turns off, and vice versa.At boost mode, first power switch SWA continues to keep conducting, the second power switch SWB continues to keep turning off, 3rd power switch SWC and the 4th power switch SWD carries out complementally turn-on and turn-off and switches, that is: during the 3rd power switch SWC conducting, 4th power switch SWD turns off, and vice versa.In voltage boosting-reducing pattern, first power switch SWA and the second power switch SWB forms first group of Switch Controller, 3rd power switch SWC and the 4th power switch SWD forms second group of Switch Controller, and this first group of Switch Controller and second group of Switch Controller carry out turn-on and turn-off switching independently of each other.

In theory, based on the relative size of input voltage vin and output voltage Vo, voltage raising and reducing type switching power converter can be regulated optionally to work in decompression mode, boost mode or voltage boosting-reducing pattern, thus reach object input voltage vin being converted to any suitable output voltage Vo.But, in fact existing adjusting and voltage-reduction switch power inverter can not realize the steady switching between above three kinds of mode of operations, and output voltage Vo can be caused to occur larger fluctuation spike when switching to another kind of mode of operation (such as voltage boosting-reducing pattern) from a kind of mode of operation (such as decompression mode).

Utility model content

For one or more problem of the prior art, embodiment of the present disclosure provides a kind of voltage raising and reducing type switching power converter, for the pattern switch control unit of voltage raising and reducing type switching power converter and control circuit.

In one of the present disclosure, proposing a kind of pattern switch control unit, automatically steadily switching between decompression mode and voltage boosting-reducing pattern and between voltage boosting-reducing pattern and boost mode for controlling voltage raising and reducing type switching power converter.This voltage raising and reducing type switching power converter can comprise the first power switch to the second power switch pair, and the first power switch of the first power switch centering and the second power switch coupled in series are in the input of this voltage raising and reducing type switching power converter with reference between ground, the ratio that the ON time of the first power switch accounts for whole first power switch and the second power switch turn-on and turn-off switching cycle is step-down duty ratio; 3rd power switch of the second power switch centering and the 4th power switch coupled in series are in the output of this voltage raising and reducing type switching power converter with reference between ground, and the ON time of the 3rd power switch accounts for the ratio of the turn-on and turn-off switching cycle of whole 3rd power switch and the 4th power switch for boosting duty ratio.

This pattern switch control unit can comprise: step-down duty ratio detects and detects and comparison circuit with comparison circuit and duty ratio of boosting.According to each embodiment of the present disclosure, the detection of this step-down duty ratio has the first detection input and first with comparison circuit and compares output, this the first detection input is for receiving the signal characterizing step-down duty ratio, this step-down duty ratio detects with comparison circuit for generation of the signal characterizing step-down duty cycle threshold, and providing first mode switch-over control signal to compare output described first by the signal characterizing this step-down duty ratio compared with characterizing the signal of step-down duty cycle threshold, wherein said step-down duty cycle threshold has the first sluggishness; If step-down duty ratio is greater than step-down duty cycle threshold, then first mode switch-over control signal controls described voltage raising and reducing type switching power converter and switches to voltage boosting-reducing pattern from decompression mode, make described step-down duty cycle threshold be reduced to the second step-down duty cycle threshold, the amount of reduction equals described first sluggishness simultaneously; If step-down duty ratio is less than described second step-down duty cycle threshold, then first mode switch-over control signal controls described voltage raising and reducing type switching power converter and switches to decompression mode from voltage boosting-reducing pattern, makes step-down duty cycle threshold recover initial value simultaneously.

According to each embodiment of the present disclosure, the detection of this boosting duty ratio has the second detection input and second with comparison circuit and compares output, this the second detection input is for receiving the signal characterizing boosting duty ratio, this boosting duty ratio detects with comparison circuit for generation of the signal characterizing duty cycle threshold of boosting, and providing second pattern switch-over control signal to compare output described second by the signal characterizing this boosting duty ratio compared with characterizing the signal of duty cycle threshold of boosting, wherein said boosting duty cycle threshold has the second sluggishness; If boosting duty ratio is greater than boosting duty cycle threshold, then the second pattern switch-over control signal controls described voltage raising and reducing type switching power converter and switches to boost mode from voltage boosting-reducing pattern, make described boosting duty cycle threshold be reduced to the second boosting duty cycle threshold, and the amount reduced equal described second sluggishness simultaneously; If boosting duty ratio is less than described second boosting duty cycle threshold, then the second pattern switch-over control signal controls described voltage raising and reducing type switching power converter from boost mode switching rise pressure-decompression mode, makes boosting duty cycle threshold recover initial value simultaneously.

In another aspect of the present disclosure, propose a kind of control circuit, for providing control signal for above-mentioned voltage raising and reducing type switching power converter.This control circuit comprises the pattern switch control unit according to each embodiment of the disclosure.This control circuit can also receiving system clock signal, characterize the output voltage of described voltage raising and reducing type switching power converter the first feedback signal, characterize the second feedback signal flowing through the switching current of described switch element and the reference signal of desired value characterizing described output voltage.This control circuit is fabricated with based on described first feedback signal, second feedback signal, reference signal and clock signal of system provide the first control signal, second control signal, 3rd control signal and the 4th control signal are respectively to described first power switch, second power switch, 3rd power switch and the 4th power switch, wherein said first control signal and described second control signal logic state complementation, the turn-on and turn-off being respectively used to control described first power switch and the second power switch switch, described 3rd control signal and described 4th control signal logic state complementation, the turn-on and turn-off being respectively used to control described 3rd power switch and described 4th power switch switch.

Of the present disclosure another in, propose a kind of voltage raising and reducing type switching power converter, comprise the pattern switch control unit according to each embodiment of the disclosure.

In one side more of the present disclosure, propose a kind of voltage raising and reducing type switching power converter, comprise the control circuit according to each embodiment of the disclosure.

Voltage raising and reducing type switching power converter according to disclosure embodiment can steadily switch automatically between decompression mode and voltage boosting-reducing pattern and between voltage boosting-reducing pattern and boost mode.At decompression mode, this control circuit makes this voltage raising and reducing type switching power converter carry out the work of depressure cycle continuously and stably, depressure cycle refers to that the first power switch in first group of Switch Controller and the second power switch carry out complementally turn-on and turn-off and switch, the 3rd power switch in second group of Switch Controller continues to keep turning off, and the 4th power switch continues to keep conducting.At boost mode, this control circuit makes this voltage raising and reducing type switching power converter carry out the work of boosting period continuously and stably, boosting period refers to that the 3rd power switch in second group of switch and the 4th power switch carry out complementally turn-on and turn-off and switch, and the first power switch in first group of Switch Controller continues to keep conducting, the second power switch continues to keep turning off.In voltage boosting-reducing pattern, the work that this control circuit makes this voltage raising and reducing type switching power converter carry out a depressure cycle and a boosting period continuously and stably to replace.

Utilize such scheme, be that voltage raising and reducing type switching power converter supplies a pattern switch-over control signal according to the pattern switch control unit of disclosure embodiment, to control this voltage raising and reducing type switching power converter automatically between decompression mode and voltage boosting-reducing pattern, and steadily switch between voltage boosting-reducing pattern and boost mode, avoid the critical zone switched in pattern, switching back and forth unnecessary between decompression mode and voltage boosting-reducing pattern and between voltage boosting-reducing pattern and boost mode, the fluctuation spike of output voltage when reduction pattern switches, strengthen the stability of voltage raising and reducing type switching power converter

Accompanying drawing explanation

Accompanying drawing below contributes to understanding better next to the description of the different embodiment of the disclosure.These accompanying drawings not according to the feature of reality, size and scale, but schematically show the principal character of some execution modes of the disclosure.These drawings and embodiments provide embodiments more of the present disclosure in mode that is non-limiting, nonexhaustive.For simplicity's sake, same or similar assembly or the structure in different accompanying drawing with identical function adopt identical Reference numeral.

Fig. 1 shows the topological structure 10 of the power switch in a kind of common voltage raising and reducing type switching power converter;

Fig. 2 shows the circuit framework schematic diagram of voltage raising and reducing type switching power converter 100 according to a disclosure embodiment and control circuit 108 thereof;

Fig. 3 illustrates the waveform schematic diagram flowing through the inductive current IL of perceptual energy-storage travelling wave tube Lo when voltage raising and reducing type switching power converter 100 is changed between decompression mode and voltage boosting-reducing pattern in Fig. 2 embodiment;

Fig. 4 illustrates the waveform schematic diagram flowing through the inductive current IL of perceptual energy-storage travelling wave tube Lo when voltage raising and reducing type switching power converter 100 is changed between voltage boosting-reducing pattern and boost mode in Fig. 2 embodiment;

Fig. 5 shows the circuit diagram of the pattern switch control unit 105 according to a disclosure exemplary embodiment;

Fig. 6 shows and detects the work wave schematic diagram with comparison circuit 1051 according to the step-down duty ratio of a disclosure embodiment;

Fig. 7 shows and detects the work wave schematic diagram with comparison circuit 1052 according to the boosting duty ratio of a disclosure embodiment;

Fig. 8 illustrates the circuit diagram of current detecting according to a disclosure embodiment and slope compensation unit 106;

Fig. 9 shows the first slope compensation signal and the second slope compensation signal that in Fig. 8, current detecting and slope compensation unit 106 receive, and the waveform schematic diagram of the first current detection signal exported and the second current detection signal;

Figure 10 shows the circuit framework schematic diagram of the pattern switch control unit 105 according to a disclosure variant embodiment;

Figure 11 shows the circuit framework schematic diagram of the pattern switch control unit 105 according to another variant embodiment of the disclosure;

Figure 12 shows and detects the work wave schematic diagram with comparison circuit 1051 according to the step-down duty ratio of Figure 11 illustrated embodiment;

Figure 13 shows and detects the work wave schematic diagram with comparison circuit 1052 according to the boosting duty ratio of Figure 11 illustrated embodiment.

Embodiment

Embodiments more of the present disclosure will be described below in detail.In ensuing explanation, some concrete details, the design parameter of such as, particular circuit configurations in embodiment and these circuit elements, all for providing better understanding to embodiment of the present disclosure.Even if those skilled in the art be appreciated that when lack some details or additive method, element, material etc. in conjunction with, embodiment of the present disclosure also can be implemented.

In specification of the present disclosure, the specific features all meaning when mentioning " embodiment " to describe in this embodiment, structure or parameter, step etc. are at least included in according in an embodiment of the present disclosure.Thus, in specification of the present disclosure, be not used in refer in particular in same embodiment according to the such as term such as " according to an embodiment of the present disclosure ", " in one embodiment ", according to the such as term such as " in a further embodiment ", " according to different embodiment of the present disclosure ", " embodiment other according to the disclosure ", also and be not used in and refer in particular to the feature mentioned and can only be included in specifically different embodiments.It should be appreciated by those skilled in the art, disclosed in one or more embodiment of present disclosure specification, each specific features, structure or parameter, step etc. can combine in any suitable manner.In addition, in specification of the present disclosure and claim, " coupling " one word mean to realize directly or indirectly connecting by mode that is electric or non-electrical." one " is also not used in and refers in particular to single, but can comprise plural form." ... in " can comprise " and ... in " and " ... on " implication.Except non-specifically explicitly points out, "or" can comprise "or", " with " and " or/and " implication, and be not used in one that refers in particular to and can only select in several feature arranged side by side, but mean to select one of them or combination that is several or wherein certain several feature.Except non-specifically explicitly points out, " based on " word do not have exclusiveness, but mean except based on except the feature clearly described, the feature that clearly can also not describe based on other." circuit " means to be coupled in together to provide the structure of specific function to one or more active or passive element of major general." signal " at least can refer to the signal comprising electric current, voltage, electric charge, temperature, data, pressure or other type.If the embodiment of " transistor " can comprise " field-effect transistor " or " bipolar junction transistor ", then " grid/grid region ", " source electrode/source region ", " drain electrode/drain region " can comprise " base stage/base ", " emitter/emitter region ", " collector electrode/collector region " respectively, and vice versa.It should be appreciated by those skilled in the art, what more than enumerate is only exemplary to the explanation describing term in the disclosure, and is not used in and carries out absolute restriction to each term.

Fig. 2 shows the circuit framework schematic diagram of the voltage raising and reducing type switching power converter 100 according to a disclosure embodiment.This voltage raising and reducing type switching power converter 100 can comprise: input IN, for receiving input voltage vin, output OUT, for providing suitable output voltage Vo, thinking load supplying and providing output current Io, switch element, such as comprise the first power switch SWA, second power switch SWB, 3rd power switch SWC and the 4th power switch SWD, there is the first end for coupling described input IN, for coupling second end of described output OUT, and for reception control signal (the first control signal DR1 in such as Fig. 2, second control signal DR2, 3rd control signal DR3 and the 4th control signal DR4) control end (the first control end GA in such as Fig. 2, second control end GB, 3rd control end GC and the 4th control end GD), this switch element is configured to based on control signal (the first control signal DR1 in such as Fig. 2, second control signal DR2, 3rd control signal DR3 and the 4th control signal DR4) carry out turn-on and turn-off switching, input voltage vin to be converted to described output voltage Vo, and control circuit 108, for detecting/receiving the reference signal Vref of the first feedback signal Vfb, the second feedback signal Vcs of reflection output current Io and the desired value of sign output voltage Vo that characterize output voltage Vo.This control circuit 108 is fabricated at least providing aforementioned control signals (the first control signal DR1 in such as Fig. 2, the second control signal DR2, the 3rd control signal DR3 and the 4th control signal DR4) to switch element based on described first feedback signal Vfb, the second feedback signal Vcs and reference signal Vref.

According to an exemplary embodiment of the present disclosure, the switch element of voltage raising and reducing type switching power converter 100 can have following topological structure: the first power switch SWA and the second power switch SWB coupled in series are between input IN and reference ground GND, and the public of the first power switch SWA and the second power switch SWB couples end formation first switching node SW1; 3rd power switch SWC and the 4th power switch SWD coupled in series are between output OUT and reference ground GND, and the public end that couples of the 3rd power switch SWC and the 4th power switch SWD forms second switch node SW2.In one exemplary embodiment, perceptual energy-storage travelling wave tube Lo is coupled between the first switching node SW1 and second switch node SW2.In the exemplary embodiment of Fig. 2, first to fourth power switch SWA, SWB, SWC and SWD all can comprise controllable switch element, such as, be illustrated as MOSFET.This first to fourth power switch SWA, SWB, SWC and SWD can have respective control end respectively, such as described first control end GA, the second control end GB, the 3rd control end GC and the 4th control end GD, be respectively used to the first control signal DR1, the second control signal DR2 that reception control circuit 108 provides, the 3rd control signal DR3 and the 4th control signal DR4.

According to an exemplary embodiment of the present disclosure, the control circuit 108 of voltage raising and reducing type switching power converter 100 adopts peak value comparison method pulse-width-modulated mode to carry out turn-on and turn-off switching controls to switch element.In one embodiment, control circuit 108 at least provides the first control signal DR1, the second control signal DR2 in such as Fig. 2, the 3rd control signal DR3 and the 4th control signal DR4 respectively to the first power switch SWA in switch element, the second power switch SWB, the 3rd power switch SWC and the 4th power switch SWD, switches with the turn-on and turn-off controlling these power switchs.According to an exemplary embodiment of the present disclosure, first power switch SWA and the second power switch SWB forms first group of Switch Controller (be commonly referred to step-down switching to), and the 3rd power switch SWC and the 4th power switch SWD forms second group of Switch Controller (be commonly referred to boosted switch to).Control circuit 108 is fabricated to control this first group of Switch Controller and second group of Switch Controller carries out turn-on and turn-off switching independently of each other.Control circuit 108 can adjust this voltage raising and reducing type switching power converter 100 according to the relative size of input voltage vin and output voltage Vo and at least work in decompression mode, voltage boosting-reducing pattern and boost mode.

According to an exemplary embodiment of the present disclosure, if input voltage vin is higher than output voltage Vo, then this voltage raising and reducing type switching power converter 100 works in decompression mode.At decompression mode, control circuit 108 makes first group of Switch Controller carry out turn-on and turn-off switching, and makes the 3rd power switch SWC in second group of Switch Controller continue to keep turning off, and the 4th power switch SWD continues to keep conducting.Now, voltage boosting-reducing type switching power converter 100 in fact has voltage-dropping type topological structure.In one embodiment, at decompression mode, control circuit 108 controls the first power switch SWA in this first group of Switch Controller and the second power switch SWB to carry out complementally turn-on and turn-off and switches, that is: during the first power switch SWA conducting, second power switch SWB turns off, and vice versa.The ratio that generally ON time of the first power switch SWA can be accounted for whole first power switch SWA and the second power switch SWB turn-on and turn-off switching cycle is called step-down duty ratio, represents in the disclosure with D1.

According to an exemplary embodiment of the present disclosure, if input voltage vin declines, when being down to close to or equaling output voltage Vo, then this voltage raising and reducing type switching power converter 100 works in voltage boosting-reducing pattern.In voltage boosting-reducing pattern, control circuit 108 controls described first group of Switch Controller and second group of Switch Controller carries out turn-on and turn-off switching independently of each other, and first group of Switch Controller work switching cycle and second group of Switch Controller work switching cycle are alternately carried out, wherein first group of Switch Controller work switching cycle is called a depressure cycle, second group of Switch Controller work switching cycle is called a boosting period, and thus a voltage boosting-reducing cycle comprises a depressure cycle and a boosting period.In one embodiment, for a depressure cycle, control circuit 108 makes the 3rd power switch SWC in second group of Switch Controller continue to keep turning off, 4th power switch SWD continues to keep conducting, and makes the first power switch SWA in first group of Switch Controller and the second power switch SWB carry out complementally turn-on and turn-off switching.Thus in the handoff procedure of first group of Switch Controller, if the first power switch SWA conducting and the second power switch SWB turn off, the first power switch SWA then in fact in four power switchs and the equal conducting of the 4th power switch SWD (representing with " AD " in the disclosure), if the first power switch SWA turns off and the second power switch SWB conducting, then the second power switch SWB in fact in four power switchs and the equal conducting of the 4th power switch SWD (representing with " BD " in the disclosure).For a boosting period, control circuit 108 makes the first power switch SWA lasting maintenance conducting in first group of Switch Controller, the second power switch SWB continues to keep turning off, and makes the 3rd power switch SWC in second group of Switch Controller and the 4th power switch SWD carry out complementally turn-on and turn-off switching.Thus in the handoff procedure of second group of Switch Controller, if the 3rd power switch SWC conducting and the 4th power switch SWD turn off, the first power switch SWA then in fact in four power switchs and the equal conducting of the 3rd power switch SWC (representing with " AC " in the disclosure), if the 3rd power switch SWC turns off and the 4th power switch SWD conducting, then the first power switch SWA in fact in four power switchs and the equal conducting of the 4th power switch SWD (representing with " AD " in the disclosure).

According to an exemplary embodiment of the present disclosure, if input voltage vin is brought down below output voltage Vo, then this voltage raising and reducing type switching power converter 100 works in boost mode.At boost mode, control circuit 108 makes second group of Switch Controller carry out turn-on and turn-off switching, and makes the first power switch SWA in first group of Switch Controller continue to keep conducting, the lasting maintenance shutoff of the second power switch SWB.Now, voltage boosting-reducing type switching power converter 100 in fact has booster type topological structure.In one embodiment, at boost mode, control circuit 108 controls the 3rd power switch SWC in this second group of Switch Controller and the 4th power switch SWD to carry out complementally turn-on and turn-off and switches, that is: during the 3rd power switch SWC conducting, 4th power switch SWD turns off, and vice versa.The ratio that generally ON time of the 3rd power switch SWC can be accounted for whole 3rd power switch SWC and the 4th power switch SWD turn-on and turn-off switching cycle is called boosting duty ratio, represents in the disclosure with D2.

According to an exemplary embodiment of the present disclosure, control circuit 108 can also steadily switch by regulating power converter 100 automatically between decompression mode and voltage boosting-reducing pattern and between voltage boosting-reducing pattern and boost mode.

Control circuit 108 adjusts output voltage Vo by regulating duty ratio D1 and duty ratio D2.Under peak value comparison method pulse-width-modulated mode, the second feedback signal Vcs that control circuit 108 adopts can by detecting the switching current I flowing through the first power switch SWA _hSor obtain by detecting the inductive current IL flowing through perceptual energy-storage travelling wave tube Lo, thus the second feedback signal Vcs is proportional to switching current I _hSor inductive current IL, and contain switching current I _sor the peak information of inductive current IL.Because output current Io can regard switching current I as usually _hSor inductive current IL's is average, thus switching current I _hSor inductive current IL in fact also reflects the value of output current Io.

According to an exemplary embodiment of the present disclosure, voltage raising and reducing type switching power converter 100 can also comprise capacitive energy-storage travelling wave tube Co, its one end couples output OUT, and the other end is connected to reference to ground GND, for output (such as the first switching signal V to switch element _sW1or the second switching signal V _sW2) filtering (or can regard as output voltage Vo filtering) is with the output voltage Vo making output OUT provide level and smooth.

According to an exemplary embodiment of the present disclosure, voltage raising and reducing type switching power converter 100 can also comprise feedback circuit, for detecting output voltage Vo and providing the first feedback signal Vfb characterizing output voltage Vo.Such as, feedback circuit in Fig. 2 is illustrated as to comprise and is coupled in series in output OUT and with reference to the first feedback resistance Rf1 between ground GND and the first feedback resistance Rf2, provides the first feedback signal Vfb at the common node place of this first feedback resistance Rf1 and the first feedback resistance Rf2.In other embodiments, also can adopt other suitable feedback circuit, even also can not comprise feedback circuit, but can by direct fed-back output voltage Vo to provide the first feedback signal Vfb.

Be further described according to the voltage raising and reducing type switching power converter 100 of disclosure embodiment and control circuit 108 below with reference to Fig. 2 to Figure 13.

According to an exemplary embodiment of the present disclosure, control circuit 108 can comprise error amplifying unit 101, for the first feedback signal Vfb and reference signal Vref is carried out computing, to provide the difference amplifying signal Vcomp of the difference characterizing this first feedback signal Vfb and this reference signal Vref.

Control circuit 108 can also comprise current detecting and slope compensation unit 106, for detecting the switching current I flowing through the first power switch SWA _hSor flow through the inductive current IL of perceptual energy-storage travelling wave tube Lo to produce the second feedback signal Vcs, and this second feedback signal Vcs is carried out slope compensation, to provide the first current detection signal V _cS1with the second current detection signal V _cS2, wherein this first current detection signal V _cS1characterize inductive current IL when voltage boosting-reducing type switching power converter 100 works in decompression mode/depressure cycle, this second current detection signal characterizes inductive current IL when voltage boosting-reducing type switching power converter 100 works in boost mode/boosting period.Fig. 8 illustrates the circuit diagram of current detecting according to a disclosure embodiment and slope compensation unit 106.Current detecting unit 106 is illustrated as by detecting the electric current I flowing through the first power switch SWA in this example _hSproduce the second feedback signal V _cS.Current sense resistor RS and detecting amplifier CS can be adopted to realize this function, current sense resistor RS and the first power switch SWA coupled in series, two inputs of detecting amplifier CS couple the two ends of current sense resistor RS respectively, and its output provides described second feedback signal V _cS.It should be appreciated by those skilled in the art that the circuit realizing current detecting has multiple, in other embodiment, also can adopt other current detection circuit existing.Current detecting and slope compensation unit 106 can receive the first slope compensation signal RAMP1 and the second slope compensation signal RAMP2, for respectively to the second feedback signal V _cScompensate.As shown in Figure 9, in one embodiment, the second slope compensation signal RAMP2 can superpose by the first slope compensation signal RAMP1 the bias voltage Δ V set and obtain, and makes the peak value of the first slope compensation signal RAMP1 equal with the valley of the second slope compensation signal RAMP2.That is the peak value of the first slope compensation signal RAMP1 is just collided with the valley of the second slope compensation signal RAMP2, but the first slope compensation signal RAMP1 and the second slope compensation signal RAMP2 is not overlapping.Also can think that the bias voltage Δ V of described setting equals the amplitude of the first slope compensation signal RAMP1 in this case.It should be appreciated by those skilled in the art that Fig. 9 is only schematic for the slope of each signal and amplitude, do not represent its actual size, also non-actual ratio of pressing is drawn.Return Fig. 8, current detecting and slope compensation unit 106 obtain described first current detection signal V after adopting the first slope compensation signal RAMP1 to compensate described second feedback signal Vcs _cS1, after adopting the second slope compensation signal RAMP2 to compensate described second feedback signal Vcs, obtain described second current detection signal V simultaneously _cS2.In one embodiment, as schematically shown in Figure 8, compensate function can be realized by add circuit, namely, described first slope compensation signal RAMP1 and the second slope compensation signal RAMP2 is superimposed upon on the second feedback signal Vcs respectively, thus obtains described first current detection signal V respectively _cS1with described second current detection signal V _cS2.Thus, referring again to Fig. 9 signal, described first current detection signal V _cS1with described second current detection signal V _cS2between also there is bias voltage Δ V (that is, the second current detection signal V of described setting _cS2also can regard as by the first current detection signal V _cS1the bias voltage Δ V superposing described setting obtains).

Return and continue to illustrate with reference to figure 2, control circuit 108 can also comprise depressure cycle pwm unit 102 and boosting period pwm unit 103.Depressure cycle pwm unit 102 is for receiving described difference amplifying signal Vcomp and described first current detection signal V _cS1, and by this first current detection signal V _cS1compare to export the first pulse width modulating signal PWM1 with difference amplifying signal Vcomp.Boosting period pwm unit 103 is for receiving described difference amplifying signal Vcomp and described second current detection signal V _cS2, and by this second current detection signal V _cS2compare to export the second pulse width modulating signal PWM2 with difference amplifying signal Vcomp.

According to an exemplary embodiment of the present disclosure, control circuit 108 can also comprise logic control element 104.This logic control element 104 at least receives described first pulse width modulating signal PWM1, the second pulse width modulating signal PWM2 and clock signal clk, and at least produces described first control signal DR1, the second control signal DR2, the 3rd control signal DR3 and the 4th control signal DR4 based on this first pulse width modulating signal PWM1, the second pulse width modulating signal PWM2 and clock signal clk.This clock signal clk can be provided by such as oscillator.In one embodiment, described first control signal DR1 and the second control signal DR2 can be the square-wave signal of logical complement, and even the first control signal DR1 has logic high, then the second control signal DR2 has logic low, and vice versa.This first control signal DR1 and the second control signal DR2 is respectively used to control the first power switch SWA in described first group of Switch Controller and the second power switch SWB.Described 3rd control signal DR3 and the 4th control signal DR4 also can be the square-wave signal of logical complement, and even the 3rd control signal DR3 has logic high, then the 4th control signal DR4 has logic low, and vice versa.3rd control signal DR3 and the 4th control signal DR4 is respectively used to control the 3rd power switch SWC in described second group of Switch Controller and the 4th power switch SWD.According to an embodiment of the present disclosure, at decompression mode/depressure cycle, described first power switch SWA turns off for triggering described first control signal DR1 by described first pulse width modulating signal PWM1, and described clock signal clk is for triggering described first control signal DR1 by described first power switch SWA conducting.At boost mode/boosting period, described 3rd power switch SWC turns off for triggering described 3rd control signal DR3 by described second pulse width modulating signal PWM2, and described clock signal clk is for triggering described 3rd control signal DR3 by described 3rd power switch SWC conducting.

According to an exemplary embodiment of the present disclosure, control circuit 108 can also comprise pattern switch control unit 105.Pattern switch control unit 105 by detecting step-down duty ratio D1 and boosting duty ratio D2, and by the detected value of step-down duty ratio D1 and boosting duty ratio D2 respectively with step-down duty cycle threshold D _tH1with boosting duty cycle threshold D _tH2relatively, the mode of operation of output control voltage raising and reducing type switching power converter 100 switches based on the comparison.In an exemplary embodiment, pattern switch control unit 105 can comprise the detection of step-down duty ratio and detect and comparison circuit 1052 with comparison circuit 1051 and duty ratio of boosting.Step-down duty ratio detects with comparison circuit 1051 for detecting step-down duty ratio D1, and will characterize the signal of step-down duty ratio D1 and sign step-down duty cycle threshold D _tH1signal compare to produce first mode switch-over control signal TR1.If step-down duty ratio D1 is greater than step-down duty cycle threshold D _tH1, then first mode switch-over control signal TR1 controls voltage raising and reducing type switching power converter 100 and switches to voltage boosting-reducing pattern from decompression mode, if step-down duty ratio D1 is less than step-down duty cycle threshold D _tH1, then first mode switch-over control signal TR1 controls voltage raising and reducing type switching power converter 100 and switches to decompression mode from voltage boosting-reducing pattern.The detection of boosting duty ratio and comparison circuit 1052 are for detecting the duty ratio D2 that boosts, and duty cycle threshold D that the signal of sign boosting duty ratio D2 and sign are boosted _tH2signal compare to produce the second pattern switch-over control signal TR2.If boosting duty ratio D2 is greater than boosting duty cycle threshold D _tH2, then the second pattern switch-over control signal TR2 controls voltage raising and reducing type switching power converter 100 and switches to boost mode from voltage boosting-reducing pattern, if boosting duty ratio D2 is less than boosting duty cycle threshold D _tH2, then the second pattern switch-over control signal TR2 controls voltage raising and reducing type switching power converter 100 and switches to voltage boosting-reducing pattern from boost mode.

According to an exemplary embodiment of the present disclosure, described step-down duty cycle threshold D _tH1the first sluggish H1 can be had.In this case, if step-down duty ratio D1 is greater than step-down duty cycle threshold D _tH1, then, while first mode switch-over control signal TR1 control voltage raising and reducing type switching power converter 100 switches to voltage boosting-reducing pattern from decompression mode, this step-down duty cycle threshold D is made _tH1be reduced to the second step-down duty cycle threshold, and the amount reduced is the value of this first sluggish H1, namely the second step-down duty cycle threshold is (D _tH1-H1).If the D1 of step-down duty ratio is like this less than the second step-down duty cycle threshold (D _tH1-H1) time, first mode switch-over control signal TR1 just controls voltage raising and reducing type switching power converter 100 and switches back decompression mode from voltage boosting-reducing pattern, makes step-down duty cycle threshold D simultaneously _tH1from described second step-down duty cycle threshold (D _tH1-H1) return to initial value D _tH1, thus can to prevent between decompression mode and voltage boosting-reducing pattern unnecessary switches back and forth, strengthens the stability of voltage raising and reducing type switching power converter 100.

Fig. 3 illustrates the waveform schematic diagram flowing through the inductive current IL of perceptual energy-storage travelling wave tube Lo when changing between decompression mode and voltage boosting-reducing pattern according to the voltage raising and reducing type switching power converter 100 of a disclosure embodiment.First suite line 301 shows the waveform schematic diagram being converted to the inductive current IL before and after voltage boosting-reducing pattern from decompression mode.As shown in the figure, in buck mode, along with the decline of input voltage vin, input voltage vin will close to output voltage Vo, until step-down duty ratio D1 reaches step-down duty cycle threshold D _tH1time, if show, voltage raising and reducing type switching power converter 100 continues to operate in decompression mode and deficiency is thought the energy that load provides enough.Such as, step-down duty cycle threshold D _tH1for allowing the maximum reducing dutyfactor value reached under decompression mode, can be 95% in an exemplary embodiment, also can have other percent value in other embodiments.Once step-down duty ratio D1 reaches this step-down duty cycle threshold D _tH1, then show that voltage raising and reducing type switching power converter 100 needs to be converted to voltage boosting-reducing pattern to meet loading demand from decompression mode.Thus to be just converted to that depressure cycle of voltage boosting-reducing pattern, the first power switch SWA needs conducting complete cycle (second " AD " section see the waveform of inductive current IL in Fig. 3 first suite line 301) to think load energy supply.So at back to back boosting period, 3rd power switch SWC and the 4th power switch SWD carries out a switching over (" AC " section and the 3rd " AD " section see the waveform of inductive current IL in Fig. 3 first suite line 301), then needing to enter depressure cycle enables the second power switch SWB conducting (second " BD " section see the waveform of inductive current IL in Fig. 3 first suite line 301) to make inductive current IL homeostasis, thus meets voltage-second balance.After this, voltage raising and reducing type switching power converter 100 will stably work in voltage boosting-reducing pattern, the work of the depressure cycle that namely hockets (comprising " BD " and " AD ") and a boosting period (comprising " AC " and " AD ").

Second suite line 302 shows the waveform schematic diagram of the inductive current IL before and after from voltage boosting-reducing patten transformation to decompression mode.As shown in the figure, under voltage boosting-reducing pattern, along with the increase of input voltage vin, input voltage vin will be greater than output voltage Vo, until step-down duty ratio D1 is lower than the second step-down duty cycle threshold (D _tH1-H1) time, if show, voltage raising and reducing type switching power converter 100 continues to operate in voltage boosting-reducing pattern and will provide the energy contained for load.Such as, the second step-down duty cycle threshold (D _tH1-H1) for allowing the minimum step-down dutyfactor value reached under voltage boosting-reducing pattern, being 80% in an exemplary embodiment, also can having other percent value in other embodiments.Once step-down duty ratio D1 is less than this second step-down duty cycle threshold (D _tH1-H1), then show that voltage raising and reducing type switching power converter 100 needs to think from voltage boosting-reducing patten transformation to decompression mode the energy that load provides suitable.After patten transformation, power inverter 100 can steady operation in decompression mode, carry out the work of continuous print depressure cycle (comprising one " AD " and one " BD ").

According to an exemplary embodiment of the present disclosure, described boosting duty cycle threshold D _tH2the second sluggish H2 can be had.In this case, if boosting duty ratio D2 is greater than boosting duty cycle threshold D _tH2, then while the second pattern switch-over control signal TR2 control voltage raising and reducing type switching power converter 100 switches to boost mode from voltage boosting-reducing pattern, this boosting duty cycle threshold D _tH2be reduced to the second boosting duty cycle threshold, and the amount reduced is the value of this second sluggish H2, namely the second boosting duty cycle threshold is (D _tH2-H2).If boost like this, duty ratio D2 is less than the second boosting duty cycle threshold (D _tH2-H2) time, second pattern switch-over control signal TR2 just controls voltage raising and reducing type switching power converter 100 and switches rise pressure-decompression mode from boost mode, thus can to prevent between voltage boosting-reducing pattern and boosting-pattern unnecessary switches back and forth, strengthen the stability of voltage raising and reducing type switching power converter 100.

Fig. 4 illustrates the waveform schematic diagram flowing through the inductive current IL of perceptual energy-storage travelling wave tube Lo when changing between voltage boosting-reducing pattern and boost mode according to the voltage raising and reducing type switching power converter 100 of a disclosure embodiment.First suite line 401 shows the waveform schematic diagram of the inductive current IL before and after from voltage boosting-reducing patten transformation to boost mode.As shown in the figure, under voltage boosting-reducing pattern, along with the further decline of input voltage vin, input voltage vin will be less than output voltage Vo, until boosting duty ratio D2 reaches boosting duty cycle threshold D _tH2time, if show, voltage raising and reducing type switching power converter 100 continues to operate in voltage boosting-reducing pattern and deficiency is thought the energy that load provides enough.Such as, boost duty cycle threshold D _tH2for allowing the maximum boosting dutyfactor value reached under voltage boosting-reducing pattern, can be 30% in an exemplary embodiment, also can have other percent value in other embodiments.Once boosting duty ratio D2 reaches this boosting duty cycle threshold D _tH2, then show that voltage raising and reducing type switching power converter 100 needs from voltage boosting-reducing patten transformation to boost mode to meet loading demand.Thus after this no longer need depressure cycle (in such as Fig. 4 first suite line 401 waveform of inductive current IL " BD " section) to keep voltage-second balance, after being converted to boost mode, power inverter 100 can stablize the work carrying out continuous print boosting period (comprising one " AC " and one " AD ").

Second suite line 402 shows the waveform schematic diagram being converted to the inductive current IL before and after voltage boosting-reducing pattern from boost mode.As shown in the figure, under boost mode, along with the increase of input voltage vin, input voltage vin will close to output voltage Vo, until boosting duty ratio D2 is less than the second boosting duty cycle threshold (D _tH2-H2) time, if show, voltage raising and reducing type switching power converter 100 continues to operate in boost mode and will provide the energy contained for load.Such as, the second boosting duty cycle threshold (D _tH2-H2) for allowing the minimum boosting dutyfactor value reached under boost mode, can be 10% in an exemplary embodiment, also can have other percent value in other embodiments.Once boosting duty ratio D2 reaches this second boosting duty cycle threshold (D _tH2-H2), then show that voltage raising and reducing type switching power converter 100 needs to be converted to voltage boosting-reducing pattern from boost mode and thinks the energy that load provides suitable.Thus after being just converted to voltage boosting-reducing pattern, after power inverter 100 carries out the work an of boosting period (second " AC " section and second " AD " section see the waveform of inductive current IL in Fig. 4 second suite line 401), need to enter depressure cycle and make the second power switch SWB conducting (" BD " section see the waveform of inductive current IL in Fig. 4 second suite line 401).After this, voltage raising and reducing type switching power converter 100 will stably work in voltage boosting-reducing pattern, the work of the depressure cycle that namely hockets (comprising " BD " and " AD ") and a boosting period (comprising " AC " and " AD ").

Fig. 5 shows the circuit diagram of the pattern switch control unit 105 according to a disclosure exemplary embodiment.The detection of step-down duty ratio is illustrated as with comparison circuit 1051 and comprises the first reference wave circuit for generating 501 and the first d type flip flop 502.First reference wave circuit for generating 501 has control input end and output, wherein this control input end is for receiving described first mode switch-over control signal TR1, this the first reference wave circuit for generating 501 is for providing the first reference burst signal CR1 at its output, and the pulse duration of this first reference burst signal CR1 is adjusted based on first mode switch-over control signal TR1, the ratio making the pulse duration of this first reference burst signal CR1 account for each pulse signal cycle is greater than step-down duty cycle threshold D at step-down duty ratio D1 _tH1time equal the second step-down duty cycle threshold (D _tH1-H1), and be less than the second step-down duty cycle threshold (D at step-down duty ratio D1 _tH1-H1) time equal step-down duty cycle threshold D _tH1.First d type flip flop 502 has the first data input pin DI1, the first input end of clock C1, the first set end S1, the first reset terminal R1, the first positive output end Q1 and the first reversed-phase output Q1.First data input pin DI1 is for receiving described first control signal DR1, first input end of clock C1 is for receiving described first reference burst signal CR1, and the first set end S1 and the first reset terminal R1 equal receive logic height signal " H " normally works to make this first d type flip flop 502.

Below with reference to Fig. 6, brief description is carried out to the detection of this step-down duty ratio and comparison circuit 1051.Fig. 6 shows and detects the working waveform figure with comparison circuit 1051 according to the step-down duty ratio of a disclosure embodiment.Because the pulse duration of the first control signal DR1 can characterize step-down duty ratio D1, the pulse duration of the first reference burst signal CR1 can characterize step-down duty cycle threshold, thus the first control signal DR1 and the first reference burst signal CR1 is carried out pulse duration and compares and can realize step-down duty ratio D1 and step-down duty cycle threshold D _tH1(or the second step-down duty cycle threshold (D _tH1-H1)) comparison.With reference to figure 6, first d type flip flop 502 is clock falling edge triggering, first reference burst signal CR1 inputs the clock signal of its input end of clock as this first d type flip flop 502, thus at each trailing edge of the first reference burst signal CR1, data that its data input pin DI1 receives by the first d type flip flop 502 state of the first control signal DR1 (namely in Fig. 6 example) are delivered to the first positive output end Q1 and export and keep, until the next trailing edge of the first reference burst signal CR1 arrives.In the example of fig. 6, first control signal DR1, first reference burst signal CR1 and first mode switch-over control signal TR1 all can have the first logic state (being illustrated as high level) and the second logic state (being illustrated as low level), wherein the pulse duration of the first control signal DR1 and the first reference burst signal CR1 all refers to the width of the first logic state (i.e. high level in Fig. 6) pulse, control power inverter 100 when first mode switch-over control signal TR1 has the first logic state and switch to voltage boosting-reducing pattern from decompression mode, control power inverter 100 when first mode switch-over control signal TR1 has the second logic state and switch to decompression mode from voltage boosting-reducing pattern.

Suppose that the work at present of voltage boosting-reducing type switching power converter 100 is in decompression mode the signal of 601 cycles of clock signal of system CLK (in see the Fig. 6), then first mode switch-over control signal TR1 has the second logic state (being illustrated as low level in Fig. 6).If the pulse duration of the first control signal DR1 is greater than the pulse duration of the first reference burst signal CR1, then come interim at the trailing edge of the first reference burst signal CR1, first control signal DR1 is still in the first logic state (high level namely illustrated in Fig. 6), thus now this first logic state (being illustrated as high level in Fig. 6) of the first control signal DR1 is delivered to the first positive output end Q1 by the first d type flip flop 502, make first mode switch-over control signal TR1 by the second logic state (being illustrated as low level in Fig. 6) saltus step to the first logic state (being illustrated as high level in Fig. 6).At this moment show that step-down duty ratio D1 has exceeded step-down duty cycle threshold D _tH1, then first mode switch-over control signal TR1 controls this voltage boosting-reducing type switching power converter 100 and switches to voltage boosting-reducing pattern (signals see 602 and 603 cycles of clock signal of system CLK Fig. 6) from decompression mode.Meanwhile, the pulse duration that first reference wave circuit for generating 501 adjusts the first reference burst signal CR1 in response to first logic state of this first mode switch-over control signal TR1 reduces, and the ratio making its pulse duration account for each pulse signal cycle is reduced to and equals the second step-down duty cycle threshold (D _tH1-H1).

Suppose that the work at present of voltage boosting-reducing type switching power converter 100 is in voltage boosting-reducing pattern the signal of 602 ~ 605 cycles of clock signal of system CLK (in see the Fig. 6), then first mode switch-over control signal TR1 has the first logic state (being illustrated as high level in Fig. 6).Along with the increase of input voltage vin, at the depressure cycle of voltage boosting-reducing pattern, if the pulse duration of the first control signal DR1 is less than the pulse duration (signals see 605 cycles of clock signal of system CLK in Fig. 6) of the first reference burst signal CR1, then come interim at the trailing edge of the first reference burst signal CR1, first control signal DR1 still has the second logic state (being illustrated as low level in Fig. 6), thus now this second logic state (being illustrated as low level in Fig. 6) of this first control signal DR1 is delivered to the first positive output end Q1 by the first d type flip flop 502, make first mode switch-over control signal TR1 by the first logic state (being illustrated as high level in Fig. 6) saltus step to the second logic state (being illustrated as low level in Fig. 6).At this moment show that step-down duty ratio D1 has been less than the second step-down duty cycle threshold (D _tH1-H1), then first mode switch-over control signal TR1 controls this voltage boosting-reducing type switching power converter 100 and switches to decompression mode (signals see 606 and 607 cycles of clock signal of system CLK Fig. 6) from voltage boosting-reducing pattern.Meanwhile, the pulse duration that first reference wave circuit for generating 501 adjusts the first reference burst signal CR1 in response to second logic state of this first mode switch-over control signal TR1 increases, and the ratio making its pulse duration account for each pulse signal cycle increases to and equals step-down duty cycle threshold D _tH1.So, step-down duty ratio detects and comparison circuit 1051 just can switch between decompression mode and voltage boosting-reducing pattern by the first control signal DR1 and the first reference burst signal CR1 is compared to control power inverter 100.

The detection of boosting duty ratio is illustrated as with comparison circuit 1052 and comprises the second reference wave circuit for generating 503 and the second d type flip flop 504.Second reference wave circuit for generating 503 has control input end and output, wherein this control input end is for receiving described second pattern switch-over control signal TR2, this the second reference wave circuit for generating 503 is for providing the second reference burst signal CR2 at its output, and the pulse duration of this second reference burst signal CR2 is adjusted based on the second pattern switch-over control signal TR2, the ratio making the pulse duration of this second reference burst signal CR2 account for each pulse signal cycle is greater than boosting duty cycle threshold D at boosting duty ratio D2 _tH2time equal the second boosting duty cycle threshold (D _tH2-H2), and be less than the second boosting duty cycle threshold (D at boosting duty ratio D2 _tH2-H2) time equal boost duty cycle threshold D _tH2.Second d type flip flop 504 has the second data input pin DI2, second clock input (being also labeled as C2), the second set end S2, the second reset terminal R2, the second positive output end Q2 and the second reversed-phase output Q2.Second data input pin DI2 is for receiving described 3rd control signal DR3, second clock input C2 is for receiving described second reference burst signal CR2, and the second set end S2 and the second reset terminal R2 equal receive logic height signal " H " normally works to make this second d type flip flop 504.

Below with reference to Fig. 7, brief description is carried out to the detection of this boosting duty ratio and comparison circuit 1052.Fig. 7 shows and detects the working waveform figure with comparison circuit 1052 according to the boosting duty ratio of a disclosure embodiment.Pulse duration due to the 3rd control signal DR3 can characterize boosting duty ratio D2, the pulse duration of the second reference burst signal CR2 can characterize boosting duty cycle threshold, thus the 3rd control signal DR3 and the second reference burst signal CR2 is carried out pulse duration and compares can realize boosting duty ratio D2 and boosting duty cycle threshold D _tH2(or the second boosting duty cycle threshold (D _tH2-H2)) comparison.With reference to figure 7, second d type flip flop 504 is clock falling edge triggering, second reference burst signal CR2 inputs the clock signal of its input end of clock as this second d type flip flop 504, thus at each trailing edge of the second reference burst signal CR2, data that its data input pin DI2 receives by the second d type flip flop 504 state of the 3rd control signal DR3 (namely in Fig. 7 example) are delivered to the second positive output end Q2 and export and keep, until the next trailing edge of the second reference burst signal CR2 arrives.In the example in figure 7, 3rd control signal DR3, second reference burst signal CR2 and the second pattern switch-over control signal TR2 all can have the first logic state (being illustrated as high level) and the second logic state (being illustrated as low level), wherein the pulse duration of the 3rd control signal DR3 and the second reference burst signal CR2 all refers to the width of the first logic state (i.e. high level in Fig. 7) pulse, control power inverter 100 when the second pattern switch-over control signal TR2 has the first logic state and switch to boost mode from voltage boosting-reducing pattern, control power inverter 100 when the second pattern switch-over control signal TR2 has the second logic state and switch to voltage boosting-reducing pattern from boost mode.

Suppose that the work at present of voltage boosting-reducing type switching power converter 100 is in voltage boosting-reducing pattern the signal of 701 and 702 cycles of clock signal of system CLK (in see the Fig. 7), then the second pattern switch-over control signal TR2 has the second logic state (being illustrated as low level in Fig. 7).If the pulse duration of the 3rd control signal DR3 is greater than the pulse duration (signals see 702 cycles of clock signal of system CLK in Fig. 7) of the second reference burst signal CR2, then come interim at the trailing edge of the second reference burst signal CR2, 3rd control signal DR3 is still in the first logic state (high level namely illustrated in Fig. 7), thus now this first logic state (being illustrated as high level in Fig. 7) of the 3rd control signal DR3 is delivered to the second positive output end Q2 by the second d type flip flop 504, make the second pattern switch-over control signal TR2 by the second logic state (being illustrated as low level in Fig. 7) saltus step to the first logic state (being illustrated as high level in Fig. 7).At this moment show that boosting duty ratio D2 has exceeded boosting duty cycle threshold D _tH2, then the second pattern switch-over control signal TR2 controls this voltage boosting-reducing type switching power converter 100 and switches to boost mode (switching see 702 to 703 cycles of clock signal of system CLK Fig. 7 is illustrated) from voltage boosting-reducing pattern.Meanwhile, the pulse duration that second reference wave circuit for generating 503 adjusts the second reference burst signal CR2 in response to first logic state of this second pattern switch-over control signal TR2 reduces, and the ratio making its pulse duration account for each pulse signal cycle is reduced to and equals the second boosting duty cycle threshold (D _tH2-H2).

Suppose that the work at present of voltage boosting-reducing type switching power converter 100 is in boost mode the signal of 703 ~ 705 cycles of clock signal of system CLK (in see the Fig. 7), then the second pattern switch-over control signal TR2 has the first logic state (being illustrated as high level in Fig. 7).Along with the reduction of input voltage vin, if the pulse duration of the 3rd control signal DR3 is less than the pulse duration (signals see 705 cycles of clock signal of system CLK in Fig. 7) of the second reference burst signal CR2, then come interim at the trailing edge of the second reference burst signal CR2, 3rd control signal DR3 still has the second logic state (being illustrated as low level in Fig. 7), thus now this second logic state (being illustrated as low level in Fig. 7) of the 3rd control signal DR3 is delivered to the second positive output end Q2 by the second d type flip flop 504, make the second pattern switch-over control signal TR2 by the first logic state (being illustrated as high level in Fig. 7) saltus step to the second logic state (being illustrated as low level in Fig. 7).At this moment show that boosting duty ratio D2 has been less than the second boosting duty cycle threshold (D _tH2-H2), then the second pattern switch-over control signal TR2 controls this voltage boosting-reducing type switching power converter 100 and switches to voltage boosting-reducing pattern (signals see 706 and 707 cycles Fig. 7) from boost mode.Meanwhile, the pulse duration that second reference wave circuit for generating 503 adjusts the second reference burst signal CR2 in response to second logic state of this second pattern switch-over control signal TR2 increases, and the ratio making its pulse duration account for each pulse signal cycle increases to and equals the duty cycle threshold D that boosts _tH2.So, duty ratio of boosting detects and comparison circuit 1052 just can switch between voltage boosting-reducing pattern and boost mode by the 3rd control signal DR3 and the second reference burst signal CR2 is compared to control power inverter 100.

Be only exemplary based on the description of Fig. 5 to Fig. 7 to the pattern switch control unit 105 according to a disclosure embodiment above, and be not used in the disclosure is limited.It should be appreciated by those skilled in the art, the implementation of pattern switch control unit 105 can have multiple, and it is possible for modifying to the pattern switch control unit 105 of each exemplary embodiment of the disclosure and convert.Such as: also the signal that the first data input pin DI1 of the first d type flip flop 502 and the first input end of clock C1 receives can be exchanged in Figure 5, that is: the first data input pin DI1 receives described first reference burst signal CR1, and the first input end of clock C1 receives described first control signal DR1.Step-down duty ratio with reference to Figure 10 signal detects and comparison circuit 1051, in this case, described first control signal DR1 is as the clock signal of this first d type flip flop 502, thus at each trailing edge of the first control signal DR1, data that its data input pin DI1 receives by the first d type flip flop 502 state of the first reference burst signal CR1 (namely in Figure 10 example) are delivered to the first positive output end Q1 and export and keep, until the next trailing edge of the first control signal DR1 arrives.It is similar that step-down duty ratio in Figure 10 detects with the operation principle of comparison circuit 1051 and Fig. 5, unlike the first d type flip flop 502 in Figure 10 with the first control signal DR1 for clock signal, at each trailing edge of this first control signal DR1 by judging that the state (being such as in the first logic state or the second logic state) of described first reference burst signal CR1 judges that the pulse duration of the first control signal DR1 is greater than or is less than the pulse duration of this first reference burst signal CR1.Thus, the first mode switch-over control signal TR1 that the first d type flip flop 502 in Figure 10 embodiment exports is the first logic state and the effect of the second logic state and just contrary in Fig. 5.Namely in Figure 10 embodiment: control power inverter 100 when first mode switch-over control signal TR1 has the second logic state and switch to voltage boosting-reducing pattern from decompression mode, control power inverter 100 when first mode switch-over control signal TR1 has the first logic state and switch to decompression mode from voltage boosting-reducing pattern.

Waveform signal with reference to figure 6 can better be understood, for the embodiment of Figure 10 signal, if at the trailing edge of the first control signal DR1, first reference burst signal CR1 is still in the second logic state (such as Fig. 6 is illustrated as low level), then show that the pulse duration of the first control signal DR1 has been greater than the pulse duration of this first reference burst signal CR1, now this second logic state (being illustrated as low level in Fig. 6) of the first reference burst signal CR1 is delivered to the first positive output end Q1 by the first d type flip flop 502, make first mode switch-over control signal TR1 by the first logic state (being illustrated as high level in Fig. 6) saltus step to the second logic state (being illustrated as low level in Fig. 6).At this moment show that step-down duty ratio D1 has exceeded step-down duty cycle threshold D _tH1, then first mode switch-over control signal TR1 controls this voltage boosting-reducing type switching power converter 100 and switches to voltage boosting-reducing pattern (signals see 602 and 603 cycles of clock signal of system CLK Fig. 6) from decompression mode.Meanwhile, the pulse duration that first reference wave circuit for generating 501 adjusts the first reference burst signal CR1 in response to second logic state of this first mode switch-over control signal TR1 reduces, and the ratio making its pulse duration account for each pulse signal cycle is reduced to and equals the second step-down duty cycle threshold (D _tH1-H1).At the trailing edge of the first control signal DR1, if the first reference burst signal CR1 still has the first logic state (being illustrated as high level in Fig. 6), then show that the pulse duration of the first control signal DR1 has been less than the pulse duration (signals see 605 cycles of clock signal of system CLK in Fig. 6) of the first reference burst signal CR1, thus now this first logic state (being illustrated as high level in Fig. 6) of this first reference burst signal CR1 is delivered to the first positive output end Q1 by the first d type flip flop 502, make first mode switch-over control signal TR1 by the second logic state (being illustrated as low level in Fig. 6) saltus step to the first logic state (being illustrated as high level in Fig. 6).At this moment show that step-down duty ratio D1 has been less than the second step-down duty cycle threshold (D _tH1-H1), then first mode switch-over control signal TR1 controls this voltage boosting-reducing type switching power converter 100 and switches to decompression mode (signals see 606 and 607 cycles of clock signal of system CLK Fig. 6) from voltage boosting-reducing pattern.Meanwhile, the pulse duration that first reference wave circuit for generating 501 adjusts the first reference burst signal CR1 in response to first logic state of this first mode switch-over control signal TR1 increases, and the ratio making its pulse duration account for each pulse signal cycle increases to and equals step-down duty cycle threshold D _tH1.So, Figure 10 embodiment step-down duty ratio detect and comparison circuit 1051 just can switch between decompression mode and voltage boosting-reducing pattern by the first control signal DR1 and the first reference burst signal CR1 is compared to control power inverter 100.

Similarly, in another variant embodiment, also the signal that the second data input pin DI2 of the second d type flip flop 504 in Fig. 5 and second clock input C2 receives can be exchanged, that is: the second data input pin DI2 receives described second reference burst signal CR2, and second clock input C2 receives described 3rd control signal DR3.Boosting duty ratio with reference to Figure 10 signal detects and comparison circuit 1052, in this case, described 3rd control signal DR2 is as the clock signal of this second d type flip flop 504, thus at each trailing edge of the 3rd control signal DR3, data that its data input pin DI2 receives by the second d type flip flop 504 state of the second reference burst signal CR2 (namely in Figure 10 example) are delivered to the second positive output end Q2 and export and keep, until the next trailing edge of the 3rd control signal DR3 arrives.It is similar that boosting duty ratio in Figure 10 detects with the operation principle of comparison circuit 1052 and Fig. 5, unlike the second d type flip flop 504 in Figure 10 with the 3rd control signal DR3 for clock signal, at each trailing edge of the 3rd control signal DR3 by judging that the state (being such as in the first logic state or the second logic state) of described second reference burst signal CR2 judges that the pulse duration of the 3rd control signal DR3 is greater than or is less than the pulse duration of this second reference burst signal CR2.Thus, the second pattern switch-over control signal TR2 that the second d type flip flop 504 in Figure 10 embodiment exports is the first logic state and the effect of the second logic state and just contrary in Fig. 5.Namely in Figure 10 embodiment: control power inverter 100 when the second pattern switch-over control signal TR2 has the second logic state and switch to boost mode from voltage boosting-reducing pattern, control power inverter 100 when the second pattern switch-over control signal TR2 has the first logic state and switch to voltage boosting-reducing pattern from boost mode.

Waveform signal with reference to figure 7 can better be understood, for the embodiment of Figure 10 signal, if the pulse duration of the 3rd control signal DR3 is greater than the pulse duration (signals see 702 cycles of clock signal of system CLK in Fig. 7) of the second reference burst signal CR2, then at the pulse falling edge of the 3rd control signal DR3, second reference burst signal CR2 is in the second logic state (low level namely illustrated in Fig. 7), thus now this second logic state (being illustrated as low level in Fig. 7) of the second reference burst signal CR2 is delivered to the second positive output end Q2 by the second d type flip flop 504, make the second pattern switch-over control signal TR2 by the first logic state (being illustrated as high level in Fig. 7) saltus step to the second logic state (being illustrated as low level in Fig. 7).At this moment show that boosting duty ratio D2 has exceeded boosting duty cycle threshold D _tH2, then the second pattern switch-over control signal TR2 controls this voltage boosting-reducing type switching power converter 100 and switches to boost mode (switching see 702 to 703 cycles of clock signal of system CLK Fig. 7 is illustrated) from voltage boosting-reducing pattern.Meanwhile, the pulse duration that second reference wave circuit for generating 503 adjusts the second reference burst signal CR2 in response to second logic state of this second pattern switch-over control signal TR2 reduces, and the ratio making its pulse duration account for each pulse signal cycle is reduced to and equals the second boosting duty cycle threshold (D _tH2-H2).If the pulse duration of the 3rd control signal DR3 is less than the pulse duration (signals see 705 cycles of clock signal of system CLK in Fig. 7) of the second reference burst signal CR2, then at the trailing edge of the 3rd control signal DR3, second reference burst signal CR2 has the first logic state (being illustrated as high level in Fig. 7), thus now this first logic state (being illustrated as high level in Fig. 7) of this second reference burst signal CR2 is delivered to the second positive output end Q2 by the second d type flip flop 504, make the second pattern switch-over control signal TR2 by the second logic state (being illustrated as low level in Fig. 7) saltus step to the first logic state (illustrate in Fig. 7 high level).At this moment show that boosting duty ratio D2 has been less than the second boosting duty cycle threshold (D _tH2-H2), then the second pattern switch-over control signal TR2 controls this voltage boosting-reducing type switching power converter 100 and switches to voltage boosting-reducing pattern (signals see 706 and 707 cycles Fig. 7) from boost mode.Meanwhile, the pulse duration that second reference wave circuit for generating 503 adjusts the second reference burst signal CR2 in response to first logic state of this second pattern switch-over control signal TR2 increases, and the ratio making its pulse duration account for each pulse signal cycle increases to and equals the duty cycle threshold D that boosts _tH2.So, duty ratio of boosting detects and comparison circuit 1052 just can switch between voltage boosting-reducing pattern and boost mode by the 3rd control signal DR3 and the second reference burst signal CR2 is compared to control power inverter 100.

In other embodiments, pattern switch control unit 105 also can utilize other signal carrying step-down duty ratio D1 information and boosting duty ratio D2 information respectively realize to the detection of step-down duty ratio D1 and boosting duty ratio D2 and with the comparing of corresponding duty cycle threshold.Such as, in a variant embodiment, the second control signal DR2 can be utilized to replace the first control signal DR1 in Fig. 5 or Figure 10 embodiment.Due to the second control signal DR2 and the complementation of the first control signal DR1 logic state, thus those skilled in the art should be easy to, according to the above operation principle description of Fig. 5 or Figure 10 embodiment being understood to such variant embodiment, repeat no more herein.In another variant embodiment, the 4th control signal DR4 also can be utilized to replace the 3rd control signal DR3 in Fig. 5 or Figure 10 embodiment.Due to the 4th control signal DR4 and the complementation of the 3rd control signal DR3 logic state, thus technical staff should be easy to, according to the above operation principle description of Fig. 5 or Figure 10 embodiment being understood to such variant embodiment, repeat no more herein.Those skilled in the art should also be appreciated that the signal carrying duty cycle information is not limited only to control signal DR1, DR2, DR3 and DR4.

Next to utilize the first pulse width modulating signal PWM1 and the second pulse width modulating signal PWM2 to provide pattern switch control unit 105 according to the another exemplary embodiment of the disclosure.According to an embodiment of the present disclosure, the first pulse width modulating signal PWM1 and the second pulse width modulating signal PWM2 is narrow pulse signal.Each rising edge of a pulse of clock signal of system CLK determines the turn-on instant of the 3rd power switch SWC of the first power switch SWA and the second group power switch centering in first group of Switch Controller, and each rising edge of a pulse of the first pulse width modulating signal PWM1 determines the shutoff moment of the first power switch SWA in first group of Switch Controller, the shutoff moment of the 3rd power switch SWC in the determined second group of Switch Controller of each rising edge of a pulse of the second pulse width modulating signal PWM2.Thus, each rising edge of a pulse of the first pulse width modulating signal PWM1 in fact determines each pulse falling edge moment of the first control signal DR1, and each rising edge of a pulse of the second pulse width modulating signal PWM2 in fact determines each pulse falling edge moment of the 3rd control signal DR3.So can convert the embodiment of Figure 10 signal, in a conversion embodiment, adopt the first pulse width modulating signal PWM1 to replace described first control signal DR1, and select the first d type flip flop 502 to be rising edge flip-flops.In another conversion embodiment, the second pulse width modulating signal PWM2 also can be adopted to replace described second control signal DR2, and select the second d type flip flop 504 to be rising edge flip-flops.

Figure 11 shows the circuit framework schematic diagram of the pattern switch control unit 105 according to the another exemplary embodiment of the disclosure.With reference to the signal of Figure 11, the above-mentioned variant embodiment based on embodiment illustrated in Figure 10 better can be understood.Replace in the variant embodiment of described first control signal DR1 at employing first pulse width modulating signal PWM1, step-down duty ratio with reference to Figure 11 signal detects and comparison circuit 1051, first d type flip flop 502 is that the signal rising edge of input end of clock triggers, and its input end of clock C1 receives described first pulse width modulating signal PWM1.It is similar that step-down duty ratio in Figure 11 detects with the operation principle of comparison circuit 1051 and Figure 10, be its clock signal unlike the first d type flip flop 502 in Figure 11 with the first pulse width modulating signal PWM1, at each rising edge of this first pulse width modulating signal PWM1 by judging that the state (being such as in the first logic state or the second logic state) of described first reference burst signal CR1 judges that the pulse duration of the first control signal DR1 is greater than or is less than the pulse duration of the first reference burst signal CR1.And then realize step-down duty ratio D1 and step-down duty cycle threshold D _tH1with the second step-down duty cycle threshold (D _tH1-H1) comparison.The first mode switch-over control signal TR1 that the first d type flip flop 502 in Figure 11 embodiment exports is the first logic state and the effect of the second logic state and identical in Figure 10.

Waveform signal with reference to Figure 12 can better be understood, for the step-down duty ratio Detection & Controling circuit 1051 of Figure 11 signal, if at the rising edge of the first pulse width modulating signal PWM1, first reference burst signal CR1 is still in the second logic state (such as Figure 12 is illustrated as low level), then show that the pulse duration of the first control signal DR1 has been greater than the pulse duration of this first reference burst signal CR1, this also means that step-down duty ratio D1 has exceeded step-down duty cycle threshold D _tH1.Now this second logic state (being illustrated as low level in Figure 12) of the first control signal DR1 is delivered to the first positive output end Q1 by the first d type flip flop 502, makes first mode switch-over control signal TR1 by the first logic state (being illustrated as high level in Figure 12) saltus step to the second logic state (being illustrated as low level in Figure 12).At this moment first mode switch-over control signal TR1 controls this voltage boosting-reducing type switching power converter 100 and switches to voltage boosting-reducing pattern (signals see 1202 and 1203 cycles of clock signal of system CLK Figure 12) from decompression mode.Meanwhile, the pulse duration that first reference wave circuit for generating 501 adjusts the first reference burst signal CR1 in response to second logic state of this first mode switch-over control signal TR1 reduces, and the ratio making its pulse duration account for each pulse signal cycle is reduced to and equals the second step-down duty cycle threshold (D _tH1-H1).At the rising edge of the first pulse width modulating signal PWM1, if the first reference burst signal CR1 still has the first logic state (being illustrated as high level in Figure 12), then show that the pulse duration of the first control signal DR1 has been less than the pulse duration (signals see 1205 cycles of clock signal of system CLK in Figure 12) of the first reference burst signal CR1, this also means that step-down duty ratio D1 has been less than the second step-down duty cycle threshold (D _tH1-H1).Thus now this first logic state (being illustrated as high level in Fig. 6) of this first reference burst signal CR1 is delivered to the first positive output end Q1 by the first d type flip flop 502, makes first mode switch-over control signal TR1 by the second logic state (being illustrated as low level in Fig. 6) saltus step to the first logic state (being illustrated as high level in Fig. 6).At this moment first mode switch-over control signal TR1 controls this voltage boosting-reducing type switching power converter 100 and switches to decompression mode (signals see 606 and 607 cycles of clock signal of system CLK Fig. 6) from voltage boosting-reducing pattern.Meanwhile, the pulse duration that first reference wave circuit for generating 501 adjusts the first reference burst signal CR1 in response to first logic state of this first mode switch-over control signal TR1 increases, and the ratio making its pulse duration account for each pulse signal cycle increases to and equals step-down duty cycle threshold D _tH1.So, the pulse duration of step-down duty ratio detects and comparison circuit 1051 just achieves the first control signal DR1 the pulse duration (characterizing step-down duty ratio D1) and the first reference burst signal CR1 of Figure 11 embodiment (characterizes step-down duty cycle threshold D _tH1with the second step-down duty cycle threshold (D _tH1-H1)) comparison switch between decompression mode and voltage boosting-reducing pattern to control power inverter 100.

Replace in the variant embodiment of described 3rd control signal DR3 at employing second pulse width modulating signal PWM2, boosting duty ratio with reference to Figure 11 signal detects and comparison circuit 1052, second d type flip flop 504 is that the signal rising edge of input end of clock triggers, and its input end of clock C2 receives described second pulse width modulating signal PWM2.It is similar that boosting duty ratio in Figure 11 detects with the operation principle of comparison circuit 1052 and Figure 10, be its clock signal unlike the second d type flip flop 504 in Figure 11 with the second pulse width modulating signal PWM2, at each rising edge of this second pulse width modulating signal PWM2 by judging that the state (being such as in the first logic state or the second logic state) of described second reference burst signal CR2 judges that the pulse duration of the 3rd control signal DR3 is greater than or is less than the pulse duration of the second reference burst signal CR2.And then realize boosting duty ratio D2 and boosting duty cycle threshold D _tH2with the second boosting duty cycle threshold (D _tH2-H2) comparison.The second pattern switch-over control signal TR2 that the second d type flip flop 504 in Figure 11 embodiment exports is the first logic state and the effect of the second logic state and identical in Figure 10.

Waveform signal with reference to Figure 13 can better be understood, boosting duty ratio for Figure 11 signal detects and comparison circuit 1052, at the rising edge of the second pulse width modulating signal PWM2, if the second reference burst signal CR2 is in the second logic state (low level namely illustrated in Fig. 7), then show that the pulse duration of the 3rd control signal DR3 has been greater than the pulse duration (signals see 1302 cycles of clock signal of system CLK in Figure 13) of the second reference burst signal CR2, this also means that boosting duty ratio D2 has exceeded boosting duty cycle threshold D _tH2.Now this second logic state (being illustrated as low level in Figure 13) of the second reference burst signal CR2 is delivered to the second positive output end Q2 by the second d type flip flop 504, makes the second pattern switch-over control signal TR2 by the first logic state (being illustrated as high level in Figure 13) saltus step to the second logic state (being illustrated as low level in Figure 13).At this moment the second pattern switch-over control signal TR2 controls this voltage boosting-reducing type switching power converter 100 and switches to boost mode (switching see 1302 to 1303 cycles of clock signal of system CLK Figure 13 is illustrated) from voltage boosting-reducing pattern.Meanwhile, the pulse duration that second reference wave circuit for generating 503 adjusts the second reference burst signal CR2 in response to second logic state of this second pattern switch-over control signal TR2 reduces, and the ratio making its pulse duration account for each pulse signal cycle is reduced to and equals the second boosting duty cycle threshold (D _tH2-H2).At the rising edge of the second pulse width modulating signal PWM2, if the second reference burst signal CR2 has the first logic state (being illustrated as high level in Figure 13), then show that the pulse duration of the 3rd control signal DR3 has been less than the pulse duration (signals see 1305 cycles of clock signal of system CLK in Figure 13) of the second reference burst signal CR2, this also means that boosting duty ratio D2 has been less than the second boosting duty cycle threshold (D _tH2-H2).Now this first logic state (being illustrated as high level in Figure 13) of this second reference burst signal CR2 is delivered to the second positive output end Q2 by the second d type flip flop 504, makes the second pattern switch-over control signal TR2 by the second logic state (being illustrated as low level in Figure 13) saltus step to the first logic state (illustrate in Figure 13 high level).At this moment the second pattern switch-over control signal TR2 controls this voltage boosting-reducing type switching power converter 100 and switches to voltage boosting-reducing pattern (signals see 1306 and 1307 cycles Figure 13) from boost mode.Meanwhile, the pulse duration that second reference wave circuit for generating 503 adjusts the second reference burst signal CR2 in response to first logic state of this second pattern switch-over control signal TR2 increases, and the ratio making its pulse duration account for each pulse signal cycle increases to and equals the duty cycle threshold D that boosts _tH2.So, the pulse duration of boosting duty ratio detects and comparison circuit 1052 just achieves the 3rd control signal DR3 the pulse duration (characterizing the duty ratio D2 that boosts) and the second reference burst signal CR2 of Figure 11 embodiment (characterizes the duty cycle threshold D that boosts _tH2with the second boosting duty cycle threshold (D _tH2-H2)) comparison switch between voltage boosting-reducing pattern and boost mode to control power inverter 100.

The each exemplary embodiment described based on above Fig. 1 to Figure 13 according to the disclosure and embodiment variant thereof, control circuit 108 can regulate voltage raising and reducing type switching power converter 100 automatically steadily to switch between decompression mode and voltage boosting-reducing pattern and between voltage boosting-reducing pattern and boost mode.Control circuit 108 comprises pattern switch control unit 105, this pattern switch control unit 105 can detect step-down duty ratio D1 and boosting duty ratio D2, and by step-down duty ratio D1 and boosting duty ratio D2 detected value respectively with step-down duty cycle threshold D _tH1with boosting duty cycle threshold D _tH2relatively, the mode of operation of output control voltage raising and reducing type switching power converter 100 automatically switches based on the comparison.In one embodiment, the detection of pattern switch control unit 105 by utilizing the signal (control signal of such as switch element or pulse width modulating signal) carrying step-down duty ratio D1 and boosting duty ratio D2 information respectively to realize step-down duty ratio D1 and boosting duty ratio D2.Thus without the need to additional duty detection circuit, but utilize the existing signal in control circuit 108, not only realize simple but also cost-saving and be of value to raising integrated level.In one embodiment, pattern switch control unit 105 compare the pulse duration of the control signal of switch element and the pulse duration of reference burst signal to realize step-down duty ratio D1 and boost duty ratio D2 respectively with the comparing of corresponding duty cycle threshold.Such as, in the exemplary embodiment of Fig. 5 or Figure 10 or Figure 11, the first control signal DR1 (characterizing step-down duty ratio D1) is compared with the pulse duration of the first reference burst signal CR1 and achieves step-down duty ratio D1 and step-down duty cycle threshold D _tH1with the second step-down duty cycle threshold (D _tH1-H1) comparison, thus accurately control this voltage raising and reducing type switching power converter 100 smooth conversion between decompression mode and voltage boosting-reducing pattern according to comparative result.Not only realizing circuit is simple, and the instability between decompression mode and these two kinds of patterns of critical part of voltage boosting-reducing pattern can be avoided repeatedly to switch, and output voltage Vo there will not be large fluctuation spike.In the exemplary embodiment of Fig. 5 or Figure 10 or Figure 11, also the pulse duration of the 3rd control signal DR3 and the second reference burst signal CR2 is compared and achieve boosting duty ratio D2 and boosting duty cycle threshold D _tH2with the second boosting duty cycle threshold (D _tH2-H2) comparison, thus accurately control this voltage raising and reducing type switching power converter 100 smooth conversion between voltage boosting-reducing pattern and boost mode according to comparative result.Not only realizing circuit is simple, and the instability between voltage boosting-reducing pattern and these two kinds of patterns of critical part of boost mode can be avoided repeatedly to switch, and output voltage Vo there will not be large fluctuation spike.

Should not be considered to only to be confined to above-described according to the beneficial effect of the control circuit 108 of each embodiment of the disclosure and variant embodiment thereof, pattern switch control unit 105 and voltage raising and reducing type switching power converter 100.Can be better understood by the accompanying drawing read detailed description of the present disclosure and study each embodiment according to these and other beneficial effect of each embodiment of the disclosure.

Above-mentioned specification of the present disclosure and execution mode are only illustrated the control circuit of disclosure embodiment, pattern switch control unit, the power inverter comprising this control circuit and/or pattern switch control unit unit and control method thereof in an exemplary fashion, and are not used in restriction the scope of the present disclosure.It is all possible for carrying out changing and revising for disclosed embodiment, other feasible selectivity embodiments and to the equivalent variations of element in embodiment can understand by those skilled in the art.Other changes of disclosure the disclosed embodiments and amendment do not exceed spirit of the present disclosure and protection range.

Claims

1. a pattern switch control unit, for controlling voltage raising and reducing type switching power converter automatically between decompression mode and voltage boosting-reducing pattern, and steadily switch between voltage boosting-reducing pattern and boost mode, wherein this voltage raising and reducing type switching power converter comprises switch element, this switch element comprise the first power switch to the second power switch pair, and the first power switch of the first power switch centering and the second power switch coupled in series are in the input of this voltage raising and reducing type switching power converter with reference between ground, the ratio that the ON time of the first power switch accounts for whole first power switch and the second power switch turn-on and turn-off switching cycle is step-down duty ratio, 3rd power switch of the second power switch centering and the 4th power switch coupled in series are in the output of this voltage raising and reducing type switching power converter with reference between ground, and the ON time of the 3rd power switch accounts for the ratio of the turn-on and turn-off switching cycle of whole 3rd power switch and the 4th power switch for boosting duty ratio, this pattern switch control unit comprises:

Step-down duty ratio detects and comparison circuit, there is the first detection input and first and compare output, this the first detection input is for receiving the signal characterizing step-down duty ratio, this step-down duty ratio detects with comparison circuit for generation of the signal characterizing step-down duty cycle threshold, and providing first mode switch-over control signal to compare output described first by the signal characterizing this step-down duty ratio compared with characterizing the signal of step-down duty cycle threshold, wherein said step-down duty cycle threshold has the first sluggishness; If step-down duty ratio is greater than step-down duty cycle threshold, then first mode switch-over control signal controls described voltage raising and reducing type switching power converter and switches to voltage boosting-reducing pattern from decompression mode, make described step-down duty cycle threshold be reduced to the second step-down duty cycle threshold, the amount of reduction equals described first sluggishness simultaneously; If step-down duty ratio is less than described second step-down duty cycle threshold, then first mode switch-over control signal controls described voltage raising and reducing type switching power converter and switches to decompression mode from voltage boosting-reducing pattern, makes step-down duty cycle threshold recover initial value simultaneously; With

Boosting duty ratio detects and comparison circuit, there is the second detection input and second and compare output, this the second detection input is for receiving the signal characterizing boosting duty ratio, this boosting duty ratio detects with comparison circuit for generation of the signal characterizing duty cycle threshold of boosting, and providing second pattern switch-over control signal to compare output described second by the signal characterizing this boosting duty ratio compared with characterizing the signal of duty cycle threshold of boosting, wherein said boosting duty cycle threshold has the second sluggishness; If boosting duty ratio is greater than boosting duty cycle threshold, then the second pattern switch-over control signal controls described voltage raising and reducing type switching power converter and switches to boost mode from voltage boosting-reducing pattern, make described boosting duty cycle threshold be reduced to the second boosting duty cycle threshold, and the amount reduced equal described second sluggishness simultaneously; If boosting duty ratio is less than described second boosting duty cycle threshold, then the second pattern switch-over control signal controls described voltage raising and reducing type switching power converter from boost mode switching rise pressure-decompression mode, makes boosting duty cycle threshold recover initial value simultaneously.

2. pattern switch control unit according to claim 1, the signal of wherein said sign step-down duty ratio comprises the first control signal or the second control signal, this first control signal switches with shutoff for the conducting controlling described first power switch, this second control signal carries out switching with the conducting of described first power switch complementation and shutoff for controlling described second power switch, the signal of described sign step-down duty cycle threshold comprises the first reference burst signal and this first reference burst signal has the pulse duration of setting, described step-down duty ratio detects and is used for the pulse duration of described first control signal and the pulse duration of described reference burst signal to compare to produce described first mode switch-over control signal with comparison circuit.

3. pattern switch control unit according to claim 1, the wherein said signal characterizing boosting duty ratio comprises the 3rd control signal or the 4th control signal, 3rd control signal switches with shutoff for the conducting controlling described 3rd power switch, 4th control signal carries out switching with the conducting of described 3rd power switch complementation and shutoff for controlling described 4th power switch, the described signal characterizing boosting duty cycle threshold comprises the second reference burst signal and this second reference burst signal has the pulse duration of setting, described step-down duty ratio detects and is used for the pulse duration of described 3rd control signal and the pulse duration of described second reference burst signal to compare to produce described second pattern switch-over control signal with comparison circuit.

4. pattern switch control unit according to claim 1, wherein, described step-down duty ratio detects and comprises with comparison circuit:

First reference wave circuit for generating, there is control input end and output, wherein this control input end is for receiving described first mode switch-over control signal, this the first reference wave circuit for generating is used for providing the first reference burst signal at its output, and the pulse duration of this first reference burst signal is adjusted based on first mode switch-over control signal, the ratio making the pulse duration of this first reference burst signal account for each pulse signal cycle equals the second step-down duty cycle threshold when step-down duty ratio is greater than step-down duty cycle threshold, and step-down duty cycle threshold is equaled when step-down duty ratio is less than the second step-down duty cycle threshold, with

First d type flip flop, there is the first data input pin, the first input end of clock and the first positive output end, this first data input pin carries out conducting for receiving described first power switch of control and turns off the first control signal switched, first input end of clock is for receiving described first reference burst signal, and the first control signal that its first data input pin receives is delivered to the first positive output end at each pulse falling edge of described first reference burst signal and exports and keep as described first mode switch-over control signal by this first d type flip flop; Wherein

Described first control signal, the first reference burst signal and first mode switch-over control signal all have the first logic state and the second logic state, and show that when first mode switch-over control signal switches to the first logic state from the second logic state described step-down duty ratio is greater than described step-down duty cycle threshold, show that when first mode switch-over control signal switches to the second logic state from the first logic state described step-down duty ratio is less than described second step-down duty cycle threshold.

5. pattern switch control unit according to claim 1, wherein, described step-down duty ratio detects and comprises with comparison circuit:

First d type flip flop, there is the first data input pin, the first input end of clock and the first positive output end, this first data input pin carries out conducting for receiving described second power switch of control and turns off the second control signal switched, first input end of clock is for receiving described first reference burst signal, and the second control signal that its first data input pin receives is delivered to the first positive output end at each pulse falling edge of described first reference burst signal and exports and keep as described first mode switch-over control signal by this first d type flip flop; Wherein

Described second control signal, the first reference burst signal and first mode switch-over control signal all have the first logic state and the second logic state, and show that when first mode switch-over control signal switches to the second logic state from the first logic state described step-down duty ratio is greater than described step-down duty cycle threshold, show that when first mode switch-over control signal switches to the first logic state from the second logic state described step-down duty ratio is less than described second step-down duty cycle threshold.

6. pattern switch control unit according to claim 1, wherein, described step-down duty ratio detects and comprises with comparison circuit:

First d type flip flop, there is the first data input pin, the first input end of clock and the first positive output end, this first data input pin is for receiving described first reference burst signal, first input end of clock carries out conducting for receiving described first power switch of control and turns off the first control signal switched, and the first reference burst signal that its first data input pin receives is delivered to the first positive output end at each pulse falling edge of described first control signal and exports and keep as described first mode switch-over control signal by this first d type flip flop; Wherein

Described first control signal, the first reference burst signal and first mode switch-over control signal all have the first logic state and the second logic state, and show that when first mode switch-over control signal switches to the second logic state from the first logic state described step-down duty ratio is greater than described step-down duty cycle threshold, show that when first mode switch-over control signal switches to the first logic state from the second logic state described step-down duty ratio is less than described second step-down duty cycle threshold.

7. pattern switch control unit according to claim 1, wherein, described step-down duty ratio detects and comprises with comparison circuit:

First d type flip flop, there is the first data input pin, the first input end of clock and the first positive output end, this first data input pin is for receiving described first reference burst signal, first input end of clock carries out conducting for receiving described second power switch of control and turns off the second control signal switched, and the first reference burst signal that its first data input pin receives is delivered to the first positive output end at each rising edge of a pulse of described second control signal and exports and keep as described first mode switch-over control signal by this first d type flip flop; Wherein

8. pattern switch control unit according to claim 1, wherein, described step-down duty ratio detects and comprises with comparison circuit:

First d type flip flop, there is the first data input pin, first input end of clock and the first positive output end, this first data input pin is for receiving described first reference burst signal, first input end of clock is for receiving the first pulse width modulating signal, wherein each rising edge of a pulse of this first pulse width modulating signal determines the shutoff moment of described first power switch, the first reference burst signal that its first data input pin receives is delivered to the first positive output end at each rising edge of a pulse of described first pulse width modulating signal and exports and keep as described first mode switch-over control signal by this first d type flip flop, wherein

Described first reference burst signal and first mode switch-over control signal all have the first logic state and the second logic state, and show that when first mode switch-over control signal switches to the second logic state from the first logic state described step-down duty ratio is greater than described step-down duty cycle threshold, show that when first mode switch-over control signal switches to the first logic state from the second logic state described step-down duty ratio is less than described second step-down duty cycle threshold.

9. pattern switch control unit according to claim 1, wherein, described boosting duty ratio detects and comprises with comparison circuit:

Second reference wave circuit for generating, there is control input end and output, wherein this control input end is for receiving described second pattern switch-over control signal, this the second reference wave circuit for generating is used for providing the second reference burst signal at its output, and the pulse duration of this second reference burst signal is adjusted based on the second pattern switch-over control signal, the ratio making the pulse duration of this second reference burst signal account for each pulse signal cycle equals the second boosting duty cycle threshold when duty ratio of boosting is greater than step-down duty cycle threshold, and equal to boost duty cycle threshold when step-down duty ratio is less than the second step-down duty cycle threshold, with

Second d type flip flop, there is the second data input pin, second clock input and the second positive output end, this second data input pin carries out conducting for receiving described 3rd power switch of control and turns off the 3rd control signal switched, second clock input is for receiving described second reference burst signal, and the 3rd control signal that its second data input pin receives is delivered to the first positive output end at each pulse falling edge of described second reference burst signal and exports and keep as described first mode switch-over control signal by this second d type flip flop; Wherein

Described 3rd control signal, the second reference burst signal and the second pattern switch-over control signal all have the first logic state and the second logic state, and show that when the second pattern switch-over control signal switches to the first logic state from the second logic state described boosting duty ratio is greater than described boosting duty cycle threshold, show that when the second pattern switch-over control signal switches to the second logic state from the first logic state described boosting duty ratio is less than described second boosting duty cycle threshold.

10. pattern switch control unit according to claim 1, wherein, described boosting duty ratio detects and comprises with comparison circuit:

Second d type flip flop, there is the second data input pin, second clock input and the second positive output end, this second data input pin carries out conducting for receiving described 4th power switch of control and turns off the 4th control signal switched, second clock input is for receiving described second reference burst signal, and the 4th control signal that its second data input pin receives is delivered to the second positive output end at each pulse falling edge of described second reference burst signal and exports and keep as described second pattern switch-over control signal by this second d type flip flop; Wherein

Described 4th control signal, the second reference burst signal and the second pattern switch-over control signal all have the first logic state and the second logic state, and show that when the second pattern switch-over control signal switches to the second logic state from the first logic state described boosting duty ratio is greater than described boosting duty cycle threshold, show that when the second pattern switch-over control signal switches to the first logic state from the second logic state described boosting duty ratio is less than described second boosting duty cycle threshold.

11. pattern switch control units according to claim 1, wherein, described boosting duty ratio detects and comprises with comparison circuit:

Second d type flip flop, there is the second data input pin, second clock input and the second positive output end, this second data input pin is for receiving described second reference burst signal, second clock input carries out conducting for receiving described 3rd power switch of control and turns off the 3rd control signal switched, and the second reference burst signal that its second data input pin receives is delivered to the second positive output end at each pulse falling edge of described 3rd control signal and exports and keep as described second pattern switch-over control signal by this second d type flip flop; Wherein

Described 3rd control signal, the second reference burst signal and the second pattern switch-over control signal all have the first logic state and the second logic state, and show that when the second pattern switch-over control signal switches to the second logic state from the first logic state described boosting duty ratio is greater than described boosting duty cycle threshold, show that when the second pattern switch-over control signal switches to the first logic state from the second logic state described boosting duty ratio is less than described second boosting duty cycle threshold.

12. pattern switch control units according to claim 1, wherein, described boosting duty ratio detects and comprises with comparison circuit:

Second d type flip flop, there is the second data input pin, second clock input and the second positive output end, this second data input pin is for receiving described second reference burst signal, second clock input carries out conducting for receiving described 4th power switch of control and turns off the 4th control signal switched, and the second reference burst signal that its second data input pin receives is delivered to the second positive output end at each rising edge of a pulse of described 4th control signal and exports and keep as described second pattern switch-over control signal by this second d type flip flop; Wherein

13. pattern switch control units according to claim 1, wherein, described boosting duty ratio detects and comprises with comparison circuit:

Second d type flip flop, there is the second data input pin, second clock input and the second positive output end, this second data input pin is for receiving described second reference burst signal, second clock input is for receiving the second pulse width modulating signal, wherein each rising edge of a pulse of this second pulse width modulating signal determines the shutoff moment of described second power switch, the second reference burst signal that its second data input pin receives is delivered to the second positive output end at each rising edge of a pulse of described second pulse width modulating signal and exports and keep as described second pattern switch-over control signal by this second d type flip flop, wherein

Described second reference burst signal and the second pattern switch-over control signal all have the first logic state and the second logic state, and show that when the second pattern switch-over control signal switches to the second logic state from the first logic state described boosting duty ratio is greater than described boosting duty cycle threshold, show that when the second pattern switch-over control signal switches to the first logic state from the second logic state described boosting duty ratio is less than described second boosting duty cycle threshold.

14. 1 kinds of voltage raising and reducing type switching power converters, comprise as one of them pattern switch control unit of claim 1 to 13.

15. 1 kinds of voltage raising and reducing type switching power converters, comprising:

Input, for receiving input voltage;

Output, for providing output voltage;

Switch element, comprise first group of power switch to second group of power switch pair, wherein the first power switch of first group of power switch centering and the second power switch coupled in series are in described input with reference between ground, and the 3rd power switch of second group of power switch centering and the 4th power switch coupled in series are in output with reference between ground; And

Control circuit, for receiving system clock signal, characterize described output voltage the first feedback signal, characterize the second feedback signal flowing through the switching current of described switch element and the reference signal of desired value characterizing described output voltage;

Described control circuit is fabricated for based on described first feedback signal, second feedback signal, reference signal and clock signal of system provide the first control signal, second control signal, 3rd control signal and the 4th control signal are respectively to described first power switch, second power switch, 3rd power switch and the 4th power switch, wherein said first control signal and described second control signal logic state complementation, the turn-on and turn-off being respectively used to control described first power switch and the second power switch switch, wherein the ON time of the first power switch accounts for the ratio of whole first power switch and the second power switch turn-on and turn-off switching cycle is step-down duty ratio, described 3rd control signal and described 4th control signal logic state complementation, the turn-on and turn-off being respectively used to control described 3rd power switch and described 4th power switch switch, and wherein the ON time of the 3rd power switch accounts for the ratio of the turn-on and turn-off switching cycle of whole 3rd power switch and the 4th power switch for boosting duty ratio, wherein

Described control circuit comprises as one of them pattern switch control unit of claim 1 to 13.

16. voltage raising and reducing type switching power converters according to claim 15, wherein:

At decompression mode, this control circuit makes this voltage raising and reducing type switching power converter carry out the work of depressure cycle continuously and stably, depressure cycle refers to that the first power switch in first group of Switch Controller and the second power switch carry out complementally turn-on and turn-off and switch, the 3rd power switch in second group of Switch Controller continues to keep turning off, and the 4th power switch continues to keep conducting;

At boost mode, this control circuit makes this voltage raising and reducing type switching power converter carry out the work of boosting period continuously and stably, boosting period refers to that the 3rd power switch in second group of switch and the 4th power switch carry out complementally turn-on and turn-off and switch, and the first power switch in first group of Switch Controller continues to keep conducting, the second power switch continues to keep turning off;

In voltage boosting-reducing pattern, the work that this control circuit makes this voltage raising and reducing type switching power converter carry out a depressure cycle and a boosting period continuously and stably to replace.

17. voltage raising and reducing type switching power converters according to claim 15, wherein said first power switch and the public of the second power switch couple end formation first switching node, the public end that couples of described 3rd power switch and the 4th power switch forms second switch node, this voltage raising and reducing type switching power converter comprises perceptual energy-storage travelling wave tube further, is coupled between described first switching node and described second switch node.

18. voltage raising and reducing type switching power converters according to claim 15, wherein said control circuit comprises further:

Error amplifying unit, for described first feedback signal and described reference signal are carried out computing, to provide the difference amplifying signal of the difference characterizing this first feedback signal and this reference signal;

Current detecting and slope compensation unit, for detecting described switching current to provide described second feedback signal, and described second feedback signal is superposed respectively the first slope compensation signal and the second slope compensation signal to produce the first current detection signal and the second current detection signal respectively, the bias voltage that wherein the second slope compensation signal superposes setting by the first slope compensation signal obtains, and makes the peak value of the first slope compensation signal equal with the valley of the second slope compensation signal;

Depressure cycle pwm unit, for receiving described difference amplifying signal and described first current detection signal, and compares to export the first pulse width modulating signal with difference amplifying signal by this first current detection signal;

Boosting period pwm unit, for receiving described difference amplifying signal and described second current detection signal, and compares to export the second pulse width modulating signal with difference amplifying signal by this second current detection signal; And

Logic control element, receive described first pulse width modulating signal, the second pulse width modulating signal, clock signal of system, first mode switch-over control signal and the second pattern switch-over control signal, and at least produce described first control signal, the second control signal, the 3rd control signal and the 4th control signal based on this first pulse width modulating signal, the second pulse width modulating signal, clock signal of system, first mode switch-over control signal and the second pattern switch-over control signal.

19. 1 kinds of control circuits, for controlling voltage raising and reducing type switching power converter, this control circuit comprises as one of them pattern switch control unit of claim 1 to 13.

20. as the control circuit of claim 19, wherein

The reference signal that this control circuit is used for receiving system clock signal, characterizes the first feedback signal of the output voltage of described voltage raising and reducing type switching power converter, characterizes the second feedback signal flowing through the switching current of described switch element and the desired value characterizing described output voltage;

Described control circuit is fabricated for based on described first feedback signal, second feedback signal, reference signal and clock signal of system provide the first control signal, second control signal, 3rd control signal and the 4th control signal are respectively to described first power switch, second power switch, 3rd power switch and the 4th power switch, wherein said first control signal and described second control signal logic state complementation, the turn-on and turn-off being respectively used to control described first power switch and the second power switch switch, described 3rd control signal and described 4th control signal logic state complementation, the turn-on and turn-off being respectively used to control described 3rd power switch and described 4th power switch switch.