CN204216883U - The background calibration circuit of pipeline ADC - Google Patents

Abstract

The utility model provides a kind of background calibration circuit of pipeline ADC, for each pipelining-stage needing calibration of pipeline ADC, this circuit comprises random number generation unit, first passage, second channel and post-processing unit, wherein, described post-processing unit is configured to, according to described first digital output signal V _aDC1[n] and the second digital output signal V _aDC2[n], described first random number P _n1[n] and the second random number P _n2[n], described first rear end output signal R _n1[n] and the second rear end output signal R _n2[n], obtains the output signal Do [n] after calibrating.The background calibration circuit of pipeline ADC of the present utility model, can calibrate the not enough and single order that do not mate with the electric capacity of its front end and introduce of gain due to operational amplifier and three rank errors simultaneously, and improve the convergence rate of calibration algorithm.

Description

Background calibration circuit of pipeline ADC

Technical Field

The utility model relates to a backstage calibration circuit of assembly line ADC.

Background

High-speed, high-precision pipelined ADCs (analog-to-digital converters) are an important component of analog integrated circuits. As shown in FIG. 1, the pipelined ADC comprises a plurality of pipeline stages, wherein each pipeline stage of the first N pipeline stages outputs two signals, wherein the digital output signal V_ADCOutput to a digital signal processing unit, and output a residual output signal R_nOutput to the next pipeline stage. The first N pipeline stages are shown in fig. 2, and include a sub ADC, a sub DAC, a subtractor, a residue amplifier, and the like.

Referring to fig. 2, in each pipeline stage of the pipeline ADC, an analog input signal V is applied_in(nT_s) Input into the sub-ADC for quantization to generate a digital output signal V_ADC[n](ii) a Then the digital output signal V is converted into a digital output signal_ADC[n]Sending the analog signal into sub-DAC for digital-to-analog conversion to obtain an analog quantity, and using the analog input signal V_in(nT_s) The analog quantity is subtracted to obtain a residual (residual) signal V_res(nT_s) (ii) a The residual signal V is used_res(nT_s) Obtaining a margin output signal R after being amplified by a margin amplifier_n(nT_s). The residual output signal R_n(nT_s) And outputting the analog input signal to the next pipeline stage as the analog input signal of the next pipeline stage.

The operational amplifier included in the residue amplifier generally causes first and third order errors due to its insufficient gain and mismatch between its capacitance (e.g., sampling capacitance, feedback capacitance, etc.) and its front end. As the manufacture of the assembly line ADC enters a deep submicron process, the first-order and third-order errors introduced by the operational amplifier become obvious, the linearity of the assembly line ADC is reduced, the SFDR is poor, and the noise floor is increased. The traditional calibration method of the ADC only calibrates the first-order coefficient of the operational amplifier, and cannot calibrate the third-order error introduced by the operational amplifier. Some proposals have been made in recent years to calibrate the first and third order coefficients of the residue amplifier simultaneously, but these calibration algorithms have a slow convergence rate.

Calibration methods for ADCs are generally divided into foreground calibration and background calibration. The foreground calibration needs to be performed after the ADC stops working, and the background calibration can be performed during the working process of the ADC, and when external factors (e.g., temperature, power supply voltage, etc.) change, the first-order and third-order errors of the residue amplifier are calibrated in real time.

The utility model aims at providing a can calibrate the backstage calibration circuit of the first order and third-order error that operational amplifier introduced fast simultaneously.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a backstage calibration circuit of assembly line ADC when can calibrate the first order and third-order error that operational amplifier introduced simultaneously, has improved calibration algorithm's convergence rate.

Therefore, the utility model provides a backstage calibration circuit of assembly line ADC for every pipeline stage that needs the calibration of assembly line ADC, this circuit include random number generation unit, first passageway, second passageway and post-processing unit, wherein, random number generation unit has output first random number P_n1[n]And outputs a second random number P_n2[n]A second output terminal of (1); the first channel comprises a first sub-ADC, a first sub-DAC, a first subtracter and a first residue amplifier which are sequentially connected, and the input end of the first sub-ADC is connected with a first input signal V_in+(nT_s) The first channel further comprises a first adder having a first input connected to the output of the first sub-ADC for receiving a first digital output signal V_ADC1[n]A second input terminal of the second residue amplifier is connected to the first output terminal of the random number generating unit, an output terminal of the second residue amplifier is connected to the input terminal of the second sub-DAC, an output terminal of the second residue amplifier is connected to the input terminal of the second back-end ADC, and an output terminal of the second back-end ADC outputs a second back-end output signal R_n1[n]And connected to the post-processing unit; the second channel comprises a second sub-ADC, a second sub-DAC, a second subtracter and a second residue amplifier which are sequentially connected, and the input end of the second sub-ADC is connected with a second input signal V_in-(nT_s) The second channel further comprises a second adder having a first input connected to the output of the second sub-ADC for receiving a second digital output signal V_ADC2[n]A second input terminal thereof is connected to the second output terminal of the random number generation unit, and an output terminal thereof is connected to the input terminal of the second sub-DAC; the output end of the second residue amplifier is connected to the input end of a second rear-end ADC (analog to digital converter), and the output end of the second rear-end ADC outputs a first signalRear end output signal R_n1[n]And connected to the post-processing unit; the post-processing unit is configured to output a first digital output signal V according to the first digital output signal_ADC1[n]And a second digital output signal V_ADC2[n]The first random number P_n1[n]And a second random number P_n2[n]The first rear end output signal R_n1[n]And a second back-end output signal R_n2[n]Obtaining the calibrated output signal Do [ n ]]。

Further, the random number generation unit comprises a random number generation subunit, an amplification subunit and a gating subunit which are connected in sequence: the random number generation subunit outputs a random signal Pn [ n ] with an average value of 0 and values of 1 and-1](ii) a The amplification subunit pairs the random signal Pn [ n]Amplifying with an amplification factor of A_pn1、A_pn2And u; the gating subunit gates the output of the amplifying subunit and comprises a first control end connected with control signals Ctrl [1:0] comprising four states]The gating subunit is configured to, when the control signal Ctrl [1:0]]When the first state is reached, the first random number P is output_n1[n]Is A_pn1·P_n[n]Said second random number P_n2[n]Is A_pn1·P_n[n]When the control signal Ctrl [1:0]]When the first random number is in the second state, the first random number P is output_n1[n]Is A_pn2·P_n[n]Said second random number P_n2[n]Is A_pn2·P_n[n]When the control signal Ctrl [1:0]]The first random number P is output when the state is the third state_n1[n]Is A_pn1·P_n[n]Said second random number P_n2[n]Is u.A_pn1·P_n[n]When the control signal Ctrl [1:0]]The first random number P is output when the state is the fourth state_n1[n]Is A_pn2·P_n[n]Said second random number P_n2[n]Is u.A_pn2·P_n[n]。

Further, the post-processing unit includes: a first intermediate value operator unit configured to calculate the first intermediate value temp, which comprises: a first arithmetic module for calculating (R)_n1[n]+R_n2[n])·P_n1[n]And a first mean module for calculating a statistical time horizon (R)_n1[n]+R_n2[n])·P_n1[n]The mean value of (a); a second intermediate value operator unit configured to calculate the second intermediate value nn, comprising: a second arithmetic module for calculating (R)_n1[n]+P_n1[n])²And a second averaging module for calculating (R) over statistical time_n1[n]+P_n1[n])²The mean value of (a); an error coefficient calculation subunit having inputs connected to outputs of said first and second intermediate value calculation subunit, respectively, and being configured to calculate said first order error coefficient α based on said first intermediate value temp and said second intermediate value nn₁₁First third order error coefficient alpha₁₃The second order error coefficient alpha₂₁And a second third order error coefficient alpha₂₃(ii) a An output signal modification subunit having an input connected to the output of the error coefficient calculation subunit and configured to calculate the modified first back-end output signal R from the input signal of the post-processing unit and the output signal of the error coefficient calculation subunit_n1[n]|_correctedThe corrected second rear-end output signal R_n2[n]|_correctedAnd the calibrated output signal Do [ n ]]。

Further, the first intermediate value operator unit calculates the first intermediate value temp according to the following formula,

$\mathrm{temp}=\mathrm{mean}(\left(R_{n1}\right[n]+R_{n2}[n\left]\right)\·P_{n1}[n\left]\right)=\left\{\begin{array}{c}\mathrm{temp}00;\left(\mathrm{Ctrl}\right[1:0]=00)\\ \mathrm{temp}01;\left(\mathrm{Ctrl}\right[1:0]=01)\\ \mathrm{temp}10;\left(\mathrm{Ctrl}\right[1:0]=10)\\ \mathrm{temp}11;\left(\mathrm{Ctrl}\right[1:0]=11)\end{array}\right.,$

the second intermediate value operator unit calculates the second intermediate value nn according to the following formula,

$\mathrm{nn}=\mathrm{mean}\left({\left(R_{n1}\right[n]+P_{n1}[n\left]\right)}^2\right)=\left\{\begin{array}{c}\mathrm{nn}00;\left(\mathrm{Ctrl}\right[1:0]=00)\\ \mathrm{nn}01;\left(\mathrm{Ctrl}\right[1:0]=01)\\ \mathrm{nn}10;\left(\mathrm{Ctrl}\right[1:0]=10)\\ \mathrm{nn}11;\left(\mathrm{Ctrl}\right[1:0]=11)\end{array}\right.,$

where Ctrl [1:0] is a control signal, mean (—) represents the mean value of the content in parentheses within the statistical time, temp00, temp01, temp10, and temp11 represent the values of the four states of the first intermediate value temp, respectively, and nn00, nn01, nn10, and nn11 represent the values of the four states of the second intermediate value nn, respectively.

Further, the error coefficient calculation subunit calculates the first order error coefficient α by solving a linear equation set₁₁First third order error coefficient alpha₁₃The second order error coefficient alpha₂₁And a second third order error coefficient alpha₂₃，

$\left[\begin{array}{cccc}1& 1& k_{11}& k_{11}\\ 1& 1& k_{21}& k_{21}\\ 1& u& k_{31}& k_{32}\\ 1& u& k_{41}& k_{42}\end{array}\right]\·\left[\begin{array}{c}{\mathrm{\α}}_{11}\\ {\mathrm{\α}}_{21}\\ {\mathrm{\α}}_{13}\\ {\mathrm{\α}}_{23}\end{array}\right]=\left[\begin{array}{c}{b}_1\\ b_2\\ b_3\\ b_4\end{array}\right],$

Wherein k is₁₁、k₂₁、k₃₁、k₃₂、k₄₁And k₄₂Respectively calculated according to the following formula,

$\left\{\begin{array}{c}(k_{11}={A_{\mathrm{pn}1}}^2+3\mathrm{nn}00)\\ k_{21}=({A_{\mathrm{pn}2}}^2+3\mathrm{nn}01)\\ k_{31}=({A_{\mathrm{pn}1}}^2+3\mathrm{nn}10)\\ k_{32}=({{u^{3}A}_{\mathrm{pn}1}}^2-3u\·\mathrm{nn}10)\\ k_{41}=({A_{\mathrm{pn}2}}^2+3\mathrm{nn}11)\\ k_{42}=(u^3{A_{\mathrm{pn}2}}^2-3u\·\mathrm{nn}11)\end{array}\right.,$

b₁、b₂、b₃and b₄Respectively calculated according to the following formula,

$\left\{\begin{array}{c}{b}_1=-\frac{\mathrm{temp}00}{{A_{\mathrm{pn}1}}^2}-2\\ b_2=-\frac{\mathrm{temp}01}{{A_{\mathrm{pn}2}}^2}-2\\ b_3=-\frac{\mathrm{temp}10}{{A_{\mathrm{pn}1}}^2}-1-u\\ b_4=-\frac{\mathrm{temp}11}{{A_{\mathrm{pn}2}}^2}-1-u\end{array}\right..$

further, the output signal correction subunit calculates the corrected first back-end output signal R according to the following formula_n1[n]|_correctdAnd a modified second rear-end output signal R_n2[n]|_corrected，

$\left\{\begin{array}{c}{R}_{n1}\left[n\right]{|}_{\mathrm{corrected}}=\frac{R_{n1}\left[n\right]}{1+{\mathrm{\α}}_{11}}-\frac{{\mathrm{\α}}_{13}}{{(1+{\mathrm{\α}}_{11})}^4}{\left(R_{n1}\right[n\left]\right)}^3\\ R_{n2}\left[n\right]{|}_{\mathrm{corrected}}=\frac{R_{n2}\left[n\right]}{1+{\mathrm{\α}}_{21}}-\frac{{\mathrm{\α}}_{23}}{{(1+{\mathrm{\α}}_{21})}^4}{\left(R_{n2}\right[n\left]\right)}^3\end{array}\right..$

Further, the output signal modification subunit calculates the calibrated output signal Do [ n ] according to the following formula,

Do[n]＝V_ADC1[n]-V_ADC2[n]+R_n1[n]|_corrected-R_n2[n]|_corrected+P_n1[n]+P_n2[n]。

further, the first input signal V_in+(nT_s) And a second input signal V_in-(nT_s) Satisfies the following conditions: $V_{\mathrm{in}+}\left({\mathrm{nT}}_s\right)=-V_{\mathrm{in}-}\left({\mathrm{nT}}_s\right)=\frac{1}{2}{V}_{\mathrm{in}}\left({\mathrm{nT}}_s\right),$ wherein,V_in(nT_s) Is the analog input signal of the current pipeline stage.

Further, the first back-end ADC is a first channel of all pipeline stages after the current pipeline stage in cascade, and outputs the first back-end output signal R_n1[n]Linear summation of each digital output signal for all pipeline stages after the current pipeline stage; the second back-end ADC is a second channel of all pipeline stages after the current pipeline stage in cascade connection, and the second back-end output signal R output by the second back-end ADC is_n2[n]A linear summation of each digital output signal for all pipeline stages following the current pipeline stage.

The utility model discloses a pipeline ADC's backstage calibration circuit can calibrate first order and third-order error that the surplus amplifier introduced simultaneously to calibration algorithm's convergence rate has been improved.

Drawings

FIG. 1 is a schematic diagram of a pipelined ADC;

FIG. 2 is a schematic diagram of the structure of each pipeline stage of a prior art pipeline ADC;

fig. 3 is a schematic diagram of an overall structure of a calibration circuit of the pipeline ADC according to the present invention;

fig. 4 is a schematic structural diagram of a random number generation unit of the calibration circuit of the pipeline ADC according to the present invention;

fig. 5 is a schematic structural diagram of a post-processing unit of the calibration circuit of the pipeline ADC according to the present invention;

fig. 6 is a schematic structural diagram of an output signal correction subunit of the post-processing unit of the calibration circuit of the pipeline ADC according to the present invention.

Detailed Description

The background calibration circuit of the pipelined ADC of the present invention is described in further detail below with reference to the accompanying drawings and the detailed description, but is not intended to limit the present invention.

The utility model discloses a backstage calibration circuit of assembly line ADC, it is used for every pipeline ADC's the pipeline level that needs the calibration. For ease of description, the analog input signal of the pipeline stage is denoted as V_in(nT_s) Wherein, T_sN represents the nth sample, which is the inverse of the sampling frequency of the pipelined ADC.

Referring to fig. 3, the utility model discloses a calibration circuit of assembly line ADC includes: the device comprises a random number generation unit, a first channel, a second channel and a post-processing unit.

Referring to fig. 4, the random number generation unit includes: a random number generation subunit outputting a random signal Pn [ n ] with an average value of 0 and values of 1 and-1](ii) a An amplifier sub-unit for amplifying the random signal Pn [ n ]]Amplifying with an amplification factor of A_pn1、A_pn2And u, wherein A_pn1、A_pn2And u are three constants, respectively; a gating subunit for gating the output of the amplifying subunit, which comprises a gate coupled to the control signal Ctrl [1:0]]The control signal Ctrl [1:0]]Has four states, namely four values, 00, 01, 10 and 11, the gating subunit is configured when Ctrl [1:0]]P of 00 hours output_n1[n]Is A_pn1·P_n[n]、P_n2[n]Is A_pn1·P_n[n]When Ctrl [1:0]]P output when 01_n1[n]Is P_n2·Pn[n]、P_n2[n]Is A_pn2·P_n[n]When Ctrl [1:0]]P of 10 hours output_n1[n]Is A_pn1·P_n[n]、P_n2[n]Is u.A_pn1·P_n[n]When Ctrl [1:0]]P of output at 11_n1[n]Is A_pn2·P_n[n]、P_n2[n]Is u.A_pn2·P_n[n]。

Referring to fig. 3, the first channel has a structure similar to that of each pipeline stage in the related artThe digital-to-analog converter comprises a first sub-ADC, a first sub-DAC, a first subtracter and a first residue amplifier which are connected in sequence. The input signal of the first channel is a first input signal V_in+(nT_s) Whereinin particular, the first channel further comprises a first adder connected between the first sub-ADC and the first sub-DAC, the first adder quantizing the first digital output signal V by the first sub-ADC_ADC1[n]And a first random number P_n1[n]And the sum is transmitted to the first sub-DAC.

The second channel has the same structure as the first channel, and comprises a second sub-ADC, a second sub-DAC, a second subtractor and a second residue amplifier which are connected in sequence. The input signal of the second channel is a second input signal V_in-(nT_s) Whereinin particular, the second channel further comprises a second adder connected between the second sub-ADC and the second sub-DAC, the second adder quantizing the second digital output signal V by the second sub-ADC_ADC2[n]And a second random number P_n2[n]And the sum is transmitted to a second sub-DAC.

The first back-end ADC connected after the first channel refers to the cascade connection of the first channels of all pipeline stages after the current pipeline stage in the pipeline ADC. The output signal of the first channel, i.e. the first residual output signal V_R1(nT_s) Transmitted to the first back-end ADC to obtain a first back-end output signal R_n1[n]. Wherein a first rear-end output signal R is obtained_n1[n]Is the linear summation of each digital output signal output by the first channels of all pipeline stages following the current pipeline stage. For example, if the current pipeline stage is stage 3, and all subsequent pipeline stages are stages 4, 5 and 6, respectively, the first back-end ADC at this time refers to the cascade connection of the first channels of the pipeline stages 4, 5 and 6, and the first back-end ADC outputs a first back-end output signal R_n1[n]Can be expressed as:

R_n1[n]＝K₄·V_ADC1，4[n]+K₅·V_ADC1，5[n]+K₆·V_R，6[n]equation 0

Wherein, V_ADC1，4[n]、V_ADC1，5[n]、V_R，6[n]Digital output signals, K, representing outputs of the first channels of the 4 th, 5 th and 6 th pipeline stages, respectively₄、K₅、K₆Respectively, representing their weighting coefficients.

Similarly, the second back-end ADC connected after the second channel refers to the cascade connection of the second channels of all pipeline stages after the current pipeline stage in the pipeline ADC. The output signal of the second channel, i.e. the second residual output signal V_R2(nT_s) Transmitted to a second back-end ADC to obtain a second back-end output signal R_n2[n]. Wherein a second rear-end output signal R is obtained_n2[n]Is the linear summation of each digital output signal output by the second channels of all pipeline stages following the current pipeline stage.

The post-processing unit is configured to output a first digital output signal V_ADC1[n]And a second digital output signal V_ADC2[n]A first random number P_n1[n]And a second random number P_n2[n]A first rear-end output signal R_n1[n]And a second back-end output signal R_n2[n]Obtaining the calibrated output signal Do [ n ]]。

Referring to fig. 5, the post-processing unit includes: a first intermediate value calculation operator unit for calculating the first intermediate value temp, a second intermediate value calculation operator unit for calculating the second intermediate value nn, as well as an error coefficient calculation subunit and an output signal correction subunit.

Wherein the first intermediate value operator unit comprises: a first arithmetic module for calculating (R)_n1[n]+R_n2[n])·P_n1[n]And a first mean module for calculating the (R) over statistical time_n1[n]+R_n2[n])·P_n1[n]Is measured.The second intermediate value operator unit includes: a second arithmetic module for calculating (R)_n1[n]+P_n1[n])²And a second averaging module for calculating (R) over statistical time_n1[n]+P_n1[n])²Is measured.

An error coefficient calculation subunit configured to calculate the first order error coefficient α₁₁First third order error coefficient alpha₁₃The second order error coefficient alpha₂₁And a second third order error coefficient alpha₂₃. The realization principle is that each error coefficient alpha is obtained by solving a linear equation set represented by the following formula 1₁₁、α₂₁、α₁₃、α₂₃。

$\left[\begin{array}{cccc}1& 1& k_{11}& k_{11}\\ 1& 1& k_{21}& k_{21}\\ 1& u& k_{31}& k_{32}\\ 1& u& k_{41}& k_{42}\end{array}\right]\·\left[\begin{array}{c}{\mathrm{\α}}_{11}\\ {\mathrm{\α}}_{21}\\ {\mathrm{\α}}_{13}\\ {\mathrm{\α}}_{23}\end{array}\right]=\left[\begin{array}{c}{b}_1\\ b_2\\ b_3\\ b_4\end{array}\right]$ Equation 1

Equation 1 above can be simplified as equation 2:

k α ═ b formula 2

Wherein,

$K=\left[\begin{array}{cccc}1& 1& k_{11}& k_{11}\\ 1& 1& k_{21}& k_{21}\\ 1& u& k_{31}& k_{32}\\ 1& u& k_{41}& k_{42}\end{array}\right]$ equation 3

$\mathrm{\α}=\left[\begin{array}{c}{\mathrm{\α}}_{11}\\ {\mathrm{\α}}_{21}\\ {\mathrm{\α}}_{13}\\ {\mathrm{\α}}_{23}\end{array}\right]$ Equation 4

$b=\left[\begin{array}{c}{b}_1\\ b_2\\ b_3\\ b_4\end{array}\right]$ Equation 5

According to equation 2, each error coefficient α is obtained₁₁、α₂₁、α₁₃、α₂₃Then, alpha can be obtained according to the following formula,

$\mathrm{\α}=K^{-1}\·b=\frac{K^{*}}{\left|K\right|}\·b$ equation 6

Wherein, K^*An adjoint matrix representing K, | K | represents a determinant of K, which may be derived using the lebeniz equation, or may be derived recursively from matrix determinants of lower order using laplace expansion.

To sum up, each error coefficient α₁₁、α₂₁、α₁₃、α₂₃The calculation of (a) can be finally decomposed into various combinations of addition, multiplication, and division. Therefore, the error coefficient calculation subunit can be realized by various combinations of a plurality of adders, multipliers and dividers, and finally, each error coefficient α is obtained₁₁、α₂₁、α₁₃、α₂₃。

Specifically, in formula 1, k₁₁、k₂₁、k₃₁、k₃₂、k₄₁And k₄₂Calculated according to the following formula,

$\left\{\begin{array}{c}(k_{11}={A_{\mathrm{pn}1}}^2+3\mathrm{nn}00)\\ k_{21}=({A_{\mathrm{pn}2}}^2+3\mathrm{nn}01)\\ k_{31}=({A_{\mathrm{pn}1}}^2+3\mathrm{nn}10)\\ k_{32}=({{u^{3}A}_{\mathrm{pn}1}}^2-3u\·\mathrm{nn}10)\\ k_{41}=({A_{\mathrm{pn}2}}^2+3\mathrm{nn}11)\\ k_{42}=(u^3{A_{\mathrm{pn}2}}^2-3u\·\mathrm{nn}11)\end{array}\right.$ equation 7

b₁、b₂、b₃And b₄Calculated according to the following formula,

$\left\{\begin{array}{c}{b}_1=-\frac{\mathrm{temp}00}{{A_{\mathrm{pn}1}}^2}-2\\ b_2=-\frac{\mathrm{temp}01}{{A_{\mathrm{pn}2}}^2}-2\\ b_3=-\frac{\mathrm{temp}10}{{A_{\mathrm{pn}1}}^2}-1-u\\ b_4=-\frac{\mathrm{temp}11}{{A_{\mathrm{pn}2}}^2}-1-u\end{array}\right.$ equation 8

Where temp00, temp01, temp10 and temp11 respectively represent the values of the four states of the first intermediate value temp, and nn00, nn01, nn10 and nn11 respectively represent the values of the four states of the second intermediate value nn.

An output signal modification subunit for calculating a modified first rear-end output signal R_n1[n]|_correctedCorrected second rear end output signal R_n2[n]|_correctedAnd the calibrated output signal Do [ n ]]. Referring to fig. 6, the output signal modification subunit includes a third arithmetic module and a plurality of multipliers, adders, and the like. A third arithmetic unit for calculating From this description, the skilled person can deduce the implementation of the third arithmetic module, i.e. with the respective arithmetic module/unit, which need not necessarily be implemented in software.

The operation principle of the calibration circuit of the pipelined ADC of the present invention will be described with reference to fig. 3 to 6.

First input signal V_in+(nT_s) And a second input signal V_in-(nT_s) Input signal V of a pipeline stage forming a pipeline ADC_in(nT_s) Wherein

$V_{\mathrm{in}+}\left({\mathrm{nT}}_s\right)=-V_{\mathrm{in}-}\left({\mathrm{nT}}_s\right)=\frac{1}{2}{V}_{\mathrm{in}}\left({\mathrm{nT}}_s\right)$ equation 9

First digital output signal V_ADC1[n]And a second digital output signal V_ADC2[n]The relationship with the input signal is as follows:

V_in+(nT_s)＝V_ADC1[n]-e_ADC1[n]equation 10

V_in-(nT_s)＝V_ADC2[n]-e_ADC2[n]Equation 11

Wherein e is_ADC1[n]And e_ADC2[n]Respectively representing quantization errors of the first sub-ADC and the second sub-ADC. Due to the relation between the two input signals being V_in+(nT_s)＝-V_in-(nT_s) And therefore, the first and second electrodes are,

e_ADC1[n]＝-e_ADC2[n]equation 12

V_ADC1[n]＝-V_ADC2[n]Equation 13

The inputs V of the first and second residue amplifiers_res1(nT_s) And V_res2(nT_s) Can be respectively expressed as:

V_res1(nT_s)＝-e_ADC1[n]-P_n1[n]equation 14

V_res2(nT_s)＝e_ADC1[n]-P_n2[n]Equation 15

Due to each pipeline stage of the pipeline ADC, the influence of the error on the overall performance of the ADC is reduced in sequence from the front stage to the rear stage. For example, if there are six pipeline stages, the error of the 1 st pipeline stage has the largest influence on the overall performance of the ADC, and the error of the 2 nd pipeline stage has the smallest influence on the overall performance of the ADC. In general, the influence of the error of the last stage Flash ADC on the overall performance of the ADC is negligibly small. In the error calibration process of the whole pipeline ADC, each pipeline stage to be calibrated is calibrated step by step according to the sequence from the later stage to the former stage. For example, the influence of the error of the 6 th-stage Flash ADC on the overall performance of the ADC is small and can be ignored, the pipeline stage to be calibrated is the 1 st-5 th-stage pipeline stage, the pipeline stage 5 is calibrated first, and the 6 th stage is used as the back-end ADC; after the 5 th pipeline stage is calibrated, the 4 th pipeline stage is calibrated, and at the moment, errors of the 5 th to 6 th pipeline stages can be ignored and are jointly used as a rear-end ADC of the current pipeline stage; and after the 4 th pipeline stage is calibrated, the 3 rd pipeline stage is calibrated, and the like, so that the error calibration process of the whole pipeline ADC is completed.

Thus, the quantization error of the back-end ADC is always negligible, and the first and second back-end output signals R_n1[n]And R_n2[n]Can be expressed as:

R_n1[n]＝V_res1(nT_S)+α₁₁V_res1(nT_S)+α₁₃V_res1 ³(nT_S) Equation 16

R_n2[n]＝V_res2(nT_S)+α₂₁V_res2(nT_S)+α₂₃V_res2 ³(nT_S) Equation 17

α_ijAnd j order error coefficients of an ith residue amplifier are represented, wherein i is 1,2, and j is 1 and 3. I.e. alpha₁₁、α₁₃Respectively representing the first and third order error coefficients, alpha, of the first residue amplifier₂₁、α₂₃Respectively representing the first and third order error coefficients of the second residue amplifier. Since the two residue amplifiers are identical, there is,

α₁₁≈α₂₁equation 18

α₁₃≈α₂₃Equation 19

Referring to fig. 4, a first random number P_n1[n]And a second random number P_n2[n]And a random signal Pn [ n ]]The relationship of (c) can be expressed as:

$P_{n1}\left[n\right]=\left\{\begin{array}{c}{A}_{\mathrm{pn}1}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=00)\\ A_{\mathrm{pn}2}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=01)\\ A_{\mathrm{pn}1}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=10)\\ A_{\mathrm{pn}2}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=11)\end{array}\right.$ equation 20

$P_{n2}\left[n\right]=\left\{\begin{array}{c}{A}_{\mathrm{pn}1}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=00)\\ A_{\mathrm{pn}2}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=01)\\ {u\·A}_{\mathrm{pn}1}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=10)\\ {u\·A}_{\mathrm{pn}2}\·P_n\left[n\right];\left(\mathrm{Ctrl}\right[1:0]=11)\end{array}\right.$ Equation 21

Wherein Ctrl [1:0]]For the control signal, a random signal Pn]Has a mean value of 0 and values of 1 and-1, A_pn1、A_pn2And u are three constants, respectively.

The principle of the first and second intermediate value calculating subunit is described below with reference to fig. 5.

The output signal of the first arithmetic module is P_n1[n]·(R_n1[n]+R_n2[n]) The output of the first mean module, i.e. the output temp of the first intermediate value calculating operator unit, may be expressed as:

$\mathrm{temp}=\frac{1}{N}{\mathrm{\Σ}}_{n=1}^N\left(R_{n1}\right[n]+R_{n2}[n\left]\right)\·P_{n1}\left[n\right]$ equation 22

The output signal of the second arithmetic module is (R)_n1[n]+P_n1[n])²The output of the second mean module, i.e. the output nn of the second intermediate value calculating operator unit, can be expressed as:

$\mathrm{nn}=\frac{1}{N}{\mathrm{\Σ}}_{n=1}^N{\left(R_{n1}\right[n]+P_{n1}[n\left]\right)}^2$ equation 23

Combining equations 16, 17, R_n1[n]+R_n2[n]Can be expressed as:

$\begin{array}{c}{R}_{n1}\left[n\right]+R_{n2}\left[n\right]\\ =[V_{\mathrm{res}1}\left({\mathrm{nT}}_S\right)+V_{\mathrm{res}2}\left({\mathrm{nT}}_S\right)]+[{\mathrm{\α}}_{11}{V}_{\mathrm{resl}}\left({\mathrm{nT}}_S\right)\\ +{\mathrm{\α}}_{21}{V}_{\mathrm{res}2}\left({\mathrm{nT}}_S\right)]+[{\mathrm{\α}}_{13}{V_{\mathrm{res}1}}^3\left({\mathrm{nT}}_S\right)+{\mathrm{\α}}_{23}{V_{\mathrm{res}2}}^3\left({\mathrm{nT}}_S\right)]\end{array}$

in combination with equations 14, 15, 18, and 19, there are:

$\begin{array}{c}{R}_{n1}\left[n\right]+R_{n2}\left[n\right]\\ \≈-\left(P_{n1}\right[n]+P_{n2}[n\left]\right)-\left({\mathrm{\α}}_{11}{P}_{n1}\right[n]+{\mathrm{\α}}_{21}{P}_{n2}[n\left]\right)\\ -{\mathrm{\α}}_{13}(P_{n1}{\left[n\right]}^3+3e_{\mathrm{ADC}1}{\left[n\right]}^3{P}_{n1}[n\left]\right)\\ -{\mathrm{\α}}_{23}(P_{n2}{\left[n\right]}^3+3e_{\mathrm{ADC}1}{\left[n\right]}^2{P}_{n2}[n\left]\right)\end{array}$

equation 24

Since the output of the control signals Ctrl [1:0] can be expressed as:

$\mathrm{Ctrl}[1:0]=\left\{\begin{array}{c}00,(1\≤k\≤N)\\ 01,(N+1\≤k\≤2N)\\ 10,(2N+1\≤k\≤3N)\\ 11,(3N+1\≤k\≤4N)\end{array}\right.$ equation 25

Where k represents the kth sample and N represents the number of samples for which each state of the control signal Ctrl [1:0] lasts.

Thus, when Ctrl [1:0]At 00, averger 0 block in the first averaging block is enabled, its output temp is the first state temp 00. And due to the existence of P_n1[n]＝A_pn1P_n[n]＝P_n2[n]、P_n[n]²If equation 24 is substituted into equation 22, the first state temp00 of the first intermediate value temp can be expressed as:

$\begin{array}{c}\mathrm{temp}00=-{A_{\mathrm{pn}1}}^2\{2+({\mathrm{\α}}_{11}+{\mathrm{\α}}_{21})+({A_{\mathrm{pn}1}}^2+3\stackrel{\‾}{e_{{\mathrm{ADC}1}_1}{\left[n\right]}^2})\\ \·({\mathrm{\α}}_{13}+{\mathrm{\α}}_{23})\}\end{array}$

equation 26

The first state nn00 for the second intermediate value nn according to equation 23 is:

$\mathrm{nn}00=\frac{1}{N}{\mathrm{\Σ}}_{n=1}^N{\left(R_{n1}\right[n]+P_{n1}[n\left]\right)}^2\≈\stackrel{\‾}{e_{\mathrm{ADC}1\_1}{\left[n\right]}^2}$ equation 27

Wherein e is_{ADC1_1}[n]Expressed as control signals Ctrl [1:0]]The quantization error of the first channel in the first state, when equation 27 is substituted into equation 26, has:

temp00＝-A_pn1 ²{2+(α₁₁+α₂₁)+(A_pn1 ²+3nn00)·(α₁₃+α₂₃）}

equation 28

Similarly, when Ctrl [1: when 0 ═ 01, the first intermediate value temp may be expressed as:

temp01＝-A_pn2 ²{2+(α₁₁+α₂₁)+(A_pn2 ²+3nn01)·(α₁₃+α₂₃)}

equation 29

When Ctrl [1: when 0 ═ 10, the first intermediate value temp may be expressed as:

$\begin{array}{c}\mathrm{temp}10=-{A_{\mathrm{pn}1}}^2\{1+u+({\mathrm{\α}}_{11}+{\mathrm{u\α}}_{21})+{\mathrm{\α}}_{13}({A_{\mathrm{pn}1}}^2+3\mathrm{nn}10)\\ +{\mathrm{\α}}_{23}(u^3{A_{\mathrm{pn}1}}^2-3u\·\mathrm{nn}10)\}\end{array}$

equation 30

When Ctrl [1: when 0 ═ 11, the first intermediate value temp may be expressed as:

$\begin{array}{c}\mathrm{temp}11=-{A_{\mathrm{pn}2}}^2\{1+u+({\mathrm{\α}}_{11}+{\mathrm{u\α}}_{21})+{\mathrm{\α}}_{13}({A_{\mathrm{pn}2}}^2+3\mathrm{nn}11)\\ +{\mathrm{\α}}_{23}(u^3{A_{\mathrm{pn}2}}^2-3u\·\mathrm{nn}11)\}\end{array}$

equation 31

To simplify the expression, let k₁₁、k₂₁、k₃₁、k₃₂、k₄₁And k₄₂Are respectively expressed as the value of formula 7, and let b₁、b₂、b₃And b₄Representing the values of equation 8, respectively, equations 28, 29, 30, 31 can be simplified as:

$\left\{\begin{array}{c}{b}_1=({\mathrm{\α}}_{11}+{\mathrm{\α}}_{21})+k_{11}({\mathrm{\α}}_{13}+{\mathrm{\α}}_{23})\\ b_2=({\mathrm{\α}}_{11}+{\mathrm{\α}}_{21})+k_{21}({\mathrm{\α}}_{13}+{\mathrm{\α}}_{23})\\ b_3=({\mathrm{\α}}_{11}+u\·{\mathrm{\α}}_{21})+k_{31}\·{\mathrm{\α}}_{13}+k_{32}\·{\mathrm{\α}}_{23}\\ b_4=({\mathrm{\α}}_{11}+u\·{\mathrm{\α}}_{21})+k_{41}\·{\mathrm{\α}}_{13}+k_{42}\·{\mathrm{\α}}_{23}\end{array}\right.$ equation 32

It can be further simplified to be expressed as formula 1 and formula 2. Thus, the error coefficient α of the first and second channels can be obtained by solving the linear equation system of equation 1 (i.e., equation 32)₁₁、α₂₁、α₁₃、α₂₃。

Referring to fig. 5, the error coefficient calculation subunit calculates the error coefficient in the control signal Ctrl [1:0]When the value is 11, the error coefficient alpha is calculated according to the method of solving the linear equation system according to the input first intermediate value temp and the second intermediate value nn₁₁、α₂₁、α₁₃、α₂₃。

Referring to fig. 6, according to the error coefficient α₁₁、α₂₁、α₁₃、α₂₃And a first and a second back-end output signal R_n1[n]And R_n2[n]The modified first and second back-end output signals R may be calculated_n1[n]|_correctedAnd R_n2[n]|_corrected：

$R_{n1}\left[n\right]{|}_{\mathrm{corrected}}=\frac{R_{n1}\left[n\right]}{1+{\mathrm{\α}}_{11}}-\frac{{\mathrm{\α}}_{13}}{{(1+{\mathrm{\α}}_{11})}^4}{\left(R_{n1}\right[n\left]\right)}^3\≈V_{\mathrm{res}1}\left[{\mathrm{nT}}_S\right]$ Equation 33

$R_{n2}\left[n\right]{|}_{\mathrm{corrected}}=\frac{R_{n2}\left[n\right]}{1+{\mathrm{\α}}_{21}}-\frac{{\mathrm{\α}}_{23}}{{(1+{\mathrm{\α}}_{21})}^4}{\left(R_{n2}\right[n\left]\right)}^3\≈V_{\mathrm{res}2}\left[{\mathrm{nT}}_S\right]$ Equation 34

The following can be obtained:

V_out[n]＝R_n1[n]|_corrected-R_n2[n]|_corrected+P_n1[n]+P_n2[n]＝-2e_ADC1[n]

equation 35

Therefore, the output signal Do [ n ] after the pipeline stage calibration is:

$\begin{array}{c}\mathrm{Do}\left[n\right]=V_{\mathrm{out}}\left[n\right]+V_{\mathrm{ADC}1}\left[n\right]-V_{\mathrm{ADC}2}\left[n\right]\\ =-2e_{\mathrm{ADC}1}\left[n\right]+V_{\mathrm{ADC}1}\left[n\right]+V_{\mathrm{ADC}1}\left[n\right]\\ =2\left(V_{\mathrm{ADC}1}\right[n]-e_{\mathrm{ADC}1}[n\left]\right)=V_{\mathrm{in}}\left({\mathrm{nT}}_s\right)\end{array}$

equation 36

According to formula 36, the output signal Do [ n ] after the calibration of the calibration circuit of the pipeline ADC of the present invention eliminates the first-order and third-order errors introduced due to the insufficient gain of the operational amplifier and the mismatch of the front-end capacitor, and can realize the calibration.

On the basis of the above principle, the following detailed description illustrates the working method of the background calibration circuit of the pipeline ADC of the present invention, which includes the following steps:

step S0: a first input signal V_in+(nT_s) And a second input signal V_in-(nT_s) Respectively input into a first and a second channel, wherein in the first channel a first digital output signal V is output_ADC1[n]And a first random number P_n1[n]After addition, the second digital output signal V is input to the first sub-DAC and is output in the second channel_ADC2[n]And a second random number P_n2[n]And the sum is input to a second sub-DAC.

Step S1: a first residual output signal V output by the first residual amplifier_R1（nT_s) Output to a first back-end ADC to obtain a first back-end output signal R_n1[n](ii) a And a second residual output signal V outputted from the second residual amplifier_R2(nT_s) Output to a second back-end ADC to obtain a second back-end output signalR_n2[n]。

Step S2: the first digital output signal V_ADC1[n]A second digital output signal V_ADC2[n]A first random number P_n1[n]A second random number P_n2[n]A first rear-end output signal R_n1[n]A second rear-end output signal R_n2[n]Performing a post-processing procedure to obtain a calibrated output signal Do [ n ]]。

The post-processing procedure in step S2 includes:

step S21: calculating a second intermediate value nn according to equation 23 and a first intermediate value temp according to equations 28, 29, 30, 31; k is calculated according to the formulas 7 and 8 respectively₁₁、k₂₁、k₃₁、k₃₂、k₄₁、k₄₂And b₁、b₂、b₃、b₄。

Step S22: solving the system of linear equations of equation 1 (i.e., equation 32) to obtain the error coefficient α for the first and second channels₁₁、α₂₁、α₁₃、α₂₃(ii) a The modified first back-end output signal R is obtained according to equations 33 and 34_n1[n]|_correctedAnd a modified second rear-end output signal R_n2[n]|_corrected(ii) a Finally, the calibrated output signal Do [ n ] is obtained according to the following formula]：

$\begin{array}{c}\mathrm{Do}\left[n\right]=V_{\mathrm{ADC}1}\left[n\right]-V_{\mathrm{ADC}2}\left[n\right]+R_{n1}\left[n\right]{|}_{\mathrm{corrected}}-R_{n2}\left[n\right]{|}_{\mathrm{corrected}}\\ +P_{n1}\left[n\right]+P_{n2}\left[n\right]\end{array}$

Equation 37

Referring to the foregoing principle, it can be known to apply the utility model discloses a calibration circuit can calibrate operational amplifier's first order and third-order error.

And simultaneously, use the utility model discloses a calibration method that backstage calibration circuit realized is fast than prior art's calibration method's convergence rate. For example, when calibration is performed using conventional calibration methods, at least 2 is generally required²⁵The data can converge after one clock cycle (i.e., 33554432 clock cycles), i.e., one calibration can be completed. However, use the utility model discloses a calibration electricityThe calibration method for realizing the road only needs 2¹⁵The data can converge for one clock cycle (i.e., 32768 clock cycles). It can be seen that, the utility model discloses a pipeline ADC's backstage calibration circuit can improve calibration algorithm's convergence rate effectively, can accomplish the calibration to operational amplifier's first order and third-order error fast promptly.

The above embodiments are only exemplary embodiments of the present invention, and should not be used to limit the present invention, the scope of the present invention is defined by the appended claims. Various modifications and equivalents of the invention can be made by those skilled in the art within the spirit and scope of the invention, and these modifications and equivalents should also be considered as falling within the scope of the invention.

Claims (9)

1. A background calibration circuit of a pipeline ADC is used for each pipeline stage of the pipeline ADC needing calibration, and is characterized by comprising a random number generation unit, a first channel, a second channel and a post-processing unit,

the random number generation unit has a function of outputting a first random number P_n1[n]And outputs a second random number P_n2[n]A second output terminal of (1);

the first channel comprises a first sub-ADC, a first sub-DAC, a first subtracter and a first residue amplifier which are connected in sequence,

the input end of the first sub-ADC is connected with a first input signal V_in+(nT_s)，

The first channel further comprises a first adder having a first input connected to the output of the first sub-ADC for receiving a first digital output signal V_ADC1[n]A second input terminal thereof connected to a first output terminal of the random number generation unit, an output terminal thereof connected to an input terminal of the first sub-DAC,

the output end of the first residue amplifier is connected to the input end of the first rear-end ADC, and the output end of the first rear-end ADC outputs a first rear-end output signal R_n1[n]And connected to the post-processing unit;

the second channel comprises a second sub-ADC, a second sub-DAC, a second subtracter and a second residue amplifier which are connected in sequence,

the input end of the second sub-ADC is connected with a second input signal V_in-(nT_s)，

The second channel further comprises a second adder having a first input connected to the output of the second sub-ADC for receiving a second digital output signal V_ADC2[n]A second input terminal thereof is connected to the second output terminal of the random number generation unit, and an output terminal thereof is connected to the input terminal of the second sub-DAC;

the output end of the second residue amplifier is connected to the input end of a second rear-end ADC (analog to digital converter), and the output end of the second rear-end ADC outputs a first rear-end output signal R_n1[n]And connected to the post-processing unit;

the post-processing unit is configured to output a first digital output signal V according to the first digital output signal_ADC1[n]And a second digital output signal V_ADC2[n]The first random number P_n1[n]And a second random number P_n2[n]The first rear end output signal R_n1[n]And a second back-end output signal R_n2[n]Obtaining the calibrated output signal Do [ n ]]。

2. The background calibration circuit of the pipeline ADC of claim 1, wherein the random number generation unit comprises a random number generation subunit, an amplification subunit and a gating subunit which are connected in sequence:

the random number generation subunit outputs a random signal Pn [ n ] with an average value of 0 and values of 1 and-1;

the amplification subunit pairs the random signal Pn [ n]Amplifying with an amplification factor of A_pn1、A_pn2And u;

the gating subunit gates the output of the amplifying subunit, and includes a first control end connected to a control signal Ctrl [1:0], the gating subcell is configured to,

when the control signal Ctrl [1:0]When the first state is reached, the first random number P is output_n1[n]Is A_pn1·P_n[n]Said second random number P_n2[n]Is A_pn1·P_n[n]，

When the control signal Ctrl [1:0]When the first random number is in the second state, the first random number P is output_n1[n]Is A_pn2·P_n[n]Said second random number P_n2[n]Is A_pn2·P_n[n]，

When the control signal Ctrl [1:0]The first random number P is output when the state is the third state_n1[n]Is A_pn1·P_n[n]Said second random number P_n2[n]Is u.A_pn1·P_n[n]，

When the control signal Ctrl [1:0]The first random number P is output when the state is the fourth state_n1[n]Is A_pn2·P_n[n]Said second random number P_n2[n]Is u.A_pn2·P_n[n]。

3. A background calibration circuit for a pipelined ADC as recited in claim 2, wherein the post-processing unit comprises:

a first intermediate value operator unit configured to calculate the first intermediate value temp, comprising:

a first arithmetic module for calculating (R)_n1[n]+R_n2[n])·Pn₁[n]And, in addition,

a first mean module for calculating a statistical time horizon (R)_n1[n]+R_n2[n])·Pn₁[n]The mean value of (a);

a second intermediate value operator unit configured to calculate the second intermediate value nn, comprising:

a second arithmetic module for calculating (R)_n1[n]+P_n1[n])²And, in addition,

a second mean module for calculating a statistical time horizon (R)_n1[n]+P_n1[n])²The mean value of (a);

an error coefficient calculation subunit having inputs connected to outputs of said first and second intermediate value calculation subunit, respectively, and being configured to calculate said first order error coefficient α based on said first intermediate value temp and said second intermediate value nn₁₁First third order error coefficient alpha₁₃The second order error coefficient alpha₂₁And a second third order error coefficient alpha₂₃；

An output signal modification subunit having an input connected to the output of the error coefficient calculation subunit and configured to calculate the modified first back-end output signal R from the input signal of the post-processing unit and the output signal of the error coefficient calculation subunit_n1[n]|_correctedThe corrected second rear-end output signal R_n2[n]|_correctedAnd the calibrated output signal Do [ n ]]。

4. Background calibration circuit for a pipelined ADC according to claim 3, wherein the first intermediate value operator unit calculates the first intermediate value temp according to the formula,

$\mathrm{temp}=\mathrm{mean}(\left(R_{n1}\right[n]+R_{n2}[n\left]\right)\·p_{n1}[n\left]\right)=\left\{\begin{array}{c}\mathrm{temp}00;\left(\mathrm{Ctrl}\right[1:0]=00)\\ \mathrm{temp}01;\left(\mathrm{Ctrl}\right[1:0]=01)\\ \mathrm{temp}10;\left(\mathrm{Ctrl}\right[1:0]=10)\\ \mathrm{temp}11;\left(\mathrm{Ctrl}\right[1:0]=11)\end{array}\right.,$

the second intermediate value operator unit calculates the second intermediate value nn according to the following formula,

$\mathrm{nn}=\mathrm{mean}\left({\left(R_{n1}\right[n]+P_{n1}[n\left]\right)}^2\right)=\left\{\begin{array}{c}\mathrm{nn}00;\left(\mathrm{Ctrl}\right[1:0]=00)\\ \mathrm{nn}01;\left(\mathrm{Ctrl}\right[1:0]=01)\\ \mathrm{nn}10;\left(\mathrm{ctrl}\right[1:0]=10)\\ \mathrm{nn}11;\left(\mathrm{Ctrl}\right[1:0]=11)\end{array}\right.,$

wherein Ctrl [1:0] is a control signal, mean denotes the mean value of the content in parentheses within the statistical time, temp00, temp01, temp10 and temp11 denote the values of the four states of the first intermediate value temp, respectively, and nn00, nn01, nn10 and nn11 denote the values of the four states of the second intermediate value nn, respectively.

5. Background calibration circuit for pipelined ADC according to claim 4, wherein said error coefficient calculation subunit calculates said first order error coefficient α by solving a system of linear equations as follows₁₁First third order error coefficient alpha₁₃The second order error coefficient alpha₂₁And a second third order error coefficient alpha₂₃，

$\left[\begin{array}{cccc}1& 1& k_{11}& k_{11}\\ 1& 1& k_{21}& k_{21}\\ 1& u& k_{31}& k_{32}\\ 1& u& k_{41}& k_{42}\end{array}\right]\·\left[\begin{array}{c}{\mathrm{\α}}_{11}\\ {\mathrm{\α}}_{21}\\ {\mathrm{\α}}_{13}\\ {\mathrm{\α}}_{23}\end{array}\right]=\left[\begin{array}{c}{b}_1\\ b_2\\ b_3\\ b_4\end{array}\right],$

Wherein k is₁₁、k₂₁、k₃₁、k₃₂、k₄₁And k₄₂Respectively calculated according to the following formula,

$\left\{\begin{array}{c}{k}_{11}=({A_{\mathrm{pn}1}}^2+3\mathrm{nn}00)\\ k_{21}=({A_{\mathrm{pn}2}}^2+3\mathrm{nn}01)\\ k_{31}=({A_{\mathrm{pn}1}}^2+3\mathrm{nn}10)\\ k_{32}=(u^3{A_{\mathrm{pn}1}}^2-3u\·\mathrm{nn}10)\\ k_{41}=({A_{\mathrm{pn}2}}^2+3\mathrm{nn}11)\\ k_{42}=(u^3{A_{\mathrm{pn}2}}^2-3u\·\mathrm{nn}11)\end{array}\right.,$

b₁、b₂、b₃and b₄Respectively calculated according to the following formula,

$\left\{\begin{array}{c}{b}_1=-\frac{\mathrm{tep}00}{{A_{\mathrm{pn}1}}^2}-2\\ b_2=-\frac{\mathrm{temp}01}{{A_{\mathrm{pn}2}}^2}-2\\ b_3=-\frac{\mathrm{temp}10}{{A_{\mathrm{pn}1}}^2}-1-u\\ b_4=-\frac{\mathrm{temp}11}{{A_{\mathrm{pn}2}}^2}-1-u\end{array}\right.$

6. the background calibration circuit of pipelined ADC of claim 5 wherein said output signal modification subunit calculates a modified first back-end output signal R according to the formula_n1[n]|_correctedAnd a modified second rear-end output signal R_n2[n]|_corrected，

$\left\{\begin{array}{c}{R}_{n1}[n{\left]\right|}_{\mathrm{corrected}}=\frac{R_{n1}\left[n\right]}{1+{\mathrm{\α}}_{11}}-\frac{{\mathrm{\α}}_{13}}{{(1+{\mathrm{\α}}_{11})}^4}{\left(R_{n1}\right[n\left]\right)}^3\\ R_{n2}{\left[n\right]|}_{\mathrm{corrected}}=\frac{R_{n2}\left[n\right]}{1+{\mathrm{\α}}_{21}}-\frac{{\mathrm{\α}}_{23}}{{(1+{\mathrm{\α}}_{21})}^4}{\left(R_{n2}\right[n\left]\right)}^3\end{array}\right..$

7. The background calibration circuit of pipelined ADC of claim 6 wherein said output signal modification subunit calculates said calibrated output signal Do [ n ] according to the formula,

Do[n]＝V_ADC1[n]-V_ADC2[n]+R_n1[n]|_corrected-R_n2[n]|_corrected+P_n1[n]+P_n2[n]。

8. background calibration circuit for a pipelined ADC according to claim 1, wherein the first input signal V_in+(nT_s) And a second input signal V_in-(nT_s) Satisfies the following conditions:

$V_{\mathrm{in}+}\left({\mathrm{nT}}_s\right)=-V_{\mathrm{in}-}\left({\mathrm{nT}}_s\right)=\frac{1}{2}{V}_{\mathrm{in}}\left({\mathrm{nT}}_s\right),$

wherein, V_in(nT_s) Is the analog input signal of the current pipeline stage.

9. The background calibration circuit of pipeline ADC of claim 1, wherein said first back-end ADC is a first channel of all pipeline stages after a current pipeline stage in cascade, and outputs said first back-end output signal R_n1[n]Linear summation of each digital output signal for all pipeline stages after the current pipeline stage; the second back-end ADC is a second channel of all pipeline stages after the current pipeline stage in cascade connection, and the second back-end output signal R output by the second back-end ADC is_n2[n]A linear summation of each digital output signal for all pipeline stages following the current pipeline stage.