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CN1838328A - Method for erasing memory cell on memory array - Google Patents

Method for erasing memory cell on memory array Download PDF

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Publication number
CN1838328A
CN1838328A CNA2006100059960A CN200610005996A CN1838328A CN 1838328 A CN1838328 A CN 1838328A CN A2006100059960 A CNA2006100059960 A CN A2006100059960A CN 200610005996 A CN200610005996 A CN 200610005996A CN 1838328 A CN1838328 A CN 1838328A
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China
Prior art keywords
verification
subgroup
level
unit set
unit
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Pending
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CNA2006100059960A
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Chinese (zh)
Inventor
阿萨夫·沙比尔
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Spansion Israel Ltd
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Spansion Israel Ltd
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Publication of CN1838328A publication Critical patent/CN1838328A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.

Description

The method of erasing memory cell on memory array
Technical field
The present invention relates to the operation to nonvolatile memory (NVM) array memory cells, for example, programme and wipe, particularly minimizing is to the erasing pulse of these arrays with wipe the method for verification operation.
Background technology
At present, the nonvolatile memory product is integrated carries out the ability that electronics is programmed and wiped to storage unit.Mainly show as, erase operation is not to carry out one by one on each unit, but carries out on the subgroup, unit, just as normal execution the during programming operation.This means that to the last the unit of (the slowest) is finished and wiped, erased conditions just puts on whole subgroup, that is, whether verification exceeds predetermined level (wiping verification).
The integrated tunnel that carries out between erasing period strengthens the memory product that hot hole injects, and as in NROM (nitride ROM) technology, requires the high bias voltage of transistor junction with by taking tunnel effect generation filling orifice to, as shown in Figure 1.Must control electric charge and inject guaranteeing suitable operation of equipment, so stepping and checking algorithm often are used.In a typical algorithm, with a specific bias voltage iunjected charge, carry out a verification operation thereafter, whether reach preset state with probe unit.If do not reach preset state, just start stronger electric charge and inject by a higher bias voltage, vice versa.Concerning the tunnel strengthens the hot hole injection, often to carry out this flow process, consequently longer erasing time and lower execution efficient simultaneously respectively on the memory cell two sides.
In the length of life of equipment, particularly passing through intensive circulation (programming and erase operation continuously) afterwards, just should increase in order to the voltage of wiping NROM and similar NROM unit.For example, Fig. 2 is an exemplary embodiments of prior art, before the expression circulation and NROM unit afterwards wipe curve.This curve display the degeneration of erase operation, wherein, each the circulation after, all to apply higher voltage and come erase unit.
Fig. 3 is circulation another embodiment to the adverse effect of erasing voltage.Especially, Fig. 3 expresses in the prior art erasing voltage and the step-by-step counting based on the memory product of NROM, and it is for carrying out the function of program/erase operations (cycle count) quantity on an equipment.Leak and press (Vppd) to increase to a specific voltage value (the maximum permissible voltage 7.1V of specific products as shown in FIG.), simultaneously, number of pulses also increases.After reaching maximum permissible voltage, it is stable that voltage levvl becomes.
Since just set initial erase voltage at the product test initial stage, progressively accumulation in erase operation, and this middle and later periods in the product life cycle just is converted into low efficient.
In the prior art, once proposed and attempted a lot of measures improve with the hole be injected to the basis the efficient of wiping flow process.Wherein a kind of measure applies an extra erasing pulse with a level that is higher than last pulse, to guarantee the wiping raising reliability fully.All mention the method that adopts extra-pulse in a plurality of patent documents, for example, United States Patent (USP) 6700818, U.S. Patent application 20050117395 and 20050058005, the assignee that these patents or application have all transferred the application, the application will be with reference to its content.
Another kind of measure is to adopt big voltage span between two continuous steps.But this method may cause operation controllability to reduce.Also having a kind of measure is to adopt multiple voltage amplification.Inject because often simultaneously carry out electric charge simultaneously on a plurality of unit, the principle of this measure is, can integrated big voltage span arrive its target until first cell assembly, continues and finishes until unit set with a littler voltage span.
Also having a kind of measure is in learning phase, determines a preferential step voltage levvl according to the erase operation of a previous one-element group or same one-element group, and this voltage levvl is applied on the remaining element of array, so that faster.Another kind of measure is that first pulse level when product classification dials.But this measure can not be guaranteed short step-by-step counting time overhead.
Multiple level check is then adopted in another kind of measure.Pulse voltage can be comparatively fast to a final pulse level like this, and still this measure requires more complicated design and longer checking time.Another kind of measure requires when pulse application/verification operation, and carry out alternately on the two sides of unit.This way can make the double raising of efficiency of erasing, but controllability can reduce.
Another kind of measure is adopted the parallel mechanism of wiping that strengthens by reducing energy consumption.Also has a kind of measure, if the failure of abundant cell erasure then stops to wipe verification.Apply after the additional erasing pulse, proceed to wipe verification in the address of losing efficacy for the first time.But in above-mentioned all prior aries, verification must be wiped by several in all unit of wiping among the group, is included in and finishes before the erase operation, the loss of word line expense switching time in parallel.
Summary of the invention
The invention provides and a kind ofly wipe the bit of the storage unit that memory array lists and reduce the erasing pulse of this type of array and wipe the method for verification operation.The present invention will describe in detail hereinafter, it relates to a kind of nvm array storage unit, be particularly related to a kind of single-bit, dibit, many bits and many level NROM unit, wherein erasing move generally includes starting voltage horizontal adjustment to a targets threshold with bit, the invention is not restricted to the NROM array.
In one embodiment, for reducing the overall time of erase operation, need to reduce verification and switching time, but be not limited thereto.By shortening the verification operation between the injected pulse of hole, can reduce and above-mentionedly ask loss when of the prior art, carry out efficient thereby fully improve product.
The method that provides by one embodiment of the present of invention, storage unit on the erasable memory array, this method comprises that all bits to the unit set of memory cell array apply erasing pulse, and only a subgroup of the unit set that is wiped free of is carried out and wipe verification operation, whether be reduced to the starting voltage (Vt) of checking this storage unit and wipe verification (EV) voltage levvl, if, just unit set is stopped erase operation, no matter and whether the remainder of unit set is checked.
By one embodiment of the present of invention, have only the subgroup of unit set to be finished and wipe by verification, this unit set just can have been finished by verification and wipe.
By one embodiment of the present of invention, to this subgroup wipe verification make its level be lower than target to wipe the calibration voltage level lower, to guarantee that the whole unit set still is wiped free of even without whole unit are carried out verification.
By one embodiment of the present of invention, this method can further comprise the verification time overhead is minimized.
By one embodiment of the present of invention, can after extremely a small amount of word line, carry out and wipe verification operation, with further minimizing expense switching time with this subgroup pack.
By an alternative embodiment of the invention, reading level and wiping between the verification level, or read level and wipe verification and programming verification level between, can increase the level difference of a setting.
By an alternative embodiment of the invention, this method can further comprise, applies erasing pulse to two or more subgroups of unit set, but verification operation is not carried out in all subgroups.
By one embodiment of the present of invention, this method can further comprise, guarantees that a certain amount of bit reaches the setting level, and unit set is very high by the probability of wiping verification, and only needs verification is wiped in the actual execution in a subgroup of unit.
By one embodiment of the present of invention, this method can further comprise, finish wipe verification after, apply erasing pulse in addition.
By one embodiment of the present of invention, the subgroup of finishing this unit set of wiping verification can change to another erase operation from an erase operation between any one subgroup of the unit set that comprises unit set itself regularly, periodically or randomly.
Description of drawings
In conjunction with the accompanying drawings and detailed description hereinafter, can understand the present invention better.
Fig. 1 strengthens hot hole by tunnel effect in the prior art to inject the sketch of wiping the NROM unit;
Fig. 2 is that typical NROM unit demonstrates the degeneration of erase operation at the curve of wiping of circulation front and back in the prior art;
Fig. 3 be in the prior art based on the erasing voltage and the step counting sketch of the memory product of NROM, this erasing voltage and step counting are the functions of carrying out the quantity of program/erase operations (cycle count) on device;
Fig. 4 A and 4B are by embodiments of the invention, are partitioned the rough schematic view of the embodiment of the unit set that the memory array of subdivision lists;
Fig. 4 C is according to one embodiment of the present of invention, wipes the simplified flow chart of the method for the bit of storage unit on the array of nonvolatile memory cells;
Fig. 5 is according to one embodiment of the present of invention, the reduced graph that starting voltage distributes on the subgroup of NROM array, and this starting voltage is the function of subgroup scale;
Fig. 6 A is by in the prior art, wipes statistical distribution sketch with the starting voltage of programming unit with classic method;
Fig. 6 B is according to one embodiment of the present of invention, the statistical distribution sketch of the starting voltage of erase unit;
Fig. 7 A is according to one embodiment of the present of invention, is programmed the simplified schematic diagram of the unit set of wiping, and the surplus loss does not cause because of matching between the subgroup of unit set among the figure;
Fig. 7 B is according to one embodiment of the present of invention, the process flow diagram that the surplus that compensation causes because of not matching between the subgroup of unit set is lost;
Fig. 8 is according to one embodiment of the present of invention, the distribution of threshold voltages between two subgroups of the NROM unit that is programmed
The reduced graph of embodiment.
Embodiment
For the unit set subregion has been used some terms, can better understand these terms with reference to Fig. 4 A and 4B, aforementioned two figure are according to one embodiment of the present of invention, the embodiment of the unit set that lists at the memory array that is divided into subdivision.Fig. 4 A is an embodiment of the unit set 10 that lists at the memory array that is divided into subdivision 12 (passing through DQ in this case), with a subgroup 14 that will be wiped free of verification (rather than to whole unit set), comprise the unit on all subdivisions 12, hereinafter will describe in detail this.Subdivision 12 and subgroup 14 can be any form.Fig. 4 B divides unit set 10 into subdivision.In this example, divide unit set 10 into subelement 16 by word line.
With reference to figure 4C, this figure is according to one embodiment of the present of invention, wipes the method for the bit of storage unit on the array of nonvolatile memory cells.
Can select an erasing pulse to come the bit of erase unit, comprise negative grid voltage of selection (dialling in) (Vg or Vcvpn-are from the voltage of charge drive) and a positive leakage pressure (Vppd) (step 401).The typical range of magnitude of voltage is as follows, and Vg is from-3V to-7V, and Vppd but is not limited thereto from 3V to 7V, and its duration is the 100-1000 microsecond.Then can to unit set apply erasing pulse (step 402) thereafter.
By one embodiment of the present of invention, not to the whole unit set, but verification operation (step 403) is wiped in a subgroup that is wiped free of of unit set.Check whether storage unit starting voltage (Vt) is lower than and wipe verification (EV) voltage levvl by wiping verification operation.The subgroup of this unit set can comprise the unit in all subdivisions of storage unit set on typical meaning, it defines by application architecture, for example is connected to the physical array section of different sensor amplifier (with reference to subdivision DQ).
If the unit set that is wiped free of by the subdivision unit on the subgroup of verification all not by wiping verification, just set a new Vppd level (dialling in) (step 404) by strong (for example, a big) increment.If subdivision is arranged by wiping verification, sets a new Vppd level (step 405) with regard to (for example, less relatively) increment a little less than passing through.Up to from all unit of subgroup by wiping verification (passing through EV), just can apply erasing pulse to the subdivision of unit set, this subgroup belongs to by the subgroup (step 406) of verification.In case all unit in the subgroup all by wiping verification, just finish erase operation, and other subgroups (step 407) of inspection unit set no longer.Certainly also can check to confirm that it is wiped free of (step 408) really remaining subgroup.However, unit set still may receive one and wipe fully guaranteeing than the higher erasing pulse of the level of last pulse, improving reliability, for example, promptly is like this in United States Patent (USP) 6700818 and U.S. Patent application 20050117395 and 20050058005.Under the normal condition, should apply this additional pulse to collection of units, for example, based on making DQ by wiping (perhaps those reality are by the unit of verification) erase pulse level of verification, and apply pulse to different DQ by the subdivision of unit set.
The quantity of verification operation just can reduce like this, and can finish erase operation sooner.In addition, if the subgroup is limited on a few word line in the whole word lines that comprise the unit set that is wiped free of, expense switching time (to the verification grid voltage, returning then from 0V) also can significantly reduce.
The subgroup of wiping the unit set of verification can comprise between all subgroups of unit set itself, from an erase operation to another erase operation, regularly, periodically or randomly rotate.
This part checkschema depends on the homogeneity that is wiped free of the ground unit set can be successful.For example, with reference to Fig. 5, this figure is the distribution of threshold voltages in the subgroup of a NROM array, and it is the function of subgroup scale.Be the embodiment of a basically identical among the figure, wherein all unit and the variations between the unit are actually at random, and it is distributed as Gaussian distribution.This just can associate the erasing speed of erasing speed of subgroup (requirement can be wiped the slowest unit in this subgroup) and whole unit set.That is to say, can on subgroup, such unit, wipe verification, and need not all wiping verification on the unit.But, on all unit, do not carry out because wipe verification, to wipe in execution and have certain phenomenon that do not match between the subgroup of verification and other unit, it is detailed as follows.
With reference to Fig. 6 A and 6B.Fig. 6 A wipes statistical distribution with the starting voltage of programmed cells by classic method of the prior art.Be wiped free of the unit and have Gaussian distribution, wherein all unit all are lower than and wipe verification level (curve A).Similarly, be programmed the unit and can have Gaussian distribution, wherein all unit all are higher than programming verification level (curve B).
On the contrary, Fig. 6 B is the starting voltage statistical Butut (curve C) of the unit wiped according to method provided by the invention.As mentioned above, do not wipe verification because carry out on all unit, some did not match carrying out between the subgroup of wiping verification and other unit existence.Unmatched reason is the statistical property that cell threshold voltage distributes.If the amount of bits that is wiped free of increases, that distribution of threshold voltages will become is wideer (as, curve C is just wide than curve A).This means that the possibility that individual bit exceeds its distribution of subgroup on every side increases.This does not match and can make some unit not reach to wipe verification level (right half part of curve C is being wiped on the verification level).
With reference to figure 7A and 7B.For solving this not matching, in the product operation window, wipe level and read to set between the level an extra difference.Programming verification level then changes arbitrarily, but itself and the difference read between the level can not reduce.Can be additionally or select to adopt extra-pulse mechanism (as at United States Patent (USP) 6700818, in U.S. Patent application 20050117395 and 20050058005, or the other technologies of mentioning in the background technology part), and to be set be a stronger value, wipe the verification level to guarantee that all unit all are lower than, that is, wipe fully.As previously mentioned, the another kind of selection is that bundle bunched beam one-tenth word line still less is with further minimizing expense switching time.
If in memory array, have fixing difference, can handle by dividing erase operation into subgroup, so that it is minimized in cell erasure.Correspondingly, the unit on the array collection dynamic will be more consistent (as, after circulation, remain unchanged).But since unmatched subgroup needs by verification separately, extra subregion just needs the extra verification operation of wiping.However, also needn't carry out verification to all unit.
Because the checkschema of wiping provided by the invention is based on the statistics rule, " noise edge " that therefore can ignore probability distribution is to improve precision.With reference to figure 8, this figure is the distribution of threshold voltages figure that has two subgroups of same historical record on the NROM unit that is programmed with an array.The stack degree of this distribution is very high, but still has the unit with lowest threshold voltage, and these unit decisions are the highest datum of the read operation of sensing element content correctly, and its voltage deviation is 200mV (at 5.45V and 5.65V).But if used certain level, it makes that 8 bits can not correctly be read (in this case, the bit that is programmed that is read out is wiped free of) at least, and the level difference between two subgroups is 50mV (5.65V and 5.75V).Certainly, using eight bits as trigger mechanism, only is an embodiment, the invention is not restricted to this.Correspondingly, the verification scheme of wiping of the present invention can make that quantity is bit (X＞1 of X; For example, generally be X=8) by a predetermined level, thus it is at random to reduce noise profile significantly, and it is very big to make whole unit gather the possibility that is wiped free of (by wiping verification) fully, even in fact only on the subgroup, unit, carried out verification.
Though set forth the present invention in conjunction with some specific embodiments the front, clearly, those skilled in the art can also have a lot of other selections, correction and variation at this.Correspondingly, the present invention comprises all these classes selections, revises and changes.

Claims (11)

1, a kind of method of erasing memory cell on memory array, this method comprises:
The bit of the unit set that memory array is listed applies erasing pulse, and only verification operation is wiped in a subgroup of the unit set that is wiped free of, wipe verification (EV) voltage levvl to check whether storage unit starting voltage (Vt) is reduced to, if then stop to apply erasing pulse to unit set.
2, method according to claim 1 wherein, is only just finished the verification of wiping of whole unit set after verification is wiped in this subgroup.
3, method according to claim 1 wherein, is wiped verification to this subgroup and is made its level be lower than target to wipe the calibration voltage level, to guarantee that the whole unit set still is wiped free of even without whole unit are carried out verification.
4, method according to claim 1 wherein, also comprises the verification time overhead is minimized.
5, method according to claim 1 wherein, is carried out behind extremely a small amount of word line with described subgroup pack and is wiped verification operation, with further minimizing expense switching time.
6, method according to claim 1 wherein, also is included in and reads level and wipe to increase by a setting difference between the verification level.
7, method according to claim 1 wherein, also is included in and reads level and wipe the verification level and programme to increase by a setting difference between the verification level.
8, method according to claim 1 wherein, also comprises to two or more subgroups of described unit set applying erasing pulse, does not wipe verification operation but all described subgroups are not carried out.
9, method according to claim 1 wherein, also comprises the bit of guaranteeing some by a setting level, and makes the whole unit set improve by the possibility of wiping verification, even only actual verification is carried out in a subgroup of unit.
10, method according to claim 1 wherein, also is included in to finish and wipes the after-applied extra erasing pulse of verification.
11, method according to claim 1, wherein, this subgroup that is wiped free of the unit set of verification can comprise between the subgroup of unit set, from an erase operation to another erase operation, regularly, periodically or randomly rotate.
CNA2006100059960A 2005-01-19 2006-01-18 Method for erasing memory cell on memory array Pending CN1838328A (en)

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CN110838329A (en) * 2018-08-17 2020-02-25 北京兆易创新科技股份有限公司 Memory erasing method and system

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