CN1859052B - Asynchronous clock domain signal processing method and system - Google Patents
Asynchronous clock domain signal processing method and system Download PDFInfo
- Publication number
- CN1859052B CN1859052B CN2005101359830A CN200510135983A CN1859052B CN 1859052 B CN1859052 B CN 1859052B CN 2005101359830 A CN2005101359830 A CN 2005101359830A CN 200510135983 A CN200510135983 A CN 200510135983A CN 1859052 B CN1859052 B CN 1859052B
- Authority
- CN
- China
- Prior art keywords
- signal
- unit
- multiplexing
- clock domain
- address pointer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003672 processing method Methods 0.000 title description 7
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000012545 processing Methods 0.000 claims abstract description 13
- 230000001360 synchronised effect Effects 0.000 claims description 49
- 230000005540 biological transmission Effects 0.000 claims description 13
- 238000005070 sampling Methods 0.000 claims description 8
- 238000011084 recovery Methods 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000003139 buffering effect Effects 0.000 claims description 3
- 238000013461 design Methods 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- RGNPBRKPHBKNKX-UHFFFAOYSA-N hexaflumuron Chemical compound C1=C(Cl)C(OC(F)(F)C(F)F)=C(Cl)C=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F RGNPBRKPHBKNKX-UHFFFAOYSA-N 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
This invention discloses a signal process method for asynchronous clock domains including: utilizing multiplex clock signals to convert the asynchronous domain clock signals to signals of a multiplex clock domain to write them into a buffer-storage unit to be read to compare pointers of the write-address and read-address of the buffer-storage unit and adapting the reading rate of the signals of the multiplex clock domain to be multiplexed finally, besides, a system for processing the signals is also disclosed.
Description
Technical Field
The present invention relates to signal transmission technologies, and in particular, to a method and a system for processing asynchronous clock domain signals.
Background
In the field of communication technology, in order to improve the efficiency of signal transmission, multiple asynchronous clock domain signals, such as DS1 or E1 signals, are generally mapped and multiplexed into a high-speed Synchronous Digital Hierarchy (SDH) signal for transmission.
When mapping and multiplexing the received asynchronous clock domain signal into an SDH signal, it usually adopts: firstly, temporarily storing each asynchronous clock domain signal in a buffer unit arranged for each path, then using a multiplexing clock signal to read the temporarily stored asynchronous clock domain signal from the buffer unit of each path in a time-sharing manner, carrying out rate adaptation on the read asynchronous clock domain signal, finally multiplexing the read signal according to byte interpolation, and inserting overhead bits and bytes to form an SDH signal, for example: synchronous transport mode-N (STM-N) signals or synchronous transport signal-N (STS-N), etc. When the read rate is adapted to the data signal buffered in the buffer unit, the following steps are generally adopted: and comparing the read address and the write address of the cache unit, and then adapting the read rate according to the comparison result.
However, since the asynchronous clock domain signals are temporarily stored in the buffer unit, when the read address and the write address of the buffer unit are compared, the write address of the buffer unit is generated by the recovered clock of the asynchronous clock domain signals, and the read address is generated by the multiplexing clock of the multiplexing unit, so the read address and the write address of the buffer unit belong to different clock domains, respectively, so the read address and the write address cannot be directly compared, but the read address and the write address value need to be converted into the synchronous clock domain first, and then the read address and the write address value obtained after conversion are compared, and one currently adopted method for converting the read address and the write address value of the buffer unit into the synchronous clock domain is: firstly, Gray coding processing is carried out on a read address and a write address value of an asynchronous clock domain, then the read address and the write address value obtained by coding are synchronized to the clock domain of a multiplexing unit, and inverse coding processing is carried out on the read address and the write address value to obtain the read address and the write address value in the clock domain of the multiplexing unit, and further a correct read address and write address value comparison result is obtained.
Since the above method needs to encode and de-encode the read address and write address values of the cache unit, a special encoding unit and decoding unit need to be provided for each channel in the system, which undoubtedly increases the cost and design difficulty of the system. And with the continuous expansion of the capacity of the current SDH and SONET systems, the number of supported channels is more and more, so that more coding units and decoding units need to be arranged, which results in the consumption of system resources and the multiplied increase of the design difficulty.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an asynchronous clock domain signal processing method, which solves the problems of system resource waste and design difficulty in the prior art.
The asynchronous clock domain signal processing method provided by the invention mainly comprises the following steps:
a. converting the asynchronous clock domain signal into a multiplexing clock domain signal by using a multiplexing clock signal, and writing the multiplexing clock domain signal obtained by conversion into a cache unit;
b. reading the multiplexing clock domain signal from the buffer unit, comparing the write address pointer and the read address pointer of the buffer unit, adapting the reading rate of the multiplexing clock domain signal according to the comparison result, and finally multiplexing the read multiplexing clock domain signal.
In the above method, the asynchronous clock domain signal comprises an asynchronous data signal and an asynchronous clock signal;
the step a comprises the following steps:
a1, respectively sampling the rising edge or the falling edge of the asynchronous data signal and the asynchronous clock signal by using a multiplexing clock signal, and respectively generating a synchronous data signal and a write enable signal which are synchronous with the multiplexing clock signal;
a2, when the generated write enable signal is effective, writing the generated synchronous data signal into the set buffer unit;
in step b, the step of reading the multiplexed clock domain signal from the buffer unit includes: and reading the synchronous data signal from the buffer unit when the set read enable signal is effective.
In step b of the above method, before the step of comparing the write address pointer and the read address pointer, the method further includes: recording an initial read address pointer and a write address pointer, adding 1 to the recorded write address pointer when the write enable signal is effective each time, and taking the obtained value as a current write address pointer; and adding 1 to the recorded read address pointer every time the read enable signal is active, and using the obtained value as the current read address pointer.
In step b of the above method, the step of comparing the write address pointer and the read address pointer comprises: calculating the difference between a write address pointer and a read address pointer of the cache unit to obtain the actual storage bit number of the multiplexing clock domain signal in the cache unit;
the step of adapting the read rate in dependence on the comparison comprises: comparing the obtained actual storage bit number with the set high and low thresholds, and carrying out negative adjustment when the actual storage bit number is greater than the set high threshold; and when the actual storage bit number is smaller than the set low threshold, performing positive adjustment.
In step b of the above method, the negative adjustment is: increasing the number of transmission bits; the positive adjustment is: the number of transmission bits is reduced.
In the above method, the frequency of the multiplexed clock signal is greater than 2 times the frequency of the asynchronous clock domain signal.
In the above method, the frequency of the multiplexed clock signal is 4 times the frequency of the asynchronous clock domain signal.
Another objective of the present invention is to provide an asynchronous clock domain signal processing system, which mainly comprises: the device comprises a cache unit, a comparison unit and a multiplexing unit; wherein,
the buffer unit is used for buffering the multiplexing clock domain signal;
the comparison unit is used for comparing the write address pointer and the read address pointer of the cache unit and sending an adjustment signal to the multiplexing unit according to the comparison result;
the multiplexing unit is used for reading the multiplexing clock domain signal from the buffer unit, adapting the reading rate of the multiplexing clock domain signal according to the received adjusting signal and multiplexing the read multiplexing clock domain signal;
the system further comprises a synchronization unit; wherein,
the synchronous unit is used for receiving the multiplexing clock signal from the multiplexing unit, converting the received asynchronous clock domain signal into a multiplexing clock domain signal by using the multiplexing clock signal, and then writing the multiplexing clock domain signal into the cache unit;
the multiplexing unit is further configured to send the multiplexed clock signal to the synchronization unit.
In the above system, the asynchronous clock domain signal comprises: an asynchronous data signal and an asynchronous clock signal;
the synchronous unit is used for respectively sampling the rising edge or the falling edge of the asynchronous data signal and the asynchronous clock signal by using a multiplexing clock signal received from the multiplexing unit, respectively generating a synchronous data signal and a write enable signal which are synchronous with the multiplexing clock signal, and sending the write enable signal to the cache unit and the comparison unit when the generated write enable signal is effective, and writing the generated synchronous data signal into the cache unit;
the buffer unit is used for temporarily storing the synchronous data signals output by the synchronous unit;
the comparison unit is used for setting a write address pointer of the cache unit according to the received write enable signal, setting a read address pointer of the cache unit according to the received read enable signal, calculating the difference between the write address pointer and the read address pointer to obtain the actual storage bit number of the cache unit, comparing the obtained actual storage bit number with a set threshold, and sending an adjustment signal to the multiplexing unit according to the comparison result;
the multiplexing unit is used for sending a read enabling signal to the buffer unit and the comparison unit when the set read enabling signal is effective, reading the synchronous data signal from the buffer unit, adapting the reading rate of the synchronous data signal according to the adjusting signal received from the comparison unit, and multiplexing the read synchronous data signal.
In the above system, the adjustment signal comprises: a positive adjustment signal and a negative adjustment signal; and is
The comparison unit is used for sending a negative adjustment signal to the multiplexing unit when the obtained actual storage bit number is larger than a set high threshold; when the actual storage bit number is smaller than the set low threshold, sending a positive adjustment signal to the multiplexing unit;
the multiplexing unit is used for increasing the transmission bit number when receiving the negative adjustment signal from the comparison unit; and reducing the number of transmission bits upon receiving a positive adjustment signal from the comparing unit.
In the above system, the system further includes a clock data recovery decoding unit, configured to receive an original asynchronous clock domain signal input from outside, perform clock and data recovery and decoding processing on the original asynchronous clock domain signal, and send the processed asynchronous clock domain signal to the synchronization unit.
In the above system, the buffer unit is a first-in first-out FIFO buffer.
In summary, the present invention adopts: converting the asynchronous clock domain signal into a multiplexing clock domain signal by using the multiplexing clock signal, and writing the multiplexing clock domain signal into a set cache unit; reading the multiplexing clock domain signal from the buffer unit, comparing the write address pointer and the read address pointer of the buffer unit, adapting the read rate of the multiplexing clock domain signal according to the comparison result, and finally multiplexing the read multiplexing clock domain signal. In addition, the invention also discloses an asynchronous clock domain signal processing system. The invention adopts the method of firstly synchronizing the asynchronous clock domain signal into the multiplex clock domain signal and then storing the multiplex clock domain signal into the cache unit, so that the read address and the write address of the cache unit belong to the multiplex clock domain, thereby solving the problem that the read-write address can not be directly compared because the read-write address belongs to different clock domains in the prior art, avoiding the coding and decoding links, reducing the system resource consumption and reducing the design difficulty.
Drawings
FIG. 1 is a flowchart of an asynchronous clock domain signal processing method according to an embodiment of the invention.
FIG. 2 is a block diagram of an asynchronous clock domain signal processing system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings.
The core idea of the invention is as follows: converting the asynchronous clock domain signal into a multiplexing clock domain signal by using the multiplexing clock signal, and writing the multiplexing clock domain signal into a set cache unit; reading the multiplexing clock domain signal from the buffer unit, comparing the write address pointer and the read address pointer of the buffer unit, adapting the read rate of the multiplexing clock domain signal according to the comparison result, and finally multiplexing the read multiplexing clock domain signal.
The following describes the asynchronous clock domain signal processing method in detail by using a specific embodiment, and the flow of the method is shown in fig. 1, and the method specifically includes the following steps:
step 101: the asynchronous clock domain signal is converted to a multiplexed clock domain signal using a multiplexed clock signal.
Wherein, the asynchronous clock domain signal is: and carrying out clock, data recovery and decoding processing on the received original asynchronous clock domain signal to obtain a signal, wherein the asynchronous clock domain signal comprises an asynchronous data signal and an asynchronous clock signal. And the step of converting specifically comprises: the method includes sampling a rising edge or a falling edge of an input asynchronous data signal with a multiplexing clock signal to generate a synchronous data signal synchronous with the multiplexing clock signal, and sampling the rising edge or the falling edge of the input asynchronous clock signal with the multiplexing clock signal to generate a write enable signal synchronous with the multiplexing clock signal. The asynchronous clock domain signal is converted to a multiplexed clock domain signal using a multiplexed clock signal.
In addition, since the low-speed asynchronous data signal and the asynchronous clock signal are sampled by the high-speed multiplexed clock signal, the frequency of the multiplexed clock signal needs to be greater than 2 times the frequency of the sampled asynchronous data signal or asynchronous clock signal according to nyquist sampling law. To leave a certain margin (margin), it is taken 4 times here.
Step 102: writing the multiplexing clock domain signal obtained by conversion into a set cache unit; and the steps specifically include: and when the generated write enable signal is effective, writing the generated synchronous data signal into the set buffer unit. The buffer unit may be a FIFO buffer, etc.
Step 103: reading the multiplexing clock domain signal from the buffer unit, comparing the write address pointer and the read address pointer of the buffer unit, adapting the read rate of the multiplexing clock domain signal according to the comparison result, and finally multiplexing the read multiplexing clock domain signal.
The method specifically comprises the following steps: setting a high threshold and a low threshold in advance according to the service rate and the service jitter performance; when the set read enable signal of the multiplexing unit is effective, reading the stored multiplexing clock domain signal from the buffer unit, calculating the difference between a write address pointer and a read address pointer of the buffer unit to obtain the actual storage bit number of the multiplexing clock domain signal in the buffer unit, then respectively comparing the actual storage bit number with the set high threshold and the set low threshold, and carrying out negative adjustment when the actual storage bit number is greater than the high threshold; and when the actual storage bit number is smaller than the lower threshold, performing positive adjustment. The negative adjustment may be performed by: increasing the number of transmission bits, such as: enabling the current frame to transmit data of adjusting step size by multiple bits; the positive adjustment is performed as follows: the number of transmission bits is reduced. Such as: the current frame is made to transmit data of an adjustment step size of a few bits. And finally, multiplexing the read multiplexing clock domain signals. The value of the adjustment step may be 1, 2, 3, or 8, preferably 1.
Wherein the read enable signal is set according to a certain rule such as STM-1 frame. The asynchronous clock signals of the channels are synchronized with the multiplexed clock signal because they have been converted to write enable signals that are synchronized with the multiplexed clock signal, while the read enable signals are generated by the multiplexing unit. In this case, the read address and the write address of the buffer unit both belong to the same clock domain, i.e. the multiplexing clock domain, so the read address pointer and the write address pointer of the buffer unit can be directly compared.
The rate adaptation method described above is illustrated by an example. Assuming that the depth of the buffer unit is 1024, the initial read pointer is 0, the initial write pointer is 512, the set high threshold is 700, the low threshold is 200, after a period of time, the write address pointer is 800 in the second cycle, and the read address pointer is 960 in the first cycle, at this time, the actual storage bit number is 1024+ 800-: making the current frame transmit 1 bit more data; after a period of time, the write address pointer is changed to 100 in the third cycle, and the read address pointer is changed to 1000 in the second cycle, then the actual storage bit number is 1024 × 2+100- (1024+1000) ═ 124, which is smaller than the set low threshold value 200, which indicates that the reading speed is too fast, so that the positive adjustment is performed, and the current frame is less transmitted with 1-bit data.
Among them, it should be noted that: if the depth of the FIFO is 1024, the read/write address pointer value will not exceed 1023, and when the read/write address pointer value reaches 1023, it returns to 0 again, so that the write address pointer value may be smaller than the read address pointer value, at this time, the value of the write address pointer needs to be added with n × 1024 and then subtracted with the value of the read address pointer, so as to obtain the actual number of storage bits in the buffer unit, where n is the number of read cycles of the buffer unit.
The above describes the asynchronous clock domain signal processing method of the present invention, and the following describes the asynchronous clock domain signal processing system of the present invention, and the system structure is shown in fig. 2, and mainly includes: the device comprises a cache unit, a comparison unit and a multiplexing unit; the system further comprises a synchronization unit, wherein,
the synchronous unit is used for receiving the multiplexing clock signal from the multiplexing unit, converting the received asynchronous clock domain signal into a multiplexing clock domain signal by using the multiplexing clock signal, and then writing the multiplexing clock domain signal into the cache unit; the buffer unit is used for buffering the multiplexing clock domain signal, and can be an FIFO buffer and the like; the comparison unit is used for comparing the write address pointer and the read address pointer of the cache unit and sending an adjustment signal to the multiplexing unit according to the comparison result; the multiplexing unit is used for sending a multiplexing clock signal to the synchronization unit, reading the multiplexing clock domain signal from the buffer unit, adapting the reading rate of the multiplexing clock domain signal according to the received adjusting signal and multiplexing the read multiplexing clock domain signal.
Furthermore, in the above system, the asynchronous clock domain signal comprises: an asynchronous data signal and an asynchronous clock signal; the synchronous unit is used for respectively sampling the rising edge or the falling edge of the asynchronous data signal and the asynchronous clock signal by using the multiplexing clock signal received from the multiplexing unit, respectively generating a synchronous data signal and a write enable signal which are synchronous with the multiplexing clock signal, and sending the write enable signal to the cache unit and the comparison unit when the generated write enable signal is effective, and writing the generated synchronous data signal into the cache unit. The buffer unit is used for temporarily storing the synchronous data signals output by the synchronous unit. The comparison unit is used for setting a write address pointer of the buffer unit according to the received write enable signal, setting a read address pointer of the buffer unit according to the received read enable signal, calculating the difference between the write address pointer and the read address pointer to obtain the actual storage bit number of the buffer unit, comparing the obtained actual storage bit number with a set threshold, and sending an adjustment signal to the multiplexing unit according to the comparison result. The multiplexing unit is used for sending the read enabling signal to the buffer unit and the comparison unit when the set read enabling signal is effective, reading the temporarily stored synchronous data signal from the buffer unit, adapting the reading rate of the synchronous data according to the adjusting signal received from the comparison unit, and multiplexing the read synchronous data.
And wherein said adjustment signal comprises: a positive adjustment signal and a negative adjustment signal, and when the obtained actual storage bit number is greater than a set high threshold, sending the negative adjustment signal; and when the actual storage bit number is smaller than the set low threshold, sending a positive adjustment signal.
Said adapting the read rate of the synchronization data comprises: when receiving the negative adjustment signal from the comparison unit, the number of transmission bits is increased, such as: enabling the current frame to transmit data of adjusting step size by multiple bits; and when receiving the positive adjustment signal from the comparison unit, reducing the transmission bit number, such as: the current frame is made to transmit data of an adjustment step size of a few bits. The value of the adjustment step length can be 1, 2, 3 or 8, and is preferably 1.
In addition, the system may further include a clock data recovery decoding unit (not shown in the figure) for receiving an original asynchronous clock domain signal inputted from the outside, performing clock, data recovery and decoding processing on the original asynchronous clock domain signal, and transmitting the processed asynchronous clock domain signal to the synchronization unit, and the asynchronous clock domain signal includes: an asynchronous data signal and an asynchronous clock signal.
In short, the above description is only an example of the present invention, and is not intended to limit the scope of the present invention.
Claims (12)
1. A method for asynchronous clock domain signal processing, the method comprising:
a. converting the asynchronous clock domain signal into a multiplexing clock domain signal by using a multiplexing clock signal, and writing the multiplexing clock domain signal obtained by conversion into a cache unit;
b. reading the multiplexing clock domain signal from the buffer unit, comparing the write address pointer and the read address pointer of the buffer unit, adapting the reading rate of the multiplexing clock domain signal according to the comparison result, and finally multiplexing the read multiplexing clock domain signal;
wherein the asynchronous clock domain signal comprises an asynchronous data signal and an asynchronous clock signal;
the step a comprises the following steps:
a1, respectively sampling the rising edge or the falling edge of the asynchronous data signal and the asynchronous clock signal by using a multiplexing clock signal, and respectively generating a synchronous data signal and a write enable signal which are synchronous with the multiplexing clock signal;
a2, when the generated write enable signal is valid, the generated synchronous data signal is written into the set buffer unit.
2. The method of claim 1,
in step b, the step of reading the multiplexed clock domain signal from the buffer unit includes: and reading the synchronous data signal from the buffer unit when the set read enable signal is effective.
3. The method of claim 1, wherein in step b, before the step of comparing the write address pointer and the read address pointer, further comprising: recording an initial read address pointer and a write address pointer, adding 1 to the recorded write address pointer when the write enable signal is effective each time, and taking the obtained value as a current write address pointer; and adding 1 to the recorded read address pointer every time the read enable signal is active, and using the obtained value as the current read address pointer.
4. The method according to any one of claims 1 to 3, wherein in step b, the step of comparing the write address pointer and the read address pointer is: calculating the difference between a write address pointer and a read address pointer of the cache unit to obtain the actual storage bit number of the multiplexing clock domain signal in the cache unit;
the step of adapting the read rate in dependence on the comparison comprises: comparing the obtained actual storage bit number with the set high and low thresholds, and carrying out negative adjustment when the actual storage bit number is greater than the set high threshold; and when the actual storage bit number is smaller than the set low threshold, performing positive adjustment.
5. The method according to claim 4, wherein in step b, the negative adjustment is: increasing the number of transmission bits; the positive adjustment is: the number of transmission bits is reduced.
6. A method according to claim 1, 2 or 3, wherein the frequency of the multiplexed clock signal is greater than 2 times the frequency of the asynchronous clock domain signal.
7. The method of claim 6, wherein the frequency of the multiplexed clock signal is 4 times the frequency of the asynchronous clock domain signal.
8. An asynchronous clock domain signal processing system, the system comprising: the device comprises a cache unit, a comparison unit and a multiplexing unit; wherein,
the buffer unit is used for buffering the multiplexing clock domain signal and temporarily storing the synchronous data signal output by the synchronous unit;
the comparison unit is used for comparing the write address pointer and the read address pointer of the cache unit and sending an adjustment signal to the multiplexing unit according to the comparison result;
the multiplexing unit is used for reading the multiplexing clock domain signal from the buffer unit, adapting the reading rate of the multiplexing clock domain signal according to the received adjusting signal and multiplexing the read multiplexing clock domain signal;
characterized in that the system further comprises a synchronization unit; wherein,
the synchronous unit is used for receiving the multiplexing clock signal from the multiplexing unit, converting the received asynchronous clock domain signal into a multiplexing clock domain signal by using the multiplexing clock signal, and then writing the multiplexing clock domain signal into the buffer unit, wherein the asynchronous clock domain signal comprises: an asynchronous data signal and an asynchronous clock signal, the converting comprising: sampling rising edges or falling edges of the asynchronous data signal and the asynchronous clock signal respectively by using a multiplexing clock signal received from a multiplexing unit, and generating a synchronous data signal and a write enable signal which are synchronous with the multiplexing clock signal respectively, wherein the writing comprises the following steps: when the generated write enable signal is valid, writing the generated synchronous data signal into a buffer unit;
the multiplexing unit is further configured to send the multiplexed clock signal to the synchronization unit.
9. The system of claim 8,
the synchronization unit is used for sending a write enable signal to the buffer unit and the comparison unit when the generated write enable signal is valid;
the comparison unit is used for setting a write address pointer of the cache unit according to the received write enable signal, setting a read address pointer of the cache unit according to the received read enable signal, calculating the difference between the write address pointer and the read address pointer to obtain the actual storage bit number of the cache unit, comparing the obtained actual storage bit number with a set threshold, and sending an adjustment signal to the multiplexing unit according to the comparison result;
the multiplexing unit is used for sending a read enabling signal to the buffer unit and the comparison unit when the set read enabling signal is effective, reading the synchronous data signal from the buffer unit, adapting the reading rate of the synchronous data signal according to the adjusting signal received from the comparison unit, and multiplexing the read synchronous data signal.
10. The system of claim 9, wherein the adjustment signal comprises: a positive adjustment signal and a negative adjustment signal; and is
The comparison unit is used for sending a negative adjustment signal to the multiplexing unit when the obtained actual storage bit number is larger than a set high threshold; when the actual storage bit number is smaller than the set low threshold, sending a positive adjustment signal to the multiplexing unit;
the multiplexing unit is used for increasing the transmission bit number when receiving the negative adjustment signal from the comparison unit; and reducing the number of transmission bits upon receiving a positive adjustment signal from the comparing unit.
11. The system of claim 8, further comprising a clock data recovery decoding unit for receiving an original asynchronous clock domain signal inputted from the outside, performing clock, data recovery and decoding processes on the original asynchronous clock domain signal, and transmitting the processed asynchronous clock domain signal to the synchronization unit.
12. The system according to any of claims 8 to 11, wherein said buffer unit is a first-in-first-out FIFO buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101359830A CN1859052B (en) | 2005-12-29 | 2005-12-29 | Asynchronous clock domain signal processing method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101359830A CN1859052B (en) | 2005-12-29 | 2005-12-29 | Asynchronous clock domain signal processing method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1859052A CN1859052A (en) | 2006-11-08 |
| CN1859052B true CN1859052B (en) | 2011-06-15 |
Family
ID=37297919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005101359830A Active CN1859052B (en) | 2005-12-29 | 2005-12-29 | Asynchronous clock domain signal processing method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1859052B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101056164B (en) * | 2007-05-31 | 2011-04-27 | 北京中星微电子有限公司 | A synchronization device across asynchronization clock domain signals |
| US9275704B2 (en) * | 2014-07-31 | 2016-03-01 | Texas Instruments Incorporated | Method and apparatus for asynchronous FIFO circuit |
| CN105703828A (en) * | 2016-01-21 | 2016-06-22 | 上海斐讯数据通信技术有限公司 | Infrared laser communication system |
| CN112199071B (en) * | 2020-10-26 | 2024-02-09 | 中国兵器工业集团第二一四研究所苏州研发中心 | Address controllable asynchronous buffer and asynchronous buffer method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1059437A (en) * | 1990-06-04 | 1992-03-11 | Gpt有限公司 | Synchronous digital hierarchy sign indicating number speed is adjusted again |
| US6516001B1 (en) * | 1998-06-05 | 2003-02-04 | Nec Corporation | Device for converting sonet data input into DS-N data output |
| CN1585312A (en) * | 2003-08-19 | 2005-02-23 | 华为技术有限公司 | Method for converting asynchronous clock zone into synchronous one |
| CN1588837A (en) * | 2004-08-25 | 2005-03-02 | 启攀微电子（上海）有限公司 | Shaking attenuation processor in SDH branch clock restoration |
-
2005
- 2005-12-29 CN CN2005101359830A patent/CN1859052B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1059437A (en) * | 1990-06-04 | 1992-03-11 | Gpt有限公司 | Synchronous digital hierarchy sign indicating number speed is adjusted again |
| US6516001B1 (en) * | 1998-06-05 | 2003-02-04 | Nec Corporation | Device for converting sonet data input into DS-N data output |
| CN1585312A (en) * | 2003-08-19 | 2005-02-23 | 华为技术有限公司 | Method for converting asynchronous clock zone into synchronous one |
| CN1588837A (en) * | 2004-08-25 | 2005-03-02 | 启攀微电子（上海）有限公司 | Shaking attenuation processor in SDH branch clock restoration |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1859052A (en) | 2006-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4928275A (en) | Synchronization of asynchronous data signals | |
| US5142529A (en) | Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency | |
| EP1865632B1 (en) | A method and apparatus for signal splitting and synthesizing | |
| CN101299647B (en) | Apparatus and method for implementing nondestructive switch of SDH service | |
| JP2008148250A (en) | Transmitter device, and receiver device | |
| CN1859052B (en) | Asynchronous clock domain signal processing method and system | |
| WO2020147661A1 (en) | Signal transmission method and apparatus, network device and computer-readable storage medium | |
| JP2004064617A (en) | Serial digital signal transmission system | |
| US7068679B1 (en) | Asynchronous payload mapping using direct phase transfer | |
| WO2009026831A1 (en) | A system and a method for virtual concatenation synchronization in optical transport network | |
| US6349101B1 (en) | Cell buffer circuit for an ATM cells to SDH-based data conversion system | |
| CN114826476B (en) | Method and system for realizing GMP mapping in OTN | |
| US7349445B2 (en) | Phase adjusting apparatus, phase adjusting method for use therein, and program for phase adjusting method | |
| KR100358382B1 (en) | Apparatus for parallel mapping of serial input data in SDH system | |
| JP4685131B2 (en) | Moving average calculation processing method when clock deviation changes | |
| CN1983920B (en) | Hybrid transmitting system and method for processing its signal | |
| JP3722748B2 (en) | Multiplexing method and apparatus suitable for overhead data transmission from multiple communication lines | |
| KR100301294B1 (en) | Apparatus for processing data by a byte in optical transmission system | |
| JP2003244085A (en) | Phase matching control system and phase matching control method in a plurality of system transmission lines | |
| US6888826B1 (en) | Pointer generator design that provides multiple outputs that can be synchronized to different clocks | |
| CN110519667B (en) | Method for realizing optical signal line crossing | |
| US9549231B2 (en) | Optical transmission device and OPU frame generation method | |
| CN100417159C (en) | Method for decreasing operating frequency of virtual cascade restoring module | |
| JP2706199B2 (en) | SDH interface circuit | |
| JP2002247002A (en) | Asynchronous signal transmission device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |