CN1858706A - Method and system for 51 one-chip computer on-system upgrading - Google Patents
Method and system for 51 one-chip computer on-system upgrading Download PDFInfo
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- CN1858706A CN1858706A CN 200610035034 CN200610035034A CN1858706A CN 1858706 A CN1858706 A CN 1858706A CN 200610035034 CN200610035034 CN 200610035034 CN 200610035034 A CN200610035034 A CN 200610035034A CN 1858706 A CN1858706 A CN 1858706A
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Abstract
This invention discloses a method for upgrading 51 single-chip processors on the system including: designing a JTAG interface on the 51 single-chip processor of a single-chip processor system, utilizing the JTAG public instruction to realize upgrade and program to the processor connected with the interface. This invention also discloses a system of 51 single-chip processor system including a 51 single-chip processor, a JTAG interface module for providing the JTAG interface and realizing program and check to the processor connected with the JTAG interface by its level settting and scan function of the JTAG chain to outside pins of the chip, which can program on board directly.
Description
Technical field
The present invention relates to a kind of Single Chip Microcomputer (SCM) system, specifically, relate to a kind of 51 single-chip microcomputers in the system upgrade method and system.
Background technology
51 single-chip microcomputers are because its good cost performance is continued to use decades at electronic applications, and are still in the ascendant.And 51 series monolithic chips are from strap internal program storer, and application program energy direct burning can be removed the outer ROM circuit of sheet from 51 singlechip chips, make that the hardware design of system is comparatively simple.
Because the sheet internal program software burning of 51 single-chip microcomputers needs the program voltage of 12V, and generally burn sheet and solidify by means of the programmable device of ALL-11 and so on.Therefore,, need from system, take out singlechip chip, after the programmable device burning, install back on the veneer again if the sheet internal program of veneer needs burning or upgrading.So not only operation is gone up cumbersome, also there is a problem: can upgrade in order to guarantee chip software, the socket of chip correspondence has been installed on the veneer, but these sockets (the particularly socket of plastic leaded chip carrier PLCC) can produce the problem of the loose contact that be caused by oxidation and so on along with the prolongation of service time, have reduced the reliability of system.
A kind of prior art system is not used socket for strengthening reliability, directly chips welding to system single board, add the flying needle of man-hour by ICT (In Circuit Test) then and carry out chip software and programme.The shortcoming of this method is:
1, design is higher at the loading equipemtn cost of the ICT of this system;
2, can only carry out the programming of ICT flying needle man-hour adding for the first time, upgrade software can not be programmed by ICT again after the system sales.
Another kind of prior art system is selected the single-chip microcomputer of the 5V program voltage of ATMEL, and increases aiding CPU in system, solidifies the custom-designed chip programming driver of ATMEL in the above.The host CPU that described CPU is specifically designed to system carries out software programming, realizes the programing function of host CPU in system.But the single-chip microcomputer price of 5V program voltage is more expensive; And CPU who carries out software programming specially of system's needs, hardware circuit is very complicated; Aiding CPU can only be programmed to a kind of producer chip, can't programme to the chip of other alternative producers.
Summary of the invention
In view of above-mentioned existing in prior technology problem, the purpose of this invention is to provide a kind of 51 single-chip microcomputers in the system upgrade method and system, during with the software upgrading of solution singlechip chip, need from system, take out chip and hardware cost problem of higher.
The objective of the invention is to be achieved through the following technical solutions:
51 single-chip microcomputers provided by the invention comprise in the system upgrade method:
A, on 51 single-chip microcomputers, jtag interface is set;
B, utilize the public instruction of JTAG, realize the single-chip microcomputer that links to each other with the jtag interface programming of upgrading.
The wherein said jtag interface mode that is provided with comprises by Erasable Programmable Logic Device EPLD logic chip and providing, and when programming, the operating voltage of 5V is transformed to the program voltage of 12V.
The operation carried out of the public instruction of the described JTAG of utilization comprises further:
B1, single-chip microcomputer is carried out full wafer wipe.
B2, single-chip microcomputer is write object code;
Comprise that also the object code to writing carries out verification after writing object code.
And, described single-chip microcomputer comprises the builtin voltage mapping mode that adopts the MAX232 chip for providing the program voltage mode of 12V.
51 Single Chip Microcomputer (SCM) system provided by the invention, comprise 51 single-chip microcomputers, the jtag interface module, it is used to provide jtag interface, utilize level setting and the scan function of JTAG chain, realize the single-chip microcomputer that links to each other with the jtag interface chip is programmed and verification the chip exterior pin; Voltage control module, the conversion that it is used to control the operating voltage of the program voltage of 51 common single-chip microcomputer 12V and 5V or 3.3V can utilize the builtin voltage conversion of some chip to realize exporting the program voltage of 12V; The isolated controlling module, it is used for the ternary pin that does not have the singlechip CPU that is connected with the jtag interface module of isolating.
Wherein the jtag interface module comprises Erasable Programmable Logic Device EPLD logic chip, and wherein the address date hardware of the pin of EPLD and 51 single-chip microcomputers links.
This system comprises that also voltage control module comprises the MAX232 chip.
Described further isolated controlling module comprises three-state buffer.
Utilize the present invention, 51 single-chip microcomputers are no matter be first processing, still system's software upgrading from now on, do not need chip is taken off from veneer, computing machine is directly by a simple JTAG loaded cable, just can programme to singlechip chip, not only cost is lower, and has improved the reliability of system upgrade.
Utilize the present invention to carry out in-system programming further to any a 51 singlechip chips.
Description of drawings
Fig. 1 is a described system chart of the present invention;
Fig. 2 is the circuit connection diagram of described system of the present invention;
Fig. 3 utilizes jtag interface to realize the operational flowchart that singlechip chip is programmed.
Embodiment
Boundary scan interface (JTAG) technology is popular measurability interfacing of present industry, and it is to increase boundary scan cell on the input and output pin of chip, and these boundary scan cells are connected into a JTAG chain, are connected on the jtag interface.By control to jtag interface, can realize the isolating chip external circuit, directly the inside pin circuitry of chip is carried out level setting and scanning (under the INTEST mode); Also can realize the inner pin circuitry of isolating chip, directly the chip exterior pin be carried out level setting and scanning (under the EXTEST mode).Jtag interface comprises 5 signal: TDO, TDI, TCK, TMS, TRST.TDO is the output interface of JTAG chain serial data; TDI is the input interface of JTAG chain serial data; TCK is the clock signal of JTAG chain serial data; TMS is the control signal of control JTAG chain duty; TRST is the reset signal of jtag interface, when this signal is 0, and JTAG chain forced resetting.
Present logic chip as: chips such as Erasable Programmable Logic Device EPLD, CPLD, FPGA, the JTAG chain is contained in inside, and jtag interface is provided.Computing machine can pass through interfaces such as serial ports, parallel port, USB and connect the JTAG loaded cable, is attached thereto, and carries out the various instruction manipulations of JTAG.
Utilize jtag interface, not only can realize band jtag interface chip itself is carried out load software (as Erasable Programmable Logic Device EPLD software loading), simultaneously, can also realize the external circuit of the pin that links to each other with the JTAG chain on this chip is carried out level setting and sampled scan.The present invention utilizes level setting and the scan function of JTAG chain to the chip exterior pin, realizes the single-chip microcomputer that links to each other with the jtag interface chip is programmed and verification.
As shown in Figure 1, total system comprises background administration module, jtag interface module, voltage control module, isolated controlling module and 51 single-chip microcomputers.
Background administration module: form by computing machine and JTAG loaded cable.Computing machine is responsible for depositing the program code that will programme; Operation JTAG programming software, issue the JTAG dependent instruction, issue programming code, read and verification programming back single-chip microcomputer on code; The JTAG loaded cable connects computing machine and jtag interface module.
The jtag interface module: jtag interface is provided, and the external circuit of the pin of realizing linking to each other with the JTAG chain carries out level setting and sampled scan.Mainly form by logic chip (as EPLD), jtag interface connector etc.
Voltage control module: be used to control the switching of the operating voltage of the program voltage of 51 common single-chip microcomputer 12V and 5V or 3.3V, can utilize the builtin voltage conversion of some chip to realize exporting the program voltage of 12V.
Isolated controlling module: during 51 mcu programmings, the part port that needs RST, PSEN, ALE, P0 and P1 port, P2 and P3 needs to be connected with the pin of jtag interface module (as EPLD), and Single Chip Microcomputer (SCM) system is when normally moving, and this module is used for controlling signals such as RST, PSEN, ALE, P1, P2 and P3 port and does not link with the pin of jtag interface module (as EPLD).In order normally to move in system, realize the isolation of these pins, use three-state buffer to carry out isolated controlling here.
51 single-chip microcomputers: receive the programming instruction and the programming data of the output of JTAG chain, preserve the program object code of programming; Receive the code reading command of JTAG chain output, the program object code that output is preserved.It is the destination object that computing machine is programmed by JTAG.
Present embodiment adopts Erasable Programmable Logic Device EPLD (CPLD/FPGA) logic chip that jtag interface is provided, is used for realizing the MAX232 chip of builtin voltage conversion and 245 three-state buffers that model is 74ACT16245.Wherein the EPLD logic chip not only possesses jtag interface, or programmable logic chip; Adopt MAX232 chip hardware cost low, MAX232 is the serial ports level transferring chip simultaneously, can satisfy the needs of serial ports Transistor-Transistor Logic level and RS-232 level conversion in 51 systems.
Each parts annexation is as shown in Figure 2: background computer links to each other with jtag interface by the JTAG loaded cable; The address date hardware of 51 single-chip microcomputers and the pin of EPLD logic chip link together, promptly with chip on the JTAG chain link together, to realize system logic.245 three-state buffers connect single-chip microcomputer and EPLD to have in the single-chip microcomputer practical application that programming needs but not and other the pin that links together of the EPLD chip three-state of carrying out two end signals isolate; EPLD also exports 2 pins, one links to each other with the OE pin of three-state buffer, another tying-in is crossed Darlington transistor and is linked to each other with single-chip microcomputer EA pin with relay, realize the 12V program voltage of single-chip microcomputer EA pin and the switching controls of 5V operating voltage, when guaranteeing programming, this leg signal is 0, Darlington transistor output 1, the relay adhesive, what EA obtained is the program voltage of 12V; When system normally moved, the leg signal of this JTAG chain was 1, Darlington transistor output 0, and not adhesive of relay, EA obtains the operating voltage of 5V.
Because the jtag interface standard is the standard of an opening, all support the chip of jtag interface to defer to the public instruction of identical JTAG.To single-chip microcomputer programme and the most basic operation of verification be exactly the write and read of data.That writes is operating as: the OPADD signal, and write signal (being 1), the data-signal that write and the control signal of particular port (RST, ALE, PSEN), time-delay then, write signal exports 0 again, time-delay again, write signal exports 1 again, finishes the operation of once writing like this.That reads is operating as: the control signal (RST, ALE, PSEN) of OPADD signal, read signal (being 1) and particular port, and time-delay then, the data-signal that will read is obtained in read signal output 0, and read signal exports 1 again, finishes the operation of once reading like this.
Write operation corresponds to the JTAG operating process, background computer issue preset (PRELOAD) instruction, the control signal of address signal, the data-signal that need write and particular port (RST, ALE, PSEN), write signal (being 1) from jtag interface TDI serial-shift to the JTAG chain; Instruct by external testing (EXTEST) then, data parallel on the JTAG chain is exported on the pin of EPLD, after time-delay, issue again preset (PRELOAD) instruction, the control signal (RST, ALE, PSEN) of address signal, the data-signal that need write, write signal (being 0) and particular port from jtag interface TDI serial-shift to the JTAG chain; By external testing (EXTEST) instruction, the data parallel on the JTAG chain is exported on the pin of EPLD then; Again through the time-delay after, issue preset (PRELOAD) instruction, the control signal (RST, ALE, PSEN) of address signal, write signal (being 1) and particular port from jtag interface TDI serial-shift to the JTAG chain; By external testing (EXTEST) instruction, the data parallel on the JTAG chain is exported on the pin of EPLD at last.So just finish the operation of once writing.
Read operation corresponds to the JTAG operating process, and computing machine issues and presets (PRELOAD) instruction, the control signal of address signal, particular port (RST, ALE, PSEN) and read signal (being 1) from jtag interface TDI serial-shift to the JTAG chain; By external testing (EXTEST) instruction, the data parallel on the JTAG chain is exported on the pin of EPLD then; Through the time-delay after, issue again preset (PRELOAD) instruction, the control signal of address signal and particular port (RST, ALE, PSEN), read signal (being 0) from jtag interface TDI serial-shift to the JTAG chain; By external testing (EXTEST) instruction, the data parallel on the JTAG chain is exported on the pin of EPLD then; Then issue sampling (SAMPLE) instruction, obtain the data on the data line pin of EPLD, serial-shift is exported to jtag interface TDO; At last through the time-delay after, issue preset (PRELOAD) instruction, the control signal of address signal, the data-signal that need write and particular port (RST, ALE, PSEN), read signal (being 1) from jtag interface TDI serial-shift to the JTAG chain.Finished the operation of once reading like this.
After basic read-write operation has been arranged, can be according to the programming instruction and flow process (record is all arranged on each handbook) requirement of various 51 singlechip chips, target program is programmed on the singlechip chip in the system.Flow process as shown in Figure 3,
Step 1: the signal that EPLD output control three-state buffer OE is set is 0.
Step 2: the order of reading device ID, whether verifying parts is normal, is to change step 3 normally over to, otherwise forwards step 10 to.
Step 3: it is 0 that EPLD voltage selection signal is set, and selects the program voltage of 12V.
Step 4: single-chip microcomputer is carried out the order that full wafer is wiped, carry out full wafer and wipe.
Step 5: single-chip microcomputer is write object code;
Step 6: it is 1 that EPLD voltage selection signal is set, and selects the operating voltage of 5V.
Step 7: read the object code of programming on the single-chip microcomputer.
Step 8: the object code that verification writes and reads, if consistent, change step 9 over to, otherwise forward step 10 to.
Step 9: report and programme successfully.
Step 10: when makeing mistakes, report corresponding error message.
Step 11: process ends.
Except designing load software, can also directly utilize third party JTAG loading tool software to realize according to jtag instruction.These softwares have been finished the driving of jtag interface various command, only need the BSDL file of input JTAG chip and the script file of 51 mcu programming orders, just can be by the programing function of computer parallel port realization to chip.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (11)
1, a kind of 51 single-chip microcomputers is characterized in that in the system upgrade method, comprising:
A, boundary scan interface JTAG is set on 51 single-chip microcomputers;
B, utilize the public instruction of JTAG, realize the single-chip microcomputer that links to each other with the jtag interface programming of upgrading.
2, the method for claim 1 is characterized in that, the described jtag interface mode that is provided with comprises by Erasable Programmable Logic Device EPLD logic chip and providing.
3, the described method of claim 1 is characterized in that, also comprises, when programming, the operating voltage of 5V is transformed to the program voltage of 12V.
4, the method for claim 1 is characterized in that, the operation that the public instruction of the described JTAG of utilization is carried out comprises:
B1, single-chip microcomputer is carried out full wafer wipe;
B2, single-chip microcomputer is write object code.
5, method as claimed in claim 4 is characterized in that, comprises that also the object code to writing carries out verification.
6, method as claimed in claim 3 is characterized in that, comprises the builtin voltage mapping mode that adopts the MAX232 chip for described single-chip microcomputer provides the program voltage mode of 12V.
7, a kind of 51 single-chip microcomputers are in the system upgrade system, comprise 51 single-chip microcomputers, it is characterized in that, also comprise the jtag interface module: be connected with 51 single-chip microcomputers, be used to provide jtag interface, utilize level setting and the scan function of JTAG chain, realize the single-chip microcomputer that links to each other with the jtag interface chip is programmed and verification the chip exterior pin.
8, system as claimed in claim 7 is characterized in that, also comprises
Voltage control module: link to each other with the jtag interface module with 51 single-chip microcomputers, be used to control the switching of the operating voltage of the program voltage of 51 common single-chip microcomputer 12V and 5V or 3.3V;
Isolated controlling module: be used for ternary pin of isolating the singlechip CPU that is connected with the jtag interface module.
9, system as claimed in claim 7 is characterized in that, the jtag interface module comprises Erasable Programmable Logic Device EPLD logic chip, and wherein the address date hardware of the pin of EPLD and 51 single-chip microcomputers links to each other.
10, system as claimed in claim 8 is characterized in that, described voltage control module comprises, utilizes the builtin voltage conversion of MAX232 chip to realize exporting the program voltage of 12V.
11, system as claimed in claim 8 is characterized in that, described isolated controlling module comprises three-state buffer.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB200610035034XA CN100370423C (en) | 2006-04-12 | 2006-04-12 | Method and system for 51 one-chip computer on-system upgrading |
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| CNB200610035034XA CN100370423C (en) | 2006-04-12 | 2006-04-12 | Method and system for 51 one-chip computer on-system upgrading |
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| CN100370423C CN100370423C (en) | 2008-02-20 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461105C (en) * | 2007-02-01 | 2009-02-11 | 中兴通讯股份有限公司 | Update and repair method of intellectualized equipment and system thereof |
| CN101276285B (en) * | 2008-05-22 | 2010-06-09 | 中兴通讯股份有限公司 | Method and system for sintering telecommunications system level |
| CN107870776A (en) * | 2017-11-03 | 2018-04-03 | 北京锐安科技有限公司 | A kind of IPMC online upgradings method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2526908Y (en) * | 2001-06-14 | 2002-12-18 | 武汉大学 | Universal system board of single board computer based on PSD |
| CN1512336A (en) * | 2002-12-28 | 2004-07-14 | 深圳市中兴通讯股份有限公司 | 8051 monolithic system upgrading method and monitoring circuit |
| CN1492329A (en) * | 2003-09-09 | 2004-04-28 | 天津大学 | On-lin upgrading method for monolithic computer in monolithic computer system |
| CN1294489C (en) * | 2004-08-31 | 2007-01-10 | 四川长虹电器股份有限公司 | Program updating method of single chip processor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461105C (en) * | 2007-02-01 | 2009-02-11 | 中兴通讯股份有限公司 | Update and repair method of intellectualized equipment and system thereof |
| CN101276285B (en) * | 2008-05-22 | 2010-06-09 | 中兴通讯股份有限公司 | Method and system for sintering telecommunications system level |
| CN107870776A (en) * | 2017-11-03 | 2018-04-03 | 北京锐安科技有限公司 | A kind of IPMC online upgradings method and device |
| CN107870776B (en) * | 2017-11-03 | 2021-01-12 | 北京锐安科技有限公司 | IPMC online upgrading method and device |
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| CN100370423C (en) | 2008-02-20 |
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Effective date of registration: 20180427 Address after: London, England Patentee after: GW partnership Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. Effective date of registration: 20180427 Address after: California, USA Patentee after: Global innovation polymerization LLC Address before: London, England Patentee before: GW partnership Co.,Ltd. |
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