CN1787377A - BiCMOS high speed low consumption 2 frequency divider - Google Patents
BiCMOS high speed low consumption 2 frequency divider Download PDFInfo
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- CN1787377A CN1787377A CN 200510030477 CN200510030477A CN1787377A CN 1787377 A CN1787377 A CN 1787377A CN 200510030477 CN200510030477 CN 200510030477 CN 200510030477 A CN200510030477 A CN 200510030477A CN 1787377 A CN1787377 A CN 1787377A
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Abstract
This invention relates to a BiCMOS high speed low power loss band splitter composed of a first latch and a second latch with the circuit of combining a bipolar device and a CMOS device, in which, the bipolar device-the active load of the transistor is PMOS tube and the constant current source of the transistor is NMOS tube, the cross couple pair is an offset circuit of small offset current aiming at increasing the speed of the latch having the advantages of both the bipolar device and the CMOS device.
Description
Technical field
The present invention relates to a kind of BiCMOS high-speed low-power-consumption 2 frequency dividers, belong to the technical field of integrated circuit (IC) design and signal processing.
Background technology
In recent years, along with the development of radio frequency integrated circuit technology is rapid, many wireless communications products have been used in the daily life: 900MHz gsm mobile telephone, the above Intel of 1GHz Centrino TM processor chips and 2.4GHz Bluetooth communication product or the like.These products all will use phase-locked loop to come clocking without exception.Frequency divider is as the important component part of phase-locked loop, and its operating rate has directly determined the range of application of phase-locked loop.In today of information age, the high-speed communication development trend that is inevitable.Therefore, the operating rate of raising frequency divider is imperative.
Ambipolar (Bipolar) 2 frequency divider operation speed are fast, can improve the performance of HF switch effectively, but ambipolar 2 frequency divider power consumptions are bigger, and chip occupying area is also big, has increased the manufacturing cost of chip.And cmos device is low in energy consumption, and area is little, is convenient to integrated.So fast, low in energy consumption characteristics that the frequency divider of the BiCMOS circuit engineering that combines with cmos circuit based on ambipolar circuit is expected to have operating rate concurrently can satisfy the requirement of modern high-speed communications systems well.
Frequency divider has many kinds, and is wherein fastest with the trigger-type frequency divider operation.The structured flowchart of typical trigger-type frequency divider as shown in Figure 1.This frequency divider is formed by the cascade of two L latchs.This frequency divider can be realized 2 frequency divisions to input signal.
Latch is the elementary cell of frequency divider.Have a kind of traditional frequency divider to contain two L latchs that are made of bipolar device, its circuit structure as shown in Figure 2.There are problems in this frequency divider, and is big as power consumption, chip occupying area is bigger, and the manufacturing cost of chip is higher.
Summary of the invention
The objective of the invention is to release a kind of BiCMOS high-speed low-power-consumption 2 frequency dividers.This frequency divider combines the characteristics of Bipolar device and cmos device, have simple in structure, operating rate is fast, advantage such as low in energy consumption, and based on the chip of fraction frequency device of the present invention, its chip area footprints is few.By this frequency divider of cascade N level, can realize 2
NDivision function, N is a natural number.
Technical scheme of the present invention is that described high speed, low-power consumption BiCMOS2 frequency divider are made up of the first latch L1 and the second latch L2, two latchs are circuit that Bipolar device and cmos device combine, promptly the differential pair of two latchs and cross-couplings are to being the Bipolar device, transistorized active load is the PMOS pipe, transistorized constant-current source is the NMOS pipe, the cross-couplings of two latchs is intended to improve the operating rate of latch to being the biasing circuit of little bias current.
Now specifically describe technical scheme of the present invention in conjunction with the accompanying drawings.
A kind of BiCMOS high-speed low-power-consumption 2 frequency dividers are made up of the first latch L1 and the second latch L2, and the first latch L1 contains D
1End,
End, CLK
1End,
End, Vbias
1End, V
CC1End, Q
Out1End,
End and ground wire, V
CC1The end and ground cross between voltage source+end and voltage source one end, the second latch L
2Contain D
2End,
End, CLK
2End,
End, Vbias
2End, V
CC2End, Q
Out2End,
End and ground wire, V
CC2End and ground cross are between voltage source+end and voltage source one end, and the first latch L1 is connected the D of the first latch L1 with circuit between the second latch L2
1End,
End, Q
Out1End,
End, CLK
1The end and
End is respectively with the second latch L2's
End, Q
Out2End, D
2End,
End,
End and CLK
2End connects, the Vbias of the first latch L1
1The Vbias of the end and the second latch L2
2End is connected the CLK of the first latch L1 with the biased electrical pressure side
1The end and
End is the differential signal input of described frequency divider, the Q of the second latch L2
Out2The end and
End is 2 frequency division differential signal outputs of described frequency divider, it is characterized in that, the first latch L1 also contains the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the first transistor Q1, transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4, the 5th transistor Q5, the 6th transistor Q6, the first metal-oxide-semiconductor M1 and the 4th metal-oxide-semiconductor M4 are the NMOS pipes, the second metal-oxide-semiconductor M2 and the 3rd metal-oxide-semiconductor M3 are the PMOS pipes, the first transistor Q1, transistor seconds Q2, the 3rd transistor Q3, the 4th transistor Q4, the 5th transistor Q5 and the 6th transistor Q6 are the NPN pipes, the second latch L2 also contains the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 7th transistor Q7, the 8th transistor Q8, the 9th transistor Q9, the tenth transistor Q10, the 11 transistor Q11, the tenth two-transistor Q12, the 5th metal-oxide-semiconductor M5 and the 8th metal-oxide-semiconductor M8 are the NMOS pipes, the 6th metal-oxide-semiconductor M6 and the 7th metal-oxide-semiconductor M7 are the PMOS pipe, the 7th transistor Q7, the 8th transistor Q8, the 9th transistor Q9, the tenth transistor Q10, the 11 transistor Q11 and the tenth two-transistor Q12 are the NPN pipes, the circuit of the first latch L1 connects, the source electrode of the second metal-oxide-semiconductor M2, the source electrode of the 3rd metal-oxide-semiconductor M3, the collector electrode of transistor seconds Q2 and V
CC1End connects, the collector electrode of the drain electrode of the grid of the 3rd metal-oxide-semiconductor M3, the 3rd metal-oxide-semiconductor M3, the collector electrode of the 4th transistor Q4, the 6th transistor Q6, base stage and the Q of the 5th transistor Q5
Out1End connects, the collector electrode of the drain electrode of the grid of the second metal-oxide-semiconductor M2, the second metal-oxide-semiconductor M2, the collector electrode of the 3rd transistor Q3, the 5th transistor Q5, the base stage of the 6th transistor Q6 with
End connects, the base stage of the 3rd transistor Q3 and D
1End connects, the base stage of the 4th transistor Q4 with
End connects, and the emitter of the emitter of the 3rd transistor Q3 and the 4th transistor Q4 is connected the base stage of the first transistor Q1 and CLK with the collector electrode of the first transistor Q1
1End connects, the base stage of transistor seconds Q2 with
End connects, the emitter of the emitter of the first transistor Q1 and transistor seconds Q2 is connected with the drain electrode of the first metal-oxide-semiconductor M1, the source electrode of the first metal-oxide-semiconductor M1 is connected with ground wire, the emitter of the emitter of the 5th transistor Q5 and the 6th transistor Q6 is connected with the drain electrode of the 4th metal-oxide-semiconductor M4, grid and the Vbias of the grid of the first metal-oxide-semiconductor M1 and the 4th metal-oxide-semiconductor M4
1End connects, and the source electrode of the 4th metal-oxide-semiconductor M4 is connected with ground wire, and the circuit of the second latch L2 connects, the source electrode of the source electrode of the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, collector electrode and the V of the 8th transistor Q8
CC2End connects, the drain electrode of the grid of the 6th metal-oxide-semiconductor M6, the 6th metal-oxide-semiconductor M6, the collector electrode of the 9th transistor Q9, the collector electrode of the 11 transistor Q11, base stage and the Q of the tenth two-transistor Q12
Out2End connects, the collector electrode of the drain electrode of the grid of the 7th metal-oxide-semiconductor M7, the 7th metal-oxide-semiconductor M7, the collector electrode of the tenth transistor Q10, the tenth two-transistor Q12, the base stage of the 11 transistor Q11 with
End connects, the base stage of the 9th transistor Q9 and D
2End connects, the base stage of the tenth transistor Q10 with
End connects, and the emitter of the emitter of the 9th transistor Q9 and the tenth transistor Q10 is connected the base stage of the 7th transistor Q7 and CLK with the collector electrode of the 7th transistor Q7
2End connects, the base stage of the 8th transistor Q8 with
End connects, the emitter of the emitter of the 7th transistor Q7 and the 8th transistor Q8 is connected with the drain electrode of the 5th metal-oxide-semiconductor M5, the source electrode of the 5th metal-oxide-semiconductor M5 is connected with ground wire, the emitter of the emitter of the 11 transistor Q11 and the tenth two-transistor Q12 is connected with the drain electrode of the 8th metal-oxide-semiconductor M8, grid and the Vbias of the grid of the 5th metal-oxide-semiconductor M5 and the 8th metal-oxide-semiconductor M8
2End connects, and the source electrode of the 8th metal-oxide-semiconductor M8 is connected with ground wire.
The present invention can can realize any 2 by this frequency divider of cascade N level simultaneously by 2 frequency divisions of simple circuit configuration realization to differential input signal
NThe system division function, N is a natural number.Compare with 2 traditional frequency dividers, the invention has the advantages that: existing is that 2 frequency dividers of the BiCMOS of 300 μ A and the BiCMOS technology manufacturing of adopting 0.8 μ m are that example illustrates it with quiescent bias current.
1, operating rate is fast
The operating rate of 2 frequency dividers of the present invention is times of traditional ambipolar 2 frequency dividers, and the high operation speed of 2 frequency dividers of structure of the present invention is 2.2GHz, and the high operation speed of traditional ambipolar 2 frequency dividers is 1GHz.
2, low in energy consumption
The low-power consumption of 2 frequency dividers of the present invention characterizes with following index: the frequency power consumption ratio of 2 frequency dividers of the present invention is 0.68mW/GHz, and the power consumption frequency ratio of traditional double polar form 2 frequency dividers is 1.5mW/GHz.
3, chip area footprints is little
When the integrated circuit of 2 frequency dividers of making BiCMOS, frequency divider of the present invention takies area of chip and has only 2 frequency dividers of traditional double polar form to take 20%～25% of area of chip.
Description of drawings
Fig. 1 is the structured flowchart of traditional ambipolar 2 frequency division frequency dividers.
Fig. 2 is the circuit diagram of traditional ambipolar 2 frequency division frequency dividers.
Fig. 3 is the circuit diagram of BiCMOS high-speed low-power-consumption 2 frequency dividers of the present invention.
Fig. 4 is the input-output characteristic curve of BiCMOS high-speed low-power-consumption 2 frequency dividers of the present invention.
Embodiment
Technical scheme of the present invention is exactly a specific embodiment, just repeats no more embodiment here.Below the detailed operation principle of introducing technical solution of the present invention.The circuit diagram of BiCMOS high-speed low-power-consumption 2 frequency dividers of the present invention as shown in Figure 3.The bias voltage source end is the grid step voltage control end of the first metal-oxide-semiconductor M1, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 8th metal-oxide-semiconductor M8, and the size of its magnitude of voltage is 800mV.When the difference input signal, when promptly the clock signal loading is to the differential signal input, if 2 frequency dividers
1.86 volts of forward peak values that divide the clock signal with
1.74 volts of the negative peak of clock signal, the first transistor Q1 and the 8th transistor Q8 open, and transistor seconds Q2 and the 7th transistor Q7 end.For the first latch L1, the first transistor Q1 opens, and the signal trace differential pair that the 3rd transistor Q3 and the 4th transistor Q4 are formed enters operating state, and the second latch L2 is through this signal trace differential pair output differential signal.This mode of operation is referred to as tracing mode.For the second latch L2, the 8th transistor Q8 opens, the signal latch differential pair that the 11 transistor Q11 and the tenth two-transistor Q12 are formed enters operating state, and the differential signal of second latch L2 output still keeps original state behind this differential pair (positive feedback).This mode of operation is referred to as latch mode.Otherwise, when this 2 frequency divider
1.74 volts of negative peak and
During 1.86 volts of forward peak values, the first transistor Q1 and the 8th transistor Q8 end, and transistor seconds Q2 and the 7th transistor Q7 open.The first latch L1 is in latch mode, and the second latch L2 is in tracing mode.Because the mode of operation of two latchs is conversion alternately: the first latch L1 is in latch mode, the second latch L2 is in tracing mode, the first latch L1 is in tracing mode, the second latch L2 is in latch mode, and the forward output of the second latch L2 is connected with the reverse input end of the first latch L1, guaranteed the vibration of frequency divider internal signal, therefore 2 frequency dividers of the present invention can be realized 2 division function under the control of differential clock signal, and 2 frequency division differential output signals obtain from 2 frequency division differential signal outputs.The peak-to-peak value of differential input signal is about 3.26 volts-3.44 volts, and the peak-to-peak value of 2 frequency division differential output signals is about 1.74 volts-1.86 volts.The oscillogram of differential input signal and 2 frequency division differential output signals is seen Fig. 4.
In whole 2 frequency dividers, made full use of the technical characterstic of BiCMOS: replaced load resistance in traditional double polar form 2 frequency dividers as the load pipe with the PMOS pipe, replaced the constant-current source that contains bipolar device and resistance in traditional double polar form 2 frequency dividers with the NMOS pipe as constant-current source, like this, when the integrated circuit of 2 frequency dividers of making BiCMOS, can save very big chip area.The chip area of 2 frequency dividers of the present invention is about 0.2 μ m
2, the chip area of traditional double polar form 2 frequency dividers is about 0.98 μ m
2, the chip area footprints of 2 frequency dividers of the present invention can save 75% to 80%.
In addition, the BiCMOS technology guarantees that 2 frequency dividers of the present invention have following excellent properties: operating rate is fast and low in energy consumption.
2 frequency dividers of the present invention are suitable for doing 2 of N level cascade
NFrequency divider is used in the operating rate that can significantly improve phase-locked loop in the phase-locked loop.
Claims (1)
1, a kind of BiCMOS high-speed low-power-consumption 2 frequency dividers are made up of first latch (L1) and second latch (L2), and first latch (L1) contains D
1End,
End, CLK
1End,
End, Vbias
1End, V
CC1End, Q
Out1End,
End and ground wire, V
CC1End and ground cross are between voltage source+end and voltage source-end, and second latch (L2) contains D
2End,
End, CLK
2End,
End, Vbias
2End, V
CC2End, Q
Out2End,
End and ground wire, V
CC2End and ground cross are between voltage source+end and voltage source-end, and first latch (L1) is connected the D of first latch (L1) with circuit between second latch (L2)
1End,
End, Q
Out1End,
End, CLK
1The end and
End is respectively with second latch (L2)
End, Q
Out2End, D
2End,
End,
End and CLK
2End connects, the Vbias of first latch (L1)
1The Vbias of end and second latch (L2)
2End is connected the CLK of first latch (L1) with the biased electrical pressure side
1The end and
End is the differential signal input of described frequency divider, the Q of second latch (L2)
Out2The end and
End is 2 frequency division differential signal outputs of described frequency divider, it is characterized in that, first latch (L1) also contains first metal-oxide-semiconductor (M1), second metal-oxide-semiconductor (M2), the 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the first transistor (Q1), transistor seconds (Q2), the 3rd transistor (Q3), the 4th transistor (Q4), the 5th transistor (Q5), the 6th transistor (Q6), first metal-oxide-semiconductor (M1) and the 4th metal-oxide-semiconductor (M4) are the NMOS pipes, second metal-oxide-semiconductor (M2) and the 3rd metal-oxide-semiconductor (M3) are the PMOS pipes, the first transistor (Q1), transistor seconds (Q2), the 3rd transistor (Q3), the 4th transistor (Q4), the 5th transistor (Q5) and the 6th transistor (Q6) are the NPN pipes, second latch (L2) also contains the 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6), the 7th metal-oxide-semiconductor (M7), the 8th metal-oxide-semiconductor (M8), the 7th transistor (Q7), the 8th transistor (Q8), the 9th transistor (Q9), the tenth transistor (Q10), the 11 transistor (Q11), the tenth two-transistor (Q12), the 5th metal-oxide-semiconductor (M5) and the 8th metal-oxide-semiconductor (M8) are the NMOS pipes, the 6th metal-oxide-semiconductor (M6) and the 7th metal-oxide-semiconductor (M7) are the PMOS pipe, the 7th transistor (Q7), the 8th transistor (Q8), the 9th transistor (Q9), the tenth transistor (Q10), the 11 transistor (Q11) and the tenth two-transistor (Q12) are the NPN pipes, the circuit of first latch (L1) connects, the source electrode of second metal-oxide-semiconductor (M2), the source electrode of the 3rd metal-oxide-semiconductor (M3), the collector electrode and the V of transistor seconds (Q2)
CC1End connects, the collector electrode of the drain electrode of the grid of the 3rd metal-oxide-semiconductor (M3), the 3rd metal-oxide-semiconductor (M3), the collector electrode of the 4th transistor (Q4), the 6th transistor (Q6), the base stage and the Q of the 5th transistor (Q5)
Out1End connects, the collector electrode of the drain electrode of the grid of second metal-oxide-semiconductor (M2), second metal-oxide-semiconductor (M2), the collector electrode of the 3rd transistor (Q3), the 5th transistor (Q5), the base stage of the 6th transistor (Q6) with
End connects, the base stage and the D of the 3rd transistor (Q3)
1End connects, the base stage of the 4th transistor (Q4) with
End connects, and the emitter of the emitter of the 3rd transistor (Q3) and the 4th transistor (Q4) is connected the base stage and the CLK of the first transistor (Q1) with the collector electrode of the first transistor (Q1)
1End connects, the base stage of transistor seconds (Q2) with
End connects, the emitter of the emitter of the first transistor (Q1) and transistor seconds (Q2) is connected with the drain electrode of first metal-oxide-semiconductor (M1), the source electrode of first metal-oxide-semiconductor (M1) is connected with ground wire, the emitter of the emitter of the 5th transistor (Q5) and the 6th transistor (Q6) is connected with the drain electrode of the 4th metal-oxide-semiconductor (M4), the grid and the Vbias of the grid of first metal-oxide-semiconductor (M1) and the 4th metal-oxide-semiconductor (M4)
1End connects, and the source electrode of the 4th metal-oxide-semiconductor (M4) is connected with ground wire, and the circuit of second latch (L2) connects, the source electrode of the source electrode of the 6th metal-oxide-semiconductor (M6), the 7th metal-oxide-semiconductor (M7), the collector electrode and the V of the 8th transistor (Q8)
CC2End connects, the drain electrode of the grid of the 6th metal-oxide-semiconductor (M6), the 6th metal-oxide-semiconductor (M6), the collector electrode of the 9th transistor (Q9), the collector electrode of the 11 transistor (Q11), the base stage and the Q of the tenth two-transistor (Q12)
Out2End connects, the collector electrode of the drain electrode of the grid of the 7th metal-oxide-semiconductor (M7), the 7th metal-oxide-semiconductor (M7), the collector electrode of the tenth transistor (Q10), the tenth two-transistor (Q12), the base stage of the 11 transistor (Q11) with
End connects, the base stage and the D of the 9th transistor (Q9)
2End connects, the base stage of the tenth transistor (Q10) with
End connects, and the emitter of the emitter of the 9th transistor (Q9) and the tenth transistor (Q10) is connected the base stage and the CLK of the 7th transistor (Q7) with the collector electrode of the 7th transistor (Q7)
2End connects, the base stage of the 8th transistor (Q8) with
End connects, the emitter of the emitter of the 7th transistor (Q7) and the 8th transistor (Q8) is connected with the drain electrode of the 5th metal-oxide-semiconductor (M5), the source electrode of the 5th metal-oxide-semiconductor (M5) is connected with ground wire, the emitter of the emitter of the 11 transistor (Q11) and the tenth two-transistor (Q12) is connected with the drain electrode of the 8th metal-oxide-semiconductor (M8), the grid and the Vbias of the grid of the 5th metal-oxide-semiconductor (M5) and the 8th metal-oxide-semiconductor (M8)
2End connects, and the source electrode of the 8th metal-oxide-semiconductor (M8) is connected with ground wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510030477 CN1787377A (en) | 2005-10-13 | 2005-10-13 | BiCMOS high speed low consumption 2 frequency divider |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510030477 CN1787377A (en) | 2005-10-13 | 2005-10-13 | BiCMOS high speed low consumption 2 frequency divider |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931396B (en) * | 2009-06-22 | 2012-04-25 | 杭州中科微电子有限公司 | Prescaler with clock-controlled transistor |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| CN102130678B (en) * | 2010-01-12 | 2016-01-27 | 东南大学 | Low-voltage static frequency divider integrated circuit chip |
| CN110783333A (en) * | 2018-07-24 | 2020-02-11 | 三星电子株式会社 | Integrated circuit device including latch with cross-coupled structure |
-
2005
- 2005-10-13 CN CN 200510030477 patent/CN1787377A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931396B (en) * | 2009-06-22 | 2012-04-25 | 杭州中科微电子有限公司 | Prescaler with clock-controlled transistor |
| CN102130678B (en) * | 2010-01-12 | 2016-01-27 | 东南大学 | Low-voltage static frequency divider integrated circuit chip |
| CN103281071A (en) * | 2013-06-21 | 2013-09-04 | 上海中科高等研究院 | Latch and frequency divider circuit including same |
| CN103281071B (en) * | 2013-06-21 | 2016-04-13 | 中国科学院上海高等研究院 | Latch and comprise the divider circuit of this latch |
| CN110783333A (en) * | 2018-07-24 | 2020-02-11 | 三星电子株式会社 | Integrated circuit device including latch with cross-coupled structure |
| CN110783333B (en) * | 2018-07-24 | 2024-07-09 | 三星电子株式会社 | Integrated circuit device including latches with cross-coupled structures |
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