CN1633028B - Phase lock loop and loop filter therefor - Google Patents
Phase lock loop and loop filter therefor Download PDFInfo
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- CN1633028B CN1633028B CN 200510002857 CN200510002857A CN1633028B CN 1633028 B CN1633028 B CN 1633028B CN 200510002857 CN200510002857 CN 200510002857 CN 200510002857 A CN200510002857 A CN 200510002857A CN 1633028 B CN1633028 B CN 1633028B
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Abstract
This invention relates to a phase-lock loop and its applied loop filter including a first resistor, a first capacitor and an amplifier with a specific gain value, among which, the amplifier has an input end coupled to the input and output ends of the loop filter by the first resistor, the amplifier has an output end coupled to the input end of the amplifier via the first capacitor.
Description
Technical field
The present invention relates to a kind of loop filter, particularly relate to a kind of the have phase-locked loop of the little loop filter framework of quick setting and area and the loop filter of its application.
Background technology
In general, in electronics or computer system, all has very important sequential requirement.Therefore, offer the cyclic pulse signal of system, must be accurately synchronous with reference burst signal.Phase-locked loop (Phase Locked Loop is called for short PLL) is a kind of circuit that is widely used, and its frequency that can accurately control output signal frequency and input signal is reached synchronously.The phase-locked loop usually is applied to frequency synthesizer, multiplier, divider, single and multi-pulse signal generator, pulse signal restore circuit and wireless communication apparatus or the like.
Fig. 1 is a kind of circuit block diagram that has known phase-locked loop now.Seeing also shown in Figure 1ly, for example is the output of the oscillator 101 of quartz (controlled) oscillator, is to be coupled to frequency divider 103, and is coupled to phase detecting circuit 105 by frequency divider 103.Phase detecting circuit 105 can be operated loop filter 109 by charge pump circuit 107.The output of loop filter 109 is the output OUT that are coupled to the phase-locked loop, and is coupled to voltage controlled oscillator 111.And voltage controlled oscillator 111 is understood according to loop filter 109, and frequency divider 113 is delivered in output, and the output of frequency divider 113, can feed back to the input of phase detecting circuit 105.
Loop filter 109 shown in Fig. 1 is second order loop filters.In detail, the exponent number of loop filter is to decide according to the electric capacity number that is had.In loop filter 109, comprised capacitor C p and Cz, and resistance R z.Wherein, capacitor C p is called limit electric capacity again, is to be used for providing a limit in system.The wherein end of capacitor C p couples the input and the output of loop filter 109, and the other end is ground connection then.In addition, resistance R z and capacitor C z provide a zero point in system.Wherein, the end of resistance R z is input and the output that couples loop filter 109, and the other end is then by capacitor C z ground connection.
In general, for can be produced before limit zero point.Therefore, the capacitance of capacitor C z can be designed to much larger than the capacitance of capacitor C p, so that the shared area of capacitor C z is quite big.And, zero point energy is produced before limit in order to reduce the capacitance of capacitor C z, therefore just develop and relevant technology.
Fig. 2 is a kind of circuit block diagram of phase-locked loop of improvement.See also shown in Figure 2ly, the phase-locked loop shown in it is in phase-locked loop shown in Figure 1, disposes charge pump circuit 201 in addition.Wherein, the operation of charge pump circuit 201, just opposite with charge pump circuit 107.That is to say that when 107 pairs of loop filters 109 of charge pump circuit charged, then 201 of charge pump circuits discharged capacitor C z, vice versa.So, just can reduce the electric current that flows through capacitor C z, so that can reduce the capacitance of capacitor C z.
Yet there is individual shortcoming phase-locked loop as shown in Figure 2.Owing in phase-locked loop shown in Figure 2, disposed charge pump circuit 201 in addition, though reach the shared space of meter reduction capacitor C z so that can reduce the capacitance of capacitor C z.But, but increased charge pump circuit 201, and also can exist the problem of coupling between charge pump circuit 107 and 201.
This shows that the loop filter of above-mentioned existing phase-locked loop and its application obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.The problem that exists for the loop filter that solves phase-locked loop and its application, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that the loop filter of above-mentioned existing phase-locked loop and its application exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, loop filter in the hope of the phase-locked loop of founding a kind of new structure and its application, can improve the loop filter of general existing phase-locked loop and its application, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome the defective that existing phase-locked loop exists, and a kind of phase-locked loop of new structure is provided, technical problem to be solved is to make it that less circuit area can be arranged, thereby is suitable for practicality more.
Another object of the present invention is to, overcome the defective that existing loop filter exists, and a kind of loop filter of new structure is provided, technical problem to be solved is to make its reaction speed that can increase circuit, thereby is suitable for practicality more.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The present invention provides a kind of loop filter, and it has an input and an output, and has also comprised one first resistance and one second resistance.In addition, the present invention has also comprised a nmos pass transistor, and its source terminal is by first grounding through resistance, and its gate terminal then is coupled to input and this output of loop filter by second resistance.Between the gate terminal and drain electrode end of nmos pass transistor, be cross-over connection one first electric capacity.In addition, the present invention more comprises a PMOS transistor and the 2nd PMOS transistor that is used for as current mirroring circuit.Wherein, the drain electrode end of a PMOS transistor drain end and nmos pass transistor couples each other, and source terminal then couples a voltage source.In addition, the 2nd PMOS transistor drain end is by a current source ground connection, and its source terminal is to couple voltage source equally, and its gate terminal then couples each other with the transistorized gate terminal of a PMOS, and couples the 2nd PMOS transistor drain end.
According to another embodiment of the present invention, provide a kind of loop filter, equally also be to have an input and an output, and comprise first nmos pass transistor and second nmos pass transistor, to be combined into current mirroring circuit.Wherein, the source terminal ground connection of first nmos pass transistor, and the source terminal ground connection of second nmos pass transistor, its drain electrode end is to be coupled to a common electric potential by a current source, couple each other and its gate terminal is a gate terminal with first nmos pass transistor, and be coupled to the drain electrode end of second nmos pass transistor.In addition, the present invention also comprises the PMOS transistor, its drain electrode end is that the drain electrode end with first nmos pass transistor couples each other, and its source terminal is to be connected to common electric potential by one first resistance, and gate terminal then is connected to input and this output of loop filter by second resistance.In addition, between PMOS transistor drain end and gate terminal, go back cross-over connection one first electric capacity.
From another viewpoint, the invention provides a kind of loop filter, comprised one first resistance, one first electric capacity and amplifier with certain gain value.Wherein, amplifier also has an amplifier in, is input and the output that is coupled to loop filter by first resistance.In addition, amplifier also has an amplifier out, and it is coupled to amplifier in by first electric capacity.
From another viewpoint, the present invention provides a kind of phase-locked loop, and it has a loop filter, and this loop filter has then comprised one first resistance, one first electric capacity and the amplifier with certain gain value.Wherein, amplifier also has an amplifier in, is input and the output that is coupled to loop filter by first resistance.In addition, amplifier also has an amplifier out, and it is coupled to amplifier in by first electric capacity.
Through as can be known above-mentioned, the invention relates to the loop filter of a kind of phase-locked loop and its application, this loop filter has comprised one first resistance, one first electric capacity and the amplifier with certain gain value.Wherein, amplifier also has an amplifier in, is input and the output that is coupled to loop filter by first resistance.In addition, amplifier also has an amplifier out, and it is coupled to amplifier in by first electric capacity.
By technique scheme, the loop filter of phase-locked loop of the present invention and its application has following advantage at least:
1, since the present invention with the electric capacity in the loop filter across between the input and output of amplifier, in amplifier input terminal, can cause the Miller effect.Therefore, the present invention can use little electric capacity, just can obtain big capacitance, so that the present invention can reduce the occupied space of electric capacity significantly.
2, because the present invention can use less electric capacity, therefore the time of charging and discharge can shorten, so that can accelerate the circuit speed of phase-locked loop of the present invention.
In sum, can there be less circuit area the phase-locked loop of special construction of the present invention.The loop filter of special construction of the present invention can increase the reaction speed of circuit.It has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it all has bigger improvement on product or function, have large improvement technically, and produced handy and practical effect, and the loop filter of more existing phase-locked loop and its application has the multinomial effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is a kind of circuit block diagram that has known phase-locked loop now.
Fig. 2 is a kind of circuit block diagram of phase-locked loop of improvement.
Fig. 3 is the circuit block diagram according to a kind of phase-locked loop of one embodiment of the invention.
Fig. 4 is a kind of circuit diagram of charge pump circuit.
Fig. 5 is a kind of schematic diagram of Miller equivalent electric circuit.
Fig. 6 A is the circuit diagram according to a kind of loop filter of first embodiment of the invention.
Fig. 6 B is the circuit diagram according to a kind of loop filter of second embodiment of the invention.
Fig. 7 is the circuit block diagram according to the phase-locked loop of another embodiment of the present invention.
Fig. 8 is the circuit block diagram according to a kind of phase-locked loop of another embodiment of the present invention.
101,301: oscillator 103,113,303,313: frequency divider
105,305: phase detecting circuit 107,307: charge pump circuit
109,309: loop filter 330,340: loop filter
111,311: voltage controlled oscillator 320: circuit is provided zero point
401,403: switch 601,623,625:NMOS transistor
603,605,621:PMOS transistor 607,627: current source
Ra, Rp, Rz, Ra: resistance Cp, Cz, Ca, Cc: electric capacity
C1: input capacitance C2: output capacitance
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the phase-locked loop that foundation the present invention is proposed and its embodiment of loop filter, structure, feature and the effect thereof of its application, describe in detail as after.
Fig. 3 is the circuit block diagram according to a kind of phase-locked loop of one embodiment of the invention.See also shown in Figure 3ly, the output of oscillator 301 is to deliver to frequency divider 303, and is coupled to phase detecting circuit 305 by frequency divider 303.Phase detecting circuit 305 is actions of carrying out charge or discharge by 307 pairs of loop filters of charge pump circuit 309.The output B of loop filter 309 is the output OUT that are coupled to phase-locked loop of the present invention, and is coupled to the input of voltage controlled oscillator 311.And voltage controlled oscillator 311 is according to loop filter 309, and output is coupled to frequency divider 313, and is coupled to the input of phase detecting circuit 305 by frequency divider 313.
Wherein, oscillator 301 can be a quartz (controlled) oscillator for example, is to be used for producing reference burst signal CLK0.Frequency divider 303 then with the frequency of reference burst signal CLK0 divided by a preset value after, and output comparison pulse signal CLKC is to phase detecting circuit 305.Phase detecting circuit 305 can compare the phase place of comparison pulse signal CLKC and the phase place of a pulse signal CLKA.When the leading comparison pulse signal CLKC of the phase place of pulse signal CLKA, phase detecting circuit 305 can output anticipating signal D to charge pump circuit 307.And if during the phase place of the phase lag comparison pulse signal CLKC of pulse signal CLKA, then phase detecting circuit will be exported backward signal U to charge pump circuit 307.
Fig. 4 is a kind of circuit diagram of charge pump circuit.See also shown in Figure 4ly, in charge pump circuit 307, comprised switch 401 and 403.And whether conducting of switch 401 and 403 is to decide according to phase detecting circuit 305.When if phase detecting circuit 305 detects the phase place of the leading comparison pulse signal CLKC of the phase place of pulse signal CLKA, will send anticipating signal D to charge pump circuit 307, with control switch 403 conductings.After switch 403 conductings, electric current I will be extracted out from loop filter 309, just loop filter 309 is discharged.
Otherwise,, then can send backward signal U to charge pump circuit 307, with control switch 401 conductings if phase detecting circuit 305 detects the phase lag of pulse signal CLKA when giving the phase place of comparison pulse signal CLKC.When switch 401 conductings, charge pump circuit 307 will be sent electric current I to loop filter 309, that is to say the action that charge pump circuit 307 meetings are charged to loop filter 309.So, will make loop filter 309 produce output pulse signal CLKOUT to loop filter 309 charge/discharge that hockets.
Please later consult shown in Figure 3ly, after output pulse signal CLKOUT produced, the output OUT from phase-locked loop of the present invention was output except meeting, also can be sent to voltage controlled oscillator 311 simultaneously.And voltage controlled oscillator 311 is understood according to output pulse signal CLKOUT, and produces pulse signal CLKB, and delivers to frequency divider 313 and carry out frequency division.After frequency divider 313 carries out frequency division with pulse signal CLKB, will produce pulse signal CLKA, and feed back to phase detecting circuit 305.And such feedback action just can make the frequency of output pulse signal CLKOUT and the Frequency Synchronization of reference burst signal CLKC.
In loop filter 309, be to comprise circuit 320 is provided zero point.As its name suggests, providing circuit 320 zero point is to be used to provide zero point.In the present invention, providing circuit 320 zero point is the amplifiers 322 that comprised resistance R z, capacitor C c and had yield value K.At this, the present invention utilizes capacitor C c and amplifier 322 and forms capacitor C z among Fig. 1.Yet capacitor C c and amplifier 322 area occupied are still less than the shared area of capacitor C z.The wherein input of amplifier 322 is input A and the output B that are coupled to loop filter 309 by resistance R z, and capacitor C c then is output and the input that is connected across amplifier 322.
According to the Miller theorem, amplifier 322 and capacitor C c can equivalence be equivalent electric circuit as shown in Figure 5.In Fig. 5, the input capacitance C1 of amplifier 322 can equal (1-K) Cc.And output capacitance C2 then can equal (1-1/K) Cc, and wherein K can be negative value, and can utilize the negative feedback amplifier circuit to obtain.Therefore, have the knack of this skill person, just can utilize very little capacitor C c, and obtain very big capacitance as long as adjust the yield value K of amplifier 322.
Following the present invention has provided two embodiment, and the actual execution mode of circuit at zero point is described.
Fig. 6 A is the circuit diagram according to a kind of loop filter of first embodiment of the invention.See also shown in Fig. 6 A, provide in the circuit 320, comprised nmos pass transistor 601, PMOS transistor 603 and 605 at zero point.Wherein, first source of nmos pass transistor 601/drain electrode end is by resistance R 1 ground connection, and its gate terminal is to be coupled on the input A and output B of loop filter 309 by resistance R 2, and between gate terminal and its drain electrode end, also disposes capacitor C z.
In addition, PMOS transistor 603 and 605 is to be combined into current mirroring circuit.Wherein, the drain electrode end of PMOS transistor 603 is the drain electrode ends that are coupled to nmos pass transistor 601, and its source terminal then couples a voltage source, and its gate terminal then couples each other with the gate terminal of PMOS transistor 605.And the source terminal of PMOS transistor 605 is identical with the source terminal of PMOS transistor 603, is coupled to a voltage source, and the drain electrode end of PMOS transistor 605 then is coupled to the gate terminal of PMOS transistor 605, and by current source 607 ground connection.In the present invention, the sense of current of current source 607 be from PMOS transistor 605 to earth terminal, and its current value I c is for adjusting.
In the present embodiment, transistor 603 and 605 is current-mirror structure, so that current value I c can be copied to the drain electrode end of transistor 603.In addition, the resistance value of resistance R 1 adds the resistance value of resistance R 2, can equal the resistance value of the resistance R z of Fig. 3.Therefore, as long as the resistance value between adjustment resistance R 1 and the R2 just can guarantee that nmos pass transistor 601 is operated in active region (Active Region).
Fig. 6 B is the circuit diagram according to a kind of loop filter of second embodiment of the invention.See also shown in Figure 6ly, provide in the circuit 320, comprised PMOS transistor 621, nmos pass transistor 623 and 625 at zero point.Wherein, the source terminal ground connection of nmos pass transistor 623, gate terminal then couples each other with the gate terminal of nmos pass transistor 625.The source terminal of nmos pass transistor 625 equally also is a ground connection, and drain electrode end is to be coupled to a voltage source by current source 627, and is coupled to the gate terminal of nmos pass transistor 625, so that nmos pass transistor 623 and 625 is the structures that form current mirror.Wherein, the current value I c of current source 627 equally also is adjustable, and the sense of current is the direction towards transistor 625.
In addition, the source terminal of PMOS transistor 621 is to be coupled to voltage source by resistance R 1, and its gate terminal then is coupled to the input A and the output B of loop filter by resistance R 2.And the drain electrode end of PMOS transistor 621 is the drain electrode ends that are coupled to nmos pass transistor 623, and is coupled to the gate terminal of PMOS transistor 621 by capacitor C z.Similarly, the resistance value of resistance R 1 adds the resistance value of resistance R 2, can equal the resistance value of the resistance R z of Fig. 3.Therefore, as long as the resistance value between adjustment resistance R 1 and the R2 just can guarantee that PMOS transistor 621 is operated in active region.
More than though the structure of two kinds of loop filters is provided, do not limit the present invention with this.Haveing the knack of this skill person ought know, the emphasis that the present invention is main is to provide zero point the electric capacity in the circuit to be connected across between the input and output of amplifier, and causes the Miller effect.Therefore, any mode and the circuit that can realize this result is all within the scope of institute of the present invention desire protection.
Fig. 7 is the circuit block diagram according to the phase-locked loop of another embodiment of the present invention.Disclosed phase-locked loop in Fig. 7 is to revise from phase-locked loop shown in Figure 3.Its difference is, in loop filter 309, adding capacitor C p in addition, the one end couples the input A of loop filter 330, and be coupled to the input of amplifier 322 by resistance R z, it is the gate terminal of the nmos pass transistor 601 of Fig. 6 A or the gate terminal of the PMOS transistor 621 of Fig. 6 B for example.
The loop filter 330 that present embodiment provided is second order loop filters.It except providing zero point, more can provide a limit in the frequency response of system.
Fig. 8 is the circuit block diagram according to a kind of phase-locked loop of another embodiment of the present invention.Disclosed phase-locked loop in Fig. 8 then is to revise from phase-locked loop shown in Figure 7.Its difference is, in loop filter 340, has increased resistance R a and capacitor C a more.Wherein, the end of resistance R a couples the output B of loop filter 340, and the other end then is coupled to the input of amplifier 322 by resistance R z, is the gate terminal of nmos pass transistor 601 of for example Fig. 6 A or the gate terminal of the PMOS transistor 621 of Fig. 6 B.And the end of capacitor C a is output B and the resistance R a that couples loop filter 340, and the other end is ground connection then.And the disclosed loop filter 340 of present embodiment is three rank loop filters.
In sum because in loop filter provided by the present invention, be with electric capacity across the input of amplifier with export between, and cause the Miller effect.Therefore, the present invention can use less electric capacity to obtain bigger capacitance, so that circuit area of the present invention can dwindle, but integrated circuit still can normal running.In addition because the present invention can use less electric capacity so that the time of charging and discharge can shorten.Therefore, the circuit speed of phase-locked loop provided by the present invention can promote significantly.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the structure that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (12)
1. loop filter is characterized in that it comprises:
One first resistance:
One first electric capacity;
One amplifier, has a yield value, and have an amplifier in and an amplifier out, wherein this amplifier in is input and the output that is coupled to this loop filter by this first resistance, this amplifier out then is coupled to this amplifier in by this first electric capacity, this first resistance is made up of in the mode of series connection one second resistance and one the 3rd resistance, this amplifier is a nmos pass transistor, its source terminal is by this second grounding through resistance, its gate terminal then is coupled to the input of this loop filter and the output of this loop filter by the 3rd resistance, and the two ends of this first electric capacity couple the gate terminal and the drain electrode end of this nmos pass transistor respectively;
One the one PMOS transistor, the drain electrode end of its drain electrode end and this nmos pass transistor couples each other, and the transistorized source terminal of a PMOS then couples a voltage source; And
One the 2nd PMOS transistor, its drain electrode end are by a current source ground connection, and its source terminal is to couple this voltage source, and its gate terminal and the transistorized gate terminal of a PMOS couple each other, and couple the 2nd PMOS transistor drain end.
2. loop filter according to claim 1, it is characterized in that more comprising one second electric capacity, wherein an end couples the input of this loop filter, and is coupled to the gate terminal of this nmos pass transistor by the 3rd resistance, and the other end of this second electric capacity is ground connection then.
3. loop filter according to claim 2 is characterized in that more comprising:
One the 4th resistance, wherein an end couples the input of this loop filter, and is coupled to the gate terminal of this nmos pass transistor by the 3rd resistance, and the other end of the 4th resistance then couples the output of this loop filter; And
One the 3rd electric capacity, wherein an end couples the output of this loop filter, and the other end is ground connection then.
4. loop filter is characterized in that it comprises:
One first resistance:
One first electric capacity;
One amplifier, has a yield value, and have an amplifier in and an amplifier out, wherein this amplifier in is input and the output that is coupled to this loop filter by this first resistance, and this amplifier out then is coupled to this amplifier in by this first electric capacity;
One first nmos pass transistor, its source terminal ground connection; And
One second nmos pass transistor, its source terminal ground connection, its drain electrode end is to be coupled to a common electric potential by a current source, and being gate terminal with this first nmos pass transistor, its gate terminal couples each other, and be coupled to the drain electrode end of this second nmos pass transistor, and this amplifier is a PMOS transistor, its drain electrode end is that the drain electrode end with this first nmos pass transistor couples each other, this first resistance is made up of in the mode of series connection one second resistance and one the 3rd resistance, this second resistance is in order to be connected to this common electric potential with the transistorized source terminal of this PMOS, and the 3rd resistance is in order to be connected to the transistorized gate terminal of this PMOS the input of this loop filter and the output of this loop filter, and an end of this first electric capacity couples this PMOS transistor drain end, and the other end then couples the transistorized gate terminal of this PMOS.
5. loop filter according to claim 4, it is characterized in that more comprising one second electric capacity, wherein an end couples the input of this loop filter, and is coupled to the transistorized gate terminal of this PMOS by the 3rd resistance, and the other end of this second electric capacity is ground connection then.
6. loop filter according to claim 5 is characterized in that more comprising:
One the 4th resistance, wherein an end couples the input of this loop filter, and is coupled to the transistorized gate terminal of this PMOS by the 3rd resistance, and the other end of the 4th resistance then couples the output of this loop filter; And
One the 3rd electric capacity, wherein an end couples the output of this loop filter, and the other end is ground connection then.
7. phase-locked loop is characterized in that it comprises:
One oscillator is in order to export a reference burst signal;
One first frequency divider in order to this reference burst signal is carried out frequency division, and produces one first pulse signal;
One phase detecting circuit in order to this first pulse signal and one second pulse signal are compared, and produces a comparative result;
One charge pump circuit is to receive this comparative result;
One loop filter couples the output of this charge pump circuit, and wherein this charge pump circuit is to control this loop filter according to this comparative result to charge and discharge the two one of them, and this loop filter comprises:
One first resistance:
One first electric capacity;
One amplifier, has a yield value, and have an amplifier in and an amplifier out, wherein this amplifier in is input and the output that is coupled to this loop filter by this first resistance, this amplifier out then is coupled to this amplifier in by this first electric capacity, this first resistance is made up of in the mode of series connection one second resistance and one the 3rd resistance, this amplifier is a nmos pass transistor, its source terminal is by this second grounding through resistance, its gate terminal then is coupled to the input of this loop filter and the output of this loop filter by the 3rd resistance, and the two ends of this first electric capacity couple the gate terminal and the drain electrode end of this nmos pass transistor respectively;
One the one PMOS transistor, the drain electrode end of its drain electrode end and this nmos pass transistor couples each other, and the transistorized source terminal of a PMOS then couples a voltage source; And
One the 2nd PMOS transistor, its drain electrode end are by a current source ground connection, and its source terminal is to couple this voltage source, and its gate terminal and the transistorized gate terminal of a PMOS couple each other, and couple the 2nd PMOS transistor drain end;
One voltage controlled oscillator is in order to produce one the 3rd pulse signal according to the output of this loop filter; And
One second frequency divider in order to the 3rd pulse signal is carried out frequency division, and produces this second pulse signal to this phase detecting circuit.
8. phase-locked loop according to claim 7, it is characterized in that wherein said loop filter more comprises one second electric capacity, wherein an end couples the input of this loop filter, and being coupled to the gate terminal of this nmos pass transistor by the 3rd resistance, the other end of this second electric capacity is ground connection then.
9. phase-locked loop according to claim 8 is characterized in that wherein said loop filter more comprises:
One the 4th resistance, wherein an end couples the input of this loop filter, and is coupled to the gate terminal of this nmos pass transistor by the 3rd resistance, and the other end of the 4th resistance then couples the output of this loop filter; And
One the 3rd electric capacity, wherein an end couples the output of this loop filter, and the other end is ground connection then.
10. phase-locked loop is characterized in that it comprises:
One oscillator is in order to export a reference burst signal;
One first frequency divider in order to this reference burst signal is carried out frequency division, and produces one first pulse signal;
One phase detecting circuit in order to this first pulse signal and one second pulse signal are compared, and produces a comparative result;
One charge pump circuit is to receive this comparative result;
One loop filter couples the output of this charge pump circuit, and wherein this charge pump circuit is to control this loop filter according to this comparative result to charge and discharge the two one of them, and this loop filter comprises:
One first resistance:
One first electric capacity;
One amplifier, has a yield value, and have an amplifier in and an amplifier out, wherein this amplifier in is input and the output that is coupled to this loop filter by this first resistance, and this amplifier out then is coupled to this amplifier in by this first electric capacity;
One first nmos pass transistor, its source terminal ground connection; And
One second nmos pass transistor, its source terminal ground connection, its drain electrode end is to be coupled to a common electric potential by a current source, and being gate terminal with this first nmos pass transistor, its gate terminal couples each other, and be coupled to the drain electrode end of this second nmos pass transistor, and this amplifier is a PMOS transistor, its drain electrode end is that the drain electrode end with this first nmos pass transistor couples each other, this first resistance is made up of in the mode of series connection one second resistance and one the 3rd resistance, this second resistance is in order to be connected to this common electric potential with the transistorized source terminal of this PMOS, and the 3rd resistance is in order to be connected to the transistorized gate terminal of this PMOS the input of this loop filter and the output of this loop filter, and an end of this first electric capacity couples this PMOS transistor drain end, and the other end then couples the transistorized gate terminal of this PMOS;
One voltage controlled oscillator is in order to produce one the 3rd pulse signal according to the output of this loop filter; And
One second frequency divider in order to the 3rd pulse signal is carried out frequency division, and produces this second pulse signal to this phase detecting circuit.
11. phase-locked loop according to claim 10, it is characterized in that wherein said loop filter more comprises one second electric capacity, wherein an end couples the input of this loop filter, and being coupled to the transistorized gate terminal of this PMOS by the 3rd resistance, the other end of this second electric capacity is ground connection then.
12. phase-locked loop according to claim 11 is characterized in that wherein said loop filter more comprises:
One the 4th resistance, wherein an end couples the input of this loop filter, and is coupled to the transistorized gate terminal of this PMOS by the 3rd resistance, and the other end of the 4th resistance then couples the output of this loop filter; And
One the 3rd electric capacity, wherein an end couples the output of this loop filter, and the other end is ground connection then.
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| CN 200510002857 CN1633028B (en) | 2005-01-25 | 2005-01-25 | Phase lock loop and loop filter therefor |
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| CN 200510002857 CN1633028B (en) | 2005-01-25 | 2005-01-25 | Phase lock loop and loop filter therefor |
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| CN1633028B true CN1633028B (en) | 2010-04-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1025265C (en) * | 1990-11-29 | 1994-06-29 | 德国汤姆森-勃朗特有限公司 | Universal filter |
| CN1118940C (en) * | 1995-04-04 | 2003-08-20 | 诺基亚电信公司 | Loop filter of phase-locked loop |
-
2005
- 2005-01-25 CN CN 200510002857 patent/CN1633028B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1025265C (en) * | 1990-11-29 | 1994-06-29 | 德国汤姆森-勃朗特有限公司 | Universal filter |
| CN1118940C (en) * | 1995-04-04 | 2003-08-20 | 诺基亚电信公司 | Loop filter of phase-locked loop |
Non-Patent Citations (1)
| Title |
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| 全文. |
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| Publication number | Publication date |
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| CN1633028A (en) | 2005-06-29 |
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