CN1462901A - Active array base plate of LCD device and its manufacturing method - Google Patents
Active array base plate of LCD device and its manufacturing method Download PDFInfo
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- CN1462901A CN1462901A CN 02120672 CN02120672A CN1462901A CN 1462901 A CN1462901 A CN 1462901A CN 02120672 CN02120672 CN 02120672 CN 02120672 A CN02120672 A CN 02120672A CN 1462901 A CN1462901 A CN 1462901A
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Abstract
An active array substrate of LCD is prepared by use of 5 masks. The first mask is used to generate grid lines on transparent substrate. The second mask is used for sequentially depositing semiconductor layer, n-type doped layer and metal layer on a grid insulating layer to form data lines. The third mask is used to generate an insulating layer with low dielectric constant and the contact windows for exposing surface of data lines. Its fourth mask is used to form a transparent electric conducting layer, generate the pattern of pixel electrodes and sources, and etch on metal layer and n-type doped layer. The fifth mask is used to define protective layer.
Description
Technical field
The present invention relates to a kind of liquid crystal indicator (liquid crystal display, LCD) and manufacture method, particularly a kind of active array base plate (active matrix substrate) and manufacture method thereof with high pixel aperture than the liquid crystal indicator of (pixel aperture ratio).
Background technology
Liquid crystal indicator generally includes two upper and lower base plates with electrode, is bonded together with the involution material.Liquid crystal material is received between two substrates, has certain size particles between two substrates in order to keep distance fixing between the two substrates, can to scatter.Usually the infrabasal plate surface is formed with the thin film transistor (TFT) that is used for being used as on-off element, and this thin film transistor (TFT) has the gate electrode that is connected in sweep trace, the source electrode that is connected in the drain electrode of signal wire and is connected in pixel electrode.This upper substrate is called active array base plate again.
Heal when big when the pixel aperture ratio of liquid crystal indicator, its video picture transmits effect better.Therefore, using under the identical backlight energy, increasing the pixel aperture ratio and can improve its video picture transmission effect, perhaps, can reduce the waste of backlight energy keeping under the identical video picture transmission effect.
In order to improve the pixel aperture ratio, someone proposed before forming pixel electrode, form the thicker overlayer (over coating) of a layer thickness prior to its below, with the conductive material of avoiding pixel electrode and its below capacity effect is arranged, and enlarged the area coverage of pixel electrode.
Recently, existing people proposes many structure or methods that improve the pixel aperture ratio, as United States Patent (USP) 5,955, and 744,5,780,871,5,641,974 etc.
Summary of the invention
The object of the present invention is to provide a kind of active array base plate with liquid crystal indicator of high pixel aperture ratio.
The invention provides a kind of active array base plate of liquid crystal indicator, its structure is as described below.The gate line that is parallel to first direction is disposed on the transparency carrier, and outstanding extension of part covers active element region.Gate insulator is disposed on the transparency carrier with gate line.Low dielectric constant is positioned on the gate insulator, wherein has roughly the opening corresponding to the active component district.Data line perpendicular to first direction is disposed between gate insulator and the low dielectric constant, and part is outstanding extends to the active component district, and gate line and data line institute region surrounded can be divided into active component district and pixel region.Under the one n type doped layer configuration data line, contact with data line, and identical with the pattern of data line, near the n type doped layer of a side that is arranged in opening is as source electrode.The conductor configurations of tool source electrode pattern is on source electrode.The 2nd n type doped layer be disposed at opposite side in the opening near, and, be channel region between source electrode and the drain electrode as drain electrode.Drain electrode is disposed in the drain electrode.Semiconductor layer is disposed under a n type doped layer and the 2nd n type doped layer, and is disposed on the gate insulator, and the pattern of semiconductor layer is the set pattern of a n type doped layer, the 2nd n type doped layer and channel region.Pixel electrode is disposed on the low dielectric constant of pixel region, and extends on the lead and be connected with drain electrode.Protective seam roughly is positioned at opening.
The invention provides a kind of manufacture method of active array base plate of above-mentioned liquid crystal indicator, its method is summarized as follows.On transparency carrier, form the gate line that is parallel to first direction, and outstanding extension of part covers active element region.On gate line and transparency carrier, form gate insulator, semiconductor layer, n type doped layer and metal level, and definition semiconductor layer, n type doped layer and metal level, so that metal level transfers the data line perpendicular to first direction to.On transparency carrier, form low dielectric constant with data line, and in wherein forming opening roughly corresponding to the element active area.On low dielectric constant, form transparency conducting layer, and the definition transparency conducting layer, to form the lead of pixel electrode and tool source electrode pattern.Continuation is a mask with pixel electrode and source electrode pattern lead, data line in the etching openings and n type doped layer.Form protective seam in opening part at last.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
The top view of the making flow process of the active array base plate of the liquid crystal indicator of Figure 1A to Fig. 1 D demonstration one embodiment of the invention;
The sectional view of the making flow process of the active array base plate of the liquid crystal indicator of Fig. 2 A to Fig. 2 E demonstration one embodiment of the invention, wherein Fig. 2 A to Fig. 2 D is respectively the II-II sectional view of Figure 1A to Fig. 1 D;
Fig. 3 and Fig. 4 show the top view of making flow process of active array base plate of the liquid crystal indicator of another embodiment of the present invention;
Fig. 5 A and Fig. 5 B are respectively the A-A of presentation graphs 3 and the sectional view of B-B tangent line;
Fig. 6 is the sectional view of the C-C tangent line of presentation graphs 4; And
Fig. 7 A to Fig. 7 E is the sectional view of making flow process of active array base plate that shows the liquid crystal indicator of another embodiment of the present invention, and wherein Fig. 7 A to Fig. 7 D is respectively the II-II sectional view of Figure 1A to Fig. 1 D.
Description of reference numerals in the accompanying drawing is as follows:
Active component district: A transparency carrier: 11
Gate line: 13 gate insulators: 15,15a
Semiconductor layer: 17 n type doped layers: 19
Data line: the insulation course of 21 advanced low-k materials: 23
Opening: 24,44 pixel electrodes: 25a
Lead: 25b protective seam: 27
The lead that connects source electrode and solder joint: 25c
Solder joint: 13a
Embodiment
The invention provides a kind of active array base plate of high pixel aperture ratio, shown in Fig. 1 D and Fig. 2 E.Following examples will be described the structure and the manufacture method of this active array base plate in detail.
First embodiment
Fig. 2 A to Fig. 2 E is the sectional view of making flow process of active array base plate that shows the liquid crystal indicator of one embodiment of the invention, and Figure 1A to Fig. 1 D is a top view.Wherein Fig. 2 A to Fig. 2 D is respectively the II-II sectional view of Figure 1A to Fig. 1 D.
Please at first provide a transparency carrier 11 simultaneously with reference to Figure 1A and Fig. 2 A, for example be glass substrate, forms the ground floor metal level on transparency carrier 11, and its material for example is an aluminum or aluminum alloy, becomes gate line 13 after the photoetching etching.This gate line 13 and side direction protrude in active component district A, promptly one of pixel region jiao.Wherein, to protrude in the part of active component district A be gate electrode to gate line 25 side direction.
Then please form one deck gate insulator 15 on the transparency carrier 11 with gate line 13 simultaneously with reference to Figure 1B and Fig. 2 B, its material can be silicon nitride.Depositing semiconductor layers, n type doped layer and metal level in regular turn on gate insulator 15 afterwards, wherein the material of semiconductor layer for example is an amorphous silicon, the material of metal level for example is chromium or evanohm.And metal level/n type doped layer/semiconductor layer carried out a photoetching etching, to define data line 21, n type doped layer 19 and semiconductor layer 17.At this moment, still undefinedly go out source electrode, drain electrode and channel region.
Then please be simultaneously with reference to Fig. 1 C and Fig. 2 C, the insulation course 23 of coating one deck advanced low-k materials on transparency carrier 11 with data line 21 and gate insulator 15, this kind advanced low-k materials (specific inductive capacity is less than 5) has the transparency.Because of it has the characteristic of low-k, the conductive material that therefore can reduce pixel electrode and its below has capacity effect, and then is improved the pixel aperture ratio.This kind advanced low-k materials can be to have a photosensitive material, can also the photosensitive material of right and wrong, and for example be that specific inductive capacity is about 2.7 benzocyclobutene (BCB (benzocyclobutene)).The thickness of this low dielectric constant 23 is about about 1 μ m～5 μ m.
Form opening 24 afterwards in this low dielectric constant 23, this opening 24 roughly is positioned at active component district A.
Then please be simultaneously with reference to Fig. 1 D and Fig. 2 D, on low dielectric constant 23, form the layer of transparent conductive layer, its material for example is that (indium tin oxide ITO), and is patterned into its photoetching etching the lead 25b of pixel electrode 25a and tool source electrode pattern to indium tin oxide.Continuation is a mask with the lead 25b of pixel electrode 25a and tool source electrode pattern, data line 21 in the etching openings 24 and n type doped layer 19, to define source S and drain D, and source S and drain D lay respectively at the both sides of opening 24, toward each other, and the semiconductor layer between source S and the drain D 17 be channel region.Wherein the data line 21 corresponding to the source S top is source electrode 21S, be drain electrode 21D corresponding to the data line 21 above the drain D, and pixel electrode 25a contacts with drain electrode 21D.
Through after the above-mentioned technology, the pattern of this semiconductor layer 17 is the set pattern of n type doped layer 19, source S, drain D and channel region.
Then please refer to Fig. 2 E, form layer protective layer 27 at active component district A, its material for example is a silicon nitride, in order to the channel region that exposes between protection source S and the drain D.
After protective seam 27 forms, promptly finish active array base plate, can proceed to assemble with upper substrate and liquid crystal.
The invention provides the active array base plate of another kind of high pixel aperture ratio, shown in Fig. 1 D and Fig. 7 E.Following embodiment will describe the structure and the manufacture method of this active array base plate in detail.
Second embodiment
Fig. 7 A to Fig. 7 E is the sectional view of making flow process of active array base plate that shows the liquid crystal indicator of another embodiment of the present invention, and Figure 1A to Fig. 1 D is respectively the top view of Fig. 7 A to Fig. 7 D.
Please at first provide a transparency carrier 11 simultaneously with reference to Figure 1A and Fig. 7 A, for example be glass substrate, forms the ground floor metal level on transparency carrier 11, and its material for example is an aluminum or aluminum alloy, becomes gate line 13 after the photoetching etching.This gate line 13 and side direction protrude in active component district A, promptly one of pixel region jiao.Wherein, to protrude in the part of active component district A be gate electrode to gate line 25 side direction.
Then please be simultaneously with reference to Figure 1B and Fig. 7 B, on transparency carrier 11, form one deck gate insulator, semiconductor layer, n type doped layer and metal level in regular turn with gate line 13, wherein the material of gate insulator can be silicon nitride, the material of semiconductor layer can be amorphous silicon, and the material of metal level can be chromium or evanohm.Afterwards metal level/n type doped layer/semiconductor layer/gate insulator is carried out a photoetching etching, to define data line 21, n type doped layer 19, semiconductor layer 17 and gate insulator 15a.At this moment, still undefinedly go out source electrode, drain electrode and channel region.
Then please be simultaneously with reference to Fig. 1 C and Fig. 7 C, the insulation course 23 of coating one deck advanced low-k materials on transparency carrier 11 with data line 21, this kind advanced low-k materials (specific inductive capacity is less than 5) has the transparency.Because of it has the characteristic of low-k, the conductive material that therefore can reduce pixel electrode and its below has capacity effect, and then is improved the pixel aperture ratio.This kind advanced low-k materials can be to have a photosensitive material, can also the photosensitive material of right and wrong, and for example be that specific inductive capacity is about 2.7 benzocyclobutene (BCB (benzocyclobutene)).The thickness of this low dielectric constant 23 is about about 1 μ m～5 μ m.
Form opening 24 afterwards in this low dielectric constant 23, this opening 24 roughly is positioned at active component district A.
Then please be simultaneously with reference to Fig. 1 D and Fig. 7 D, on low dielectric constant 23, form the layer of transparent conductive layer, its material for example is that (indium tin oxide ITO), and is patterned into its photoetching etching the lead 25b of pixel electrode 25a and tool source electrode pattern to indium tin oxide.Continuation is a mask with the lead 25b of pixel electrode 25a and tool source electrode pattern, data line 21 in the etching openings 24 and n type doped layer 19, to define source S and drain D, and source S and drain D lay respectively at the both sides of opening 24, toward each other, and the semiconductor layer between source S and the drain D 17 be channel region.Wherein the data line 21 corresponding to the source S top is source electrode 21S, be drain electrode 21D corresponding to the data line 21 above the drain D, and pixel electrode 25a contacts with drain electrode 21D.
Through after the above-mentioned technology, the pattern of this semiconductor layer 17 is the set pattern of n type doped layer 19, source S, drain D and channel region.
Then please refer to Fig. 7 E, form layer protective layer 27 in active component district A, its material for example is a silicon nitride, in order to the channel region that exposes between protection source S and the drain D.
After protective seam 27 forms, promptly finish active array base plate, can proceed to assemble with upper substrate and liquid crystal.
The 3rd embodiment
If consider static discharge (electrostatic discharge simultaneously; ESD) holding circuit; then in the illustrated technology of above-mentioned cooperation Fig. 1 C and Fig. 2 C; when in low dielectric constant 23, roughly forming opening 24 corresponding to the zone of active component district A; solder joint 13a in gate line 13 ends forms opening 44 simultaneously; and continue the gate insulator 15 in the etching openings 44, make it transfer as shown in the figure gate insulator 15a to, as shown in Figure 3 and Figure 4.
Continuation is shown in Fig. 1 D and Fig. 2 D, on low dielectric constant 23, form the layer of transparent conductive layer, and when its photoetching etching is patterned into the lead 25b of pixel electrode 25a and tool source electrode pattern, form tool source electrode pattern and can be simultaneously in solder joint 13a place with the lead 25c of solder joint 13a and the source electrode that will form short circuit.Continuation is a mask with the lead 25b of pixel electrode 25a, tool source electrode pattern and the lead 25c of tool source electrode pattern, data line 21 in the etching openings 24 and 44 and n type doped layer 19, to define source S and drain D, and source S and drain D lay respectively at the both sides of opening 44, toward each other, and the semiconductor layer between source S and the drain D 17 be channel region.At this moment, lead 25c can be with solder joint 13a in the opening 44 and source S short circuit, to form diode, as esd protection circuit.
Afterwards, proceed the technology of above-mentioned first embodiment.
Though the present invention with preferred embodiment openly as above; but it is not that those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention in order to restriction the present invention; can do change and retouching, so protection scope of the present invention should be as the criterion so that claims are defined.
Claims (12)
1. the active array base plate of a liquid crystal indicator comprises:
One transparency carrier;
Many the gate line that is parallel to a first direction is disposed on this transparency carrier, and outstanding extension of part covers a plurality of active components district;
One gate insulator is disposed on this transparency carrier with those gate lines;
One low dielectric constant is positioned on this gate insulator, has a plurality of openings in this low dielectric constant roughly corresponding to those active component districts;
Many the data line perpendicular to this first direction is disposed between this gate insulator and this low dielectric constant, and part is outstanding to be extended in those openings, and a plurality of zones that those gate lines and those data lines are centered on can be divided into those active component districts and a plurality of pixel region;
A plurality of n type doped layers dispose under those data lines, contact with those data lines, and identical with the pattern of those data lines, and near those n type doped layers of a side that are arranged in those openings are as a plurality of source electrodes;
On those data lines of many those source electrode tops of conductor configurations in those openings, wherein those leads are the source electrode pattern;
A plurality of the 2nd n type doped layers be disposed at opposite side relative in those openings with those source electrodes near, and as a plurality of drain electrodes, be a plurality of channel regions between those source electrodes and those drain electrodes;
A plurality of drain electrodes are disposed in those drain electrodes;
Semi-conductor layer is disposed under those n type doped layers and those the 2nd n type doped layers, and is disposed on this gate insulator, and the pattern of this semiconductor layer is the set pattern of those n type doped layers, those the 2nd n type doped layers and those channel regions;
A plurality of pixel electrodes are disposed on this low dielectric constant of those pixel regions, and extend on those drain electrodes and be connected with those drain electrodes; And
One protective seam roughly is positioned at those openings.
2. the active array base plate of liquid crystal indicator as claimed in claim 1, wherein the material of this low dielectric constant is a benzocyclobutene.
3. the active array base plate of liquid crystal indicator as claimed in claim 1, wherein those pixel electrodes extend to those gate lines tops of part and those data lines tops of part.
4. the active array base plate of liquid crystal indicator as claimed in claim 1, wherein the material of those pixel electrodes and those source electrode pattern leads is an indium tin oxide.
5. the active array base plate of liquid crystal indicator as claimed in claim 1 more comprises:
A plurality of solder joints are positioned at those gate line ends;
This low dielectric constant is positioned on this gate insulator, has a plurality of openings in this low dielectric constant roughly corresponding to those active component districts and those solder joints; And
Those leads extend and connect corresponding those source electrodes and those solder joints in those openings corresponding to those solder joints roughly.
6. the manufacture method of the active array base plate of a liquid crystal indicator comprises:
One transparency carrier is provided;
On this transparency carrier, form many gate lines that are parallel to a first direction, and outstanding extension of part covers a plurality of active components district;
On those gate lines and this transparency carrier, form a gate insulator;
On this gate insulator, form semi-conductor layer;
On this semiconductor layer, form a n type doped layer;
Mix layer in this n type and go up formation one metal level;
Define this semiconductor layer, this n type doped layer and this metal level, so that this metal level transfers many data lines perpendicular to this first direction to;
On this transparency carrier, form a low dielectric constant with those data lines;
In this low dielectric constant, form a plurality of openings roughly corresponding to those element active areas;
On this low dielectric constant, form a transparency conducting layer;
Define this transparency conducting layer, to form a plurality of pixel electrodes and many leads with source electrode pattern;
With those pixel electrodes and those leads is mask, this data line in those openings of etching and this n type doped layer; And
Form a protective seam in those opening parts.
7. the manufacture method of the active array base plate of liquid crystal indicator as claimed in claim 6, wherein the material of this low dielectric constant is a benzocyclobutene.
8. the manufacture method of the active array base plate of liquid crystal indicator as claimed in claim 6, wherein this metal level is transferred in the step perpendicular to many data lines of this first direction at definition this semiconductor layer, this n type doped layer and this metal level, more comprise defining this gate insulator simultaneously, to exposing this transparent substrates.
9. the manufacture method of the active array base plate of liquid crystal indicator as claimed in claim 6, wherein those pixel electrodes extend to those gate lines tops of part and those data lines tops of part.
10. the manufacture method of the active array base plate of liquid crystal indicator as claimed in claim 6, wherein this transparency conducting layer is an indium tin oxide layer.
11. the manufacture method of the active array base plate of liquid crystal indicator as claimed in claim 6, wherein the material of this protective seam is a silicon nitride.
12. the manufacture method of the active array base plate of liquid crystal indicator as claimed in claim 6, wherein those gate line ends have a plurality of solder joints, those openings that form in this low dielectric constant connect corresponding those source electrodes and those solder joints roughly corresponding to those element active areas and those solder joints and roughly extend corresponding to those leads in those openings of those solder joints.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021206724A CN1185534C (en) | 2002-05-28 | 2002-05-28 | Active array base plate of LCD device and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021206724A CN1185534C (en) | 2002-05-28 | 2002-05-28 | Active array base plate of LCD device and its manufacturing method |
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| CN1462901A true CN1462901A (en) | 2003-12-24 |
| CN1185534C CN1185534C (en) | 2005-01-19 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100449391C (en) * | 2006-08-04 | 2009-01-07 | 北京京东方光电科技有限公司 | Thin-film transistor LCD pixel structure and manufacturing method therefor |
| CN100514165C (en) * | 2006-02-15 | 2009-07-15 | 乐金显示有限公司 | Array substrate for liquid crystal display device and fabrication method thereof |
| CN102522411A (en) * | 2011-12-22 | 2012-06-27 | 深圳莱宝高科技股份有限公司 | Thin film transistor, array substrate using thin film transistor and manufacturing method of array substrate |
| WO2013044796A1 (en) * | 2011-09-26 | 2013-04-04 | 京东方科技集团股份有限公司 | Array substrate and method for manufacturing same |
| CN104051472A (en) * | 2014-06-19 | 2014-09-17 | 京东方科技集团股份有限公司 | Display device, array substrate and manufacturing method of array substrate |
| CN106652900A (en) * | 2015-10-30 | 2017-05-10 | 精工爱普生株式会社 | Electro-optical device, electronic apparatus, and method for driving electro-optical device |
| WO2017121216A1 (en) * | 2016-01-14 | 2017-07-20 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Thin film transistor array panel |
| WO2017177493A1 (en) * | 2016-04-13 | 2017-10-19 | 深圳市华星光电技术有限公司 | Thin film transistor array panel and manufacturing method therefor |
| WO2019006817A1 (en) * | 2017-07-06 | 2019-01-10 | 惠科股份有限公司 | Array substrate and display panel |
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| JP5011479B2 (en) * | 2006-02-14 | 2012-08-29 | 株式会社ジャパンディスプレイイースト | Manufacturing method of display device |
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- 2002-05-28 CN CNB021206724A patent/CN1185534C/en not_active Expired - Lifetime
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| CN100514165C (en) * | 2006-02-15 | 2009-07-15 | 乐金显示有限公司 | Array substrate for liquid crystal display device and fabrication method thereof |
| CN100449391C (en) * | 2006-08-04 | 2009-01-07 | 北京京东方光电科技有限公司 | Thin-film transistor LCD pixel structure and manufacturing method therefor |
| US9178046B2 (en) | 2011-09-26 | 2015-11-03 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof |
| WO2013044796A1 (en) * | 2011-09-26 | 2013-04-04 | 京东方科技集团股份有限公司 | Array substrate and method for manufacturing same |
| CN102522411B (en) * | 2011-12-22 | 2016-02-10 | 深圳莱宝高科技股份有限公司 | Thin film transistor (TFT), the array base palte using this thin film transistor (TFT) and preparation method thereof |
| CN102522411A (en) * | 2011-12-22 | 2012-06-27 | 深圳莱宝高科技股份有限公司 | Thin film transistor, array substrate using thin film transistor and manufacturing method of array substrate |
| CN104051472A (en) * | 2014-06-19 | 2014-09-17 | 京东方科技集团股份有限公司 | Display device, array substrate and manufacturing method of array substrate |
| CN106652900A (en) * | 2015-10-30 | 2017-05-10 | 精工爱普生株式会社 | Electro-optical device, electronic apparatus, and method for driving electro-optical device |
| CN106652900B (en) * | 2015-10-30 | 2021-12-21 | 精工爱普生株式会社 | Electro-optical device, electronic apparatus, and method of driving electro-optical device |
| WO2017121216A1 (en) * | 2016-01-14 | 2017-07-20 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Thin film transistor array panel |
| US9793409B2 (en) | 2016-01-14 | 2017-10-17 | Hon Hai Precision Industry Co., Ltd. | Thin film transistor array panel |
| WO2017177493A1 (en) * | 2016-04-13 | 2017-10-19 | 深圳市华星光电技术有限公司 | Thin film transistor array panel and manufacturing method therefor |
| WO2019006817A1 (en) * | 2017-07-06 | 2019-01-10 | 惠科股份有限公司 | Array substrate and display panel |
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| CN1185534C (en) | 2005-01-19 |
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