CN1309016C - Method for forming PN boundary and once programmable read-only memory structure and mfg. process - Google Patents
Method for forming PN boundary and once programmable read-only memory structure and mfg. process Download PDFInfo
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- CN1309016C CN1309016C CNB031564844A CN03156484A CN1309016C CN 1309016 C CN1309016 C CN 1309016C CN B031564844 A CNB031564844 A CN B031564844A CN 03156484 A CN03156484 A CN 03156484A CN 1309016 C CN1309016 C CN 1309016C
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Abstract
The present invention relates to a method for forming a PN connection surface and a structure and a manufacture process of a once programmable read-only memory. The method for forming a PN connection surface comprises the following steps: a stacking structure of an N-shaped adulterating layer, a dielectric layer and a crystal nucleus layer is firstly formed, and then, an insulating layer with an opening is formed on a substrate; subsequently, a P-shaped compound crystal silicon or amorphous silicon layer is formed in the openings, and then, tempering is carried out to make the compound crystal silicon or the amorphous silicon layer converted into a single crystal silicon layer; afterwards, the electrical property of the dielectric layer is crashed. The manufacture process of a once programmable read-only memory is obtained by the method for forming a PN connection surface, wherein the adulterating layer, the dielectric layer and the crystal nucleus layer at the lower part form a stacking structure in a long strip shape; a ditch is formed in the insulating layer, and the trend of the ditch is different from that of the structure in a long strip shape.
Description
Technical field
The present invention relates to the structure of a kind of manufacture of semiconductor and semiconductor subassembly, relate in particular to a kind of PN of formation and connect the method for face, use single programmable read-only memory (the One-TimeProgrammable Read-Only Memory of this method, OTP-ROM) processing procedure, and by the single programmable read-only memory cell and the internal memory of this processing procedure gained.
Background technology
PN connects the basic structure that face is multiple semiconductor subassembly, is made of polysilicon usually.Yet because polysilicon contains many crystal grain not of uniform size (grain), and has the existence of grain boundary again, so the PN of general semiconductor subassembly connects face characteristic and inconsistent, leakage path is also many simultaneously.
Memory subassembly to high aggregation degree, read-only memory, magnetoresistive random access internal memory (Magnetoresistive Random Access Memory as three-dimensional space internal memory (3D Memory), chalcogenide compound (Chalcogenide) internal memory, single programmable diode (OTP diode), assembly such as MRAM), it all needs to have the electric current guidance unit (Current SteeringElement) that PN connects face, with guarantee electric current only at folk prescription to flowing.Simultaneously, each memory cell in these memory subassemblies also must possess consistent characteristic, to improve the sensing nargin (Sensing Margin) of open/close state.Moreover the leakage path in these memory subassemblies also must reduce, to reduce power consumption and caloric value.Therefore, as with polysilicon as the material that PN connects face, then can't satisfy the demand often.
For instance, U.S. Pat 6,420,215 disclose a kind of tridimensional single programmable read-only memory, in substrate, replace the N type polysilicon layer and the P type polysilicon layer of stack strip shape, wherein neighbouring two-layer N type polysilicon layer and P type polysilicon layer move towards perpendicular, and be separated with an antifuse layer (Antifuse Layer) therebetween, and the part that overlaps of two N type polysilicon layers and P type polysilicon layer and antifuse layer therebetween promptly constitute a memory cell up and down.When having sequencing in this kind, on selected N type and P type polysilicon layer, apply voltage, cause voltage difference up and down and make its collapse, connect face thereby form PN with antifuse layer in the centre.As previously mentioned, the character that connects face owing to polysilicon PN is inconsistent, and has the grain boundary, so each memory cell characteristic is inconsistent, and is easy to generate electric leakage under reverse bias.
The above-mentioned PN of known solution connects one of method of face problem, promptly is the size of control polysilicon grain, and the position of grain boundary.For example, people such as Yonehara are at Materials Research Society, Symp.Proc.Vol.106, p.21-26, disclose a kind of method of controlling the silicon crystal grain border in 1988 articles of being delivered, it reaches by armorphous suprabasil selectivity nucleation (nucleationprocess).Specifically, this method is that (low-nucleation-density layer is as SiO with being formed on low grain density layer
2) on high grain density layer (high-nucleation-density layer is as Si
3N
4) be defined as many fritters, or define the zonule that is formed on the low grain density layer on the high grain density layer and exposes many high grain densities, with nucleus, and then carry out gas phase crystalline substance of heap of stone, to form many silicon crystal grains according to the nucleus positional alignment as silicon crystal grain growth usefulness.But, because this method needs one extra light shield to define high grain density layer or low grain density layer, so processing procedure comparatively bothers.
In addition, solving the another kind of method that above-mentioned PN connects the face problem, then is the material that connects face with monocrystalline silicon as PN.For example, people such as Subramanian are at IEEE EDL, Vol.20, No.7, pp 341-343,1999 disclose a kind of method that forms monocrystalline silicon source/drain area and channel region, are to form a sacrificial oxide layer on an amorphous silicon layer, in this sacrificial oxide layer, form little opening again, then optionally form the germanium crystal seed layer on the amorphous silicon layer in little opening.Then carry out tempering,, and be transformed into monocrystalline silicon layer gradually so that amorphous silicon layer is by the place's initial recrystallization of germanium crystal seed layer.Then, remove germanium crystal seed layer and sacrificial oxide layer, formation source/drain area and channel region in monocrystalline silicon layer again.But, because the method needs one extra light shield to define sacrificial oxide layer, so processing procedure comparatively bothers.
Summary of the invention
For solving the problem of above-mentioned prior art method, one of the object of the invention forms the method that PN connects face for providing, it is that the PN of monocrystalline silicon connects face that the method is formed up to a rare side (P or N) with nucleation processing procedure (Nucleation Process), to improve the consistency that PN connects the face characteristic.Simultaneously, the method does not need extra light shield to define high grain density layer, low grain density layer or sacrifice layer.
Another object of the present invention is for providing the processing procedure of single programmable read-only memory, it connects the principle of surface forming method based on above-mentioned PN, inconsistent with the memory cell characteristic of improving known single programmable read-only memory processing procedure gained, and the problem of under reverse bias, leaking electricity easily.
A further object of the present invention is for providing the structure of single programmable read-only memory cell and internal memory, and it is resultant by single programmable read-only memory processing procedure of the present invention.
The method that a kind of PN of formation of the present invention connects face comprises the following steps.At first form a stack architecture in substrate, it comprises first doped layer, a dielectric layer and a crystal nucleation layer of the N type of storehouse (or P type) from the bottom to top, and wherein the material of first doped layer can be polysilicon or monocrystalline silicon, as the monocrystalline silicon on Silicon Wafer top layer.Then, form the insulating barrier with opening in substrate, this opening exposes the part crystal nucleation layer, forms second doped layer of P type (or N type) again in opening, and its material is polysilicon or amorphous silicon.Then carry out a tempering step,, dielectric layer is electrically collapsed, promptly get PN and connect face so that second doped layer changes a monocrystalline silicon layer into.
The invention provides the method that the another kind of PN of formation connects face, its step is as follows.At first form a stack architecture in substrate, it comprises the N type of storehouse (or P type) first doped layer, a dielectric layer and P type (or N type) second doped layer from the bottom to top, and wherein the material of second doped layer is polysilicon or amorphous silicon.Then form the insulating barrier with opening in substrate, this opening exposes part second doped layer, forms a crystal nucleation layer again on second doped layer that opening exposed, and for example is a germanium crystal seed layer.Carry out a tempering step then,, dielectric layer is electrically collapsed, promptly get PN and connect face so that second doped layer of crystal nucleation layer below changes monocrystalline silicon layer into.
In addition, the step of first kind of single programmable read-only memory processing procedure of the present invention is as follows: (a). a substrate at first is provided, be formed with an insulating barrier on it, and a plurality of strip stack architectures that are arranged in the irrigation canals and ditches of this insulating barrier, wherein each stack architecture all comprises the N type of storehouse (or P type) semiconductor layer, antifuse layer and crystal nucleation layer from the bottom to top, wherein the material of semiconductor layer can be polysilicon or monocrystalline silicon, for example is the monocrystalline silicon of silicon wafer surface.(b). in substrate, form a time insulating barrier.(c). form many irrigation canals and ditches in an inferior insulating barrier, its trend is different with the irrigation canals and ditches in the last insulating barrier, and exposes a plurality of parts of each crystal nucleation layer.(d). in the irrigation canals and ditches of an inferior insulating barrier, insert P type (or N type) polysilicon.(e). carry out tempering, so that the polysilicon on the crystal nucleation layer is transformed into monocrystalline silicon.
In first kind of single programmable read-only memory processing procedure of the invention described above, more can comprise the following steps to have the three-dimensional space internal memory of multilayer memory cell with formation: (f). form a conductor layer on the polysilicon in each irrigation canals and ditches of an inferior insulating barrier.(g). form the inferior semi-conductor layer of N type (or P type), an inferior antifuse layer and a time crystal nucleation layer on the conductor layer in each irrigation canals and ditches of an inferior insulating barrier, and constitute a time stack architecture.Then, step (b) ~ (g) is carried out in circulation, and to form the more insulating barrier and the stack architecture on upper strata, till the memory cell that forms predetermined number of layers, it is different that the irrigation canals and ditches in wherein neighbouring two insulating barriers move towards, and step (g) is not carried out in last circulation.This circulation also can only be carried out once, promptly repeats step (b) ~ (f), only to form two-layer memory cell.Conductor layer is as bit line or character line herein, and bit line and character line alternatively up and down form.
The present invention also provides second kind of single programmable read-only memory processing procedure, its step is as follows: (a). a substrate is provided, be formed with an insulating barrier on it, and a plurality of strip stack architectures that are arranged in the irrigation canals and ditches of this insulating barrier, wherein each stack architecture all comprises the N type of storehouse (or P type) semiconductor layer, antifuse layer from the bottom to top, and P type (or N type) amorphous silicon layer, wherein the material of semiconductor layer can be polysilicon or monocrystalline silicon, for example is the monocrystalline silicon on Silicon Wafer top layer.(b). in substrate, form a time insulating barrier.(c). form a plurality of irrigation canals and ditches in an inferior insulating barrier, its trend is different with the irrigation canals and ditches in the last insulating barrier, and exposes a plurality of parts of each amorphous silicon layer in the last insulating barrier.(d). in irrigation canals and ditches, form a crystal nucleation layer.(e). carry out tempering, so that the amorphous silicon of crystal nucleation layer below is transformed into monocrystalline silicon.(f). remove crystal nucleation layer.(g). in each irrigation canals and ditches, form a conductor layer.
As mentioned above, in single programmable read-only memory processing procedure of the present invention, the step that defines the formation position of monocrystalline silicon is integrated with the damascene process that promptly needs originally, that is on the crystal nucleation layer that opening exposed of interlayer insulating film (inter-layer insulator), form monocrystalline silicon layer, or in the opening of interlayer insulating film, form crystal nucleation layer, make the amorphous silicon under the crystal nucleation layer be transformed into monocrystalline silicon again.Therefore, the present invention needn't define high grain density layer (being equal to above-mentioned crystal nucleation layer) or low grain density layer (being equal to dielectric layer or antifuse layer between the aforementioned PN doped layer) as using one extra light shield as the prior art method, also needn't form and sacrifice layer that patterning is extra with the position of definition crystal nucleation layer.
In addition, in second kind of single programmable read-only memory processing procedure of the invention described above, more can comprise the following steps, to form second layer memory cell: (h). after in the irrigation canals and ditches of an inferior insulating barrier, forming conductor layer, continue at the inferior semi-conductor layer and time antifuse layer that form N type (or P type) on the conductor layer in each irrigation canals and ditches.(i). in substrate, form a time amorphous silicon layer of P type (or N type).(j). form a plurality of strip crystal nucleation layer on an inferior amorphous silicon layer, wherein arbitrary crystal nucleation layer is positioned at the semi-conductor layer top one time.(k). carry out a tempering step, so that the amorphous silicon of crystal nucleation layer below is transformed into monocrystalline silicon.(l). remove crystal nucleation layer.(m). on a time amorphous silicon layer that comprises monocrystalline silicon, form a time conductor layer.(n). a definition time conductor layer and a time amorphous silicon layer that comprises monocrystalline silicon, to form a plurality of strip stack architectures, its trend is different with the irrigation canals and ditches in time insulating barrier.So, promptly formed single programmable ROM module with two-layer memory cell.
Moreover, in second kind of single programmable read-only memory processing procedure of the invention described above, more can comprise following variation, have the three-dimensional space internal memory of multilayer memory cell with formation.Wherein, step (m) more comprises the another amorphous silicon layer that forms another semiconductor layer, another antifuse layer and the P type (or N type) of N type (or P type) in regular turn on an inferior conductor layer, and step (n) defines this another amorphous silicon layer, another antifuse layer, another semiconductor layer, an inferior conductor layer and a time amorphous silicon layer in regular turn, and gets a plurality of strip stack architectures.This processing procedure more is included in the step (o) of inserting another insulating barrier between these stack architectures, and then step (b) ~ (o) is carried out in circulation, to form the more insulating barrier and the stack architecture on upper strata, till the memory cell that forms predetermined number of layers.This circulation step ends at step (g) or (n), and when this circulation step ends at a step (n), the previous step (m) of this final step (n) does not form another semiconductor layer, another antifuse layer and another amorphous silicon layer, and step (n) does not define another amorphous silicon layer, another antifuse layer and another semiconductor layer.This circulation step also can only carry out half wheel, promptly by step (b) to (g), to form the internal memory only have three layers of memory cell.
As mentioned above, because PN of the present invention connects in surface forming method and the single programmable read-only memory processing procedure, constitute the P type doped layer and N type doped layer that PN connects face and have at least one to be monocrystalline silicon layer in the two, so that PN connects the character of face is more consistent, and the electric leakage under reverse bias also can reduce.Therefore, it is also more consistent to utilize this PN to connect the characteristic of the single programmable read-only memory cell of face or other assembly, and electrical leakage quantity also can reduce.
On the other hand, the invention provides a kind of structure of single programmable read-only memory cell, it comprises second doped layer of first doped layer, antifuse layer, crystal nucleation layer and the P type (or N type) of N type (or P type).Wherein, first doped layer is positioned in the substrate, and material can be polysilicon or monocrystalline silicon, for example is the monocrystalline silicon on Silicon Wafer top layer.Antifuse layer is positioned on first doped layer, and crystal nucleation layer is positioned on the antifuse layer.Second doped layer is positioned on the crystal nucleation layer, and the material of second doped layer is a monocrystalline silicon.
The present invention also provides a kind of single programmable read-only memory, and its elementary cell is the single programmable read-only memory cell of the invention described above, and obtained with aforementioned first kind of single programmable read-only memory processing procedure of the present invention.This internal memory comprises a plurality of strip stack architectures and a plurality of strip silicon layer, and wherein the strip silicon layer is positioned at the stack architecture top, and staggered with it.Each stack architecture all comprises from bottom to top the N type of storehouse (or P type) semiconductor layer, antifuse layer, and crystal nucleation layer, and wherein the material of semiconductor layer for example is the monocrystalline silicon on polysilicon or Silicon Wafer top layer.Each silicon layer is all P type (or N type) and mixes, and is made of polysilicon block and the monocrystalline silico briquette alternately arranged, and wherein arbitrary monocrystalline silico briquette is positioned on the crystal nucleation layer of a stack architecture that overlaps with this silicon layer, and arbitrary polysilicon block is between two monocrystalline silico briquettes.
The present invention also provides a kind of single programmable read-only memory, and is obtained with aforementioned second kind of single programmable read-only memory processing procedure of the present invention.This internal memory comprises a plurality of strip stack architectures and a plurality of strip conductor layer, and wherein the strip conductor layer is positioned at the stack architecture top, and staggered with it.Each stack architecture all comprises the N type of storehouse (or P type) semiconductor layer, antifuse layer from the bottom to top, and the silicon layer of P type (or N type), and wherein the material of semiconductor layer for example is the monocrystalline silicon on polysilicon or Silicon Wafer top layer.Each silicon layer all is made of amorphous silico briquette and the monocrystalline silico briquette alternately arranged, and wherein arbitrary monocrystalline silico briquette is positioned under the strip conductor layer that overlaps with this silicon layer, and arbitrary amorphous silico briquette is between two monocrystalline silico briquettes.
As mentioned above, in the structure of single programmable read-only memory cell of the present invention or internal memory, constitute the P type doped layer and N type doped layer that PN connects face and have at least one to be monocrystalline silicon layer in the two, so that formed PN connects the character of face is more consistent, and the electric leakage under reverse bias also can reduce.Therefore, it is more consistent to utilize this PN to connect the characteristic of single programmable read-only memory cell of face, and electrical leakage quantity also can reduce.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
The formation PN that Figure 1A-1C is depicted as first embodiment of the invention connects the method for face, and wherein Fig. 1 C is depicted as the structure of the single programmable read-only memory cell of first embodiment.
The formation PN that Fig. 2 A-2C is depicted as second embodiment of the invention connects the method for face.
Fig. 3 A-3D is depicted as the single programmable read-only memory processing procedure of third embodiment of the invention, and wherein Fig. 3 B/3C/3D is depicted as the structure of the single programmable read-only memory with individual layer/bilayer/three layer memory cell of the 3rd embodiment.
Fig. 4 A-4F is depicted as the single programmable read-only memory processing procedure of fourth embodiment of the invention, and wherein Fig. 4 C/4E/4F is depicted as the structure of the single programmable read-only memory with individual layer/bilayer/three layer memory cell of the 4th embodiment.
Graphic sign explanation
100,200: substrate 110,210:N type doped layer
120,220: dielectric layer 130,230: crystal nucleation layer
140,240: insulating barrier 150,250: opening
160,260:P type silicon layer 160a, 260a:P type monocrystalline silicon layer
300,400: substrate
310,410: conductive layer
320,358,368,420,456,470:N type doped layer
330,360,370,430,460,472: antifuse layer (Antifuse Layer)
340,362,372,454,466: crystal nucleation layer
342,363,367,373,380,442,461,469,475: stack architecture
350,352,374,445,450,476: insulating barrier
353,375,452: irrigation canals and ditches
354,364,376:P type doped layer
356,366,378,458,468,478: conductor layer
364a, 440a, 462a, 474a:P type monocrystalline silicon layer/piece
440,462,474:P type amorphous silicon layer
464: mask layer
Embodiment
First embodiment
Please refer to Figure 1A-1C, the formation PN that is depicted as first embodiment of the invention connects the method for face, and wherein Fig. 1 C is depicted as the structure of the single programmable read-only memory cell of first embodiment.
Please refer to Figure 1A, at first in substrate 100, form the stack architecture of N type doped layer 110, dielectric layer 120 and crystal nucleation layer 130.Wherein, substrate 100 can be an insulating barrier, also can be semi-conductor layer, for example is the top layer of monocrystalline silicon wafer crystal; And when substrate 100 was the top layer of monocrystalline silicon wafer crystal, N type doped layer 110 can be formed directly in substrate 100, and the material of N type doped layer 110 is monocrystalline silicon at this moment.In addition, the material of N type doped layer 110 also can be polysilicon, and it for example is that mode with in-situ doped (in-situ doping) is deposited in the substrate 100.The material of dielectric layer 120 for example is a silica, and it can Low Pressure Chemical Vapor Deposition (LPCVD) or thermal oxidation method (Thermal Oxidation) formation.The material of crystal nucleation layer 130 for example is a silicon nitride, and its formation method for example is a Low Pressure Chemical Vapor Deposition; And when the material of dielectric layer 120 was silica, the mode that then can heat the top layer of nitrogenize dielectric layer 120 formed the crystal nucleation layer 130 of silicon nitride material.
Please refer to Figure 1B, then form insulating barrier 140 in substrate 100, its material for example is a silica, and the formation method for example is aumospheric pressure cvd method (APCVD).In insulating barrier 140, form opening 150 then, its step for example is to comprise a lithographic process and subsequent anisotropic electric slurry etch process, in opening 150, insert P type silicon layer 160 again, its material is polysilicon or amorphous silicon, and this inserts step for example is to comprise low-pressure chemical vapor deposition processing procedure (LPCVD) and subsequent eat-back (Etching-back, EB) or cmp (Chemical Mechanical Polishing, CMP) processing procedure.
Please refer to Fig. 1 C, then carry out a tempering step, so that P type silicon layer 160 by the 130 places initial recrystallization of adjacency crystal nucleation layer, shown in the arrow direction, and forms p type single crystal silicon layer 160a.The temperature of this tempering manufacturing process is preferably 500 ~ 550 ℃, and the time of carrying out increases with the thickness of P type silicon layer 160.Then, between N type doped layer 110 and p type single crystal silicon layer 160a, apply enough forward biases,, promptly get PN and connect face so that crystal nucleation layer 130 is electrically collapsed with dielectric layer 120.
On the other hand, the structure of the single programmable read-only memory cell of present embodiment is shown in Fig. 1 C.This memory cell comprises N type doped layer 110 in the substrate 100, the antifuse layer 120 on the N type doped layer 110, the crystal nucleation layer 130 on the antifuse layer 120, and the p type single crystal silicon layer 160a on the crystal nucleation layer 130.Certainly, N type doped layer 110 can exchange with the dopant profile of p type single crystal silicon layer 160a, and this should be the known item of those skilled in the art.
Second embodiment
Please refer to Fig. 2 A-2C, the formation PN that is depicted as second embodiment of the invention connects the method for face.
Please refer to Fig. 2 A, at first in substrate 200, form the stack architecture of N type doped layer 210, dielectric layer 220 and P type silicon layer 260, in substrate 200, form insulating barrier 240 again.The material of wherein, substrate 200, N type doped layer 210, dielectric layer 220, insulating barrier 240 and P type silicon layer 260 and formation method are all as described in first embodiment.
Please refer to Fig. 2 B, then form opening 250 in insulating barrier 240, form crystal nucleation layer 230 again on the P type silicon layer 260 that opening 250 is exposed, it for example is a germanium crystal seed layer.The formation method of germanium crystal seed layer for example is to comprise the following steps: at first with GeH
4Be reacting gas, under 450 ℃, carry out selectivity low-pressure chemical vapor deposition (LPCVD) processing procedure,, under 550 ℃, make polycrystalline germanium crystallization more again, and be transformed into monocrystalline germanium on P type silicon layer 260, to form polycrystalline germanium.
Please refer to Fig. 1 C, then carry out a tempering step, so that the P type silicon layer 260 of crystal nucleation layer 230 belows by the 230 places initial recrystallization of adjacency crystal nucleation layer, shown in the arrow direction, and forms p type single crystal silicon layer 260a (be roughly dotted line and enclose the place).The temperature of this tempering manufacturing process is preferably 500 ~ 550 ℃, and the time of carrying out increases with the thickness of P type silicon layer 260.Then, between N type doped layer 210 and p type single crystal silicon layer 260a, apply enough forward biases,, promptly get PN and connect face so that dielectric layer 220 electrically collapses.
In addition, two doped layers 210 and 260 dopant profile are also interchangeable among above-mentioned second embodiment, and this should be the known item of those skilled in the art, does not give unnecessary details so its reason does not add.Yet, what is particularly worth mentioning is that, in above-mentioned first and second embodiment, it is monocrystalline silicon that one material is arranged in N type doped layer and P type doped layer, another person's material is a polysilicon, and the main carrier concentration of the two differs very greatly when meeting specific demand, and material is preferably the lower doped layer of main carrier concentration for the monocrystalline silicon person, so that PN connects the character of face is more consistent.This is because after PN connects face and forms, and the exhaustion region in the lower doped layer of main carrier concentration is than broad, and its uniformity requirement is also higher, thus preferable be its material with the neat monocrystalline silicon of lattice arrangement.
As mentioned above, connect in the surface forming method at the PN of first and second embodiment of the present invention, constitute the P type doped layer and N type doped layer that PN connects face and have at least one to be monocrystalline silicon layer in the two, so that formed PN connects the character of face is more consistent, and the electric leakage under reverse bias also can reduce.Therefore, it is also more consistent to utilize this PN to connect the characteristic of the single programmable read-only memory cell of face or other assembly, and electrical leakage quantity also can reduce.
The 3rd embodiment
Please refer to Fig. 3 A-3D, be depicted as the single programmable read-only memory processing procedure of third embodiment of the invention, wherein Fig. 3 B/3C/3D is depicted as the single programmable read-only memory structure with individual layer/bilayer/three layer memory cell of the 3rd embodiment.
Please refer to Fig. 3 A, in substrate 300, form conductor layer 310, N type doped layer 320, antifuse layer 330 and crystal nucleation layer 340 at first in regular turn.Wherein, when the top layer of substrate 300 was insulator, the material of conductor layer 310 for example was a metal silicide, and its formation method for example is a Low Pressure Chemical Vapor Deposition; And when substrate 300 was the top layer of monocrystalline silicon wafer crystal, 310 of conductor layers can be the high concentration N type doped layer (N that is formed on wherein
+Layer).The material of N type doped layer 320 for example is a polysilicon, and its formation method for example is the Low Pressure Chemical Vapor Deposition of in-situ doped (in-situ doping); N type doped layer 320 also can be formed in the N type doped layer on monocrystalline silicon wafer crystal top layer, and the material of N type doped layer 320 is monocrystalline silicon at this moment.The material of antifuse layer 330 for example is a silica, and its formation method can be chemical vapour deposition technique (CVD) or thermal oxidation method.The material of crystal nucleation layer 340 for example is a silicon nitride, and its formation method for example is Low Pressure Chemical Vapor Deposition or heating nitriding.Then use same mask patterning crystal nucleation layer 340, antifuse layer 330, N type doped layer 320 and conductor layer 310 in regular turn, to form many parallel strip stack architectures 342, wherein conductor layer 310 is as the character line of ground floor memory cell.Then, insert insulating barrier 350 between each stack architecture 342, its material for example is a silica.
Please refer to Fig. 3 B, then form insulating barrier 352 in substrate 300, patterned insulation layer 352 to be forming many parallel irrigation canals and ditches 353 again, and its trend is vertical with stack architecture 342 in the last insulating barrier 350.Then, in irrigation canals and ditches 353, insert P type doped layer 354, conductor layer 356, N type doped layer 358, antifuse layer 360 and crystal nucleation layer 362 in regular turn, to form stack architecture 363.Wherein, the material of P type doped layer 354 is amorphous silicon or polysilicon, conductor layer 356 is as the bit line of ground floor and second layer memory cell, N type doped layer 358, antifuse layer 360 and crystal nucleation layer 362 are the part of second layer memory cell, and the material of conductor layer 356, N type doped layer 358, antifuse layer 360 and crystal nucleation layer 362 as previously mentioned.What should be specified is if that as long as form one deck memory cell, the step of inserting that then above step only must proceed to conductor layer 356 gets final product herein.Next carry out a tempering step, so that be transformed into monocrystalline silicon layer with the P type doped layer 354 of crystal nucleation layer 340 contact portions, promptly finished the making of ground floor memory cell, the crystal nucleation layer 340 of wherein arbitrary p type single crystal silicon layer 354, its below and antifuse layer 330, and the N type doped layer 320 of the overlapping part of p type single crystal silicon layer 354 is set up into a memory cell jointly therewith.
Please refer to Fig. 3 C, then repeat the formation insulating barrier shown in Fig. 3 B, definition irrigation canals and ditches, and the step of inserting P type doped layer (364) Yu the conductor layer (366) of amorphous silicon or polysilicon, its difference only is that the trend of irrigation canals and ditches in this insulating barrier is vertical with the trend of irrigation canals and ditches 353 in the last insulating barrier 352, be the direction of parallel paper, so the irrigation canals and ditches that this insulating barrier reaches wherein are not shown among Fig. 3 C.Then carry out tempering, so that the P type doped layer 364 of each crystal nucleation layer 362 upper section is transformed into monocrystalline silicon layer 364a, promptly finish the memory cell of the second layer, the crystal nucleation layer 362 of wherein arbitrary p type single crystal silicon layer 364a, its below and antifuse layer 360, and the N type doped layer 358 of the overlapping part of p type single crystal silicon layer 364a is set up into a memory cell jointly therewith.In addition, conductor layer 366 is as the character line of second layer memory cell.
The rest may be inferred, carries out above-mentioned steps as long as continue circulation, can form more high-rise memory cell.For instance, please refer to Fig. 3 D, as on each conductor layer 366, continue to form N type doped layer 368, antifuse layer 370 and crystal nucleation layer 372 in the mode of inlaying, the stack architecture 373 of the P type doped layer 364 of gained, p type single crystal silicon layer 364a, conductor layer 366, N type doped layer 368, antifuse layer 370 and crystal nucleation layer 372 is promptly identical with the stack architecture 363 of crystal nucleation layer 362 with the P type doped layer 354 shown in Fig. 3 B, conductor layer 356, N type doped layer 358, antifuse layer 360, and what difference only was this levels stack architecture 363 and 373 moves towards orthogonal.Then, continue to form insulating barrier 374, and form the stack architecture 380 of the polysilicon that is arranged in irrigation canals and ditches 375 or amorphous silicon P type doped layer 376 and conductor layer 378 with above-mentioned mosaic mode, tempering has promptly been finished the 3rd layer of memory cell so that the P type doped layer 376 on the crystal nucleation layer 372 is transformed into monocrystalline silicon then.
In brief, as long as constantly repeat the formation insulating barrier shown in Fig. 3 B or the 3D, definition irrigation canals and ditches, and the step that forms the stack architecture of P type doped layer, conductor layer, N type doped layer, antifuse layer and crystal nucleation layer with mosaic mode, can form single programmable read-only memory with multilayer memory cell, the trend of the irrigation canals and ditches/stack architecture in the two wherein neighbouring insulating barriers is vertical, as the stack architecture 342 of Fig. 3 B and 363 situation.In addition, last formed stack architecture that circulates only comprises P type doped layer and conductor layer, and shown in Fig. 3 C-3D, wherein conductor layer is as the character line or the bit line of top memory cell.This is because no longer form other memory cell on the top memory cell, so top stack architecture needn't form N type doped layer, antifuse layer and crystal nucleation layer.
On the other hand, with regard to the structure of the single programmable read-only memory of this 3rd embodiment, as long as form the individual layer memory cell, the step of inserting that then above step proceeds to the conductor layer 356 shown in Fig. 3 B gets final product; Form two-layer memory cell as needing only, the step of inserting that then above step proceeds to the conductor layer 366 shown in the 3C figure gets final product.Conclude, shown in Fig. 3 C and 3D, the three-dimensional space single programmable read-only memory of this 3rd embodiment comprises at least three layers of strip stack architecture, wherein neighbouring two-layer stack architecture move towards difference (as 363 and 373), and each stack architecture (is example with 363) all comprises P type silicon layer (354), conductor layer (356), n type semiconductor layer (358), the antifuse layer (360) of storehouse from the bottom to top, and crystal nucleation layer (362).Wherein, undermost stack architecture 342 does not comprise P type silicon layer, and shown in Fig. 3 C-3D, conductor layer there is no P type silicon layer for 310 times; And the stack architecture of the superiors does not comprise n type semiconductor layer, antifuse layer and crystal nucleation layer, shown in Fig. 3 D, there is no other layer on the conductor layer 378.In addition, each P type silicon layer (is example with 364) all is made of a plurality of monocrystalline silico briquettes (364a) and polysilicon block therebetween, wherein arbitrary monocrystalline silico briquette (364a) is positioned on the crystal nucleation layer (362) of the structure of layer stack once (363) that P type silicon layer (364) therewith overlaps, and arbitrary polysilicon block is positioned between the two monocrystalline silico briquettes (364a).
In addition, as known to persons skilled in the art, the dopant profile of each P type doped layer and N type doped layer is also interchangeable in the single programmable read-only memory of above-mentioned the 3rd embodiment, to satisfy actual demand.
As mentioned above, in the single programmable read-only memory of third embodiment of the invention, constitute the P type doped layer and N type doped layer that PN connects face and have at least one to be monocrystalline silicon layer in the two, so that PN connects the character of face is more consistent, and the electric leakage under reverse bias also can reduce.Therefore, it is also more consistent to utilize this PN to connect the characteristic of single programmable read-only memory cell of face, and electrical leakage quantity also can reduce.
In addition, present embodiment will define the damascene process that promptly needs originally in the step of formation position of monocrystalline silicon and the processing procedure and integrate, that is form monocrystalline silicon layer on the crystal nucleation layer that opening exposed of interlayer insulating film.Therefore, the present invention needn't use one extra light shield to define high grain density layer (being equal to above-mentioned crystal nucleation layer) or low grain density layer (being equal to above-mentioned antifuse layer) as prior art method.
The 4th embodiment
Fig. 4 A-4F is depicted as the single programmable read-only memory processing procedure of fourth embodiment of the invention, and wherein Fig. 4 C/4E/4F is depicted as the structure of the single programmable read-only memory with individual layer/bilayer/three layer memory cell of the 4th embodiment.
Please refer to Fig. 4 A, form conductive layer 410, N type doped layer 420, antifuse layer 430 and P type amorphous silicon layer 440 at first in regular turn in substrate 400, wherein the material and the formation method of conductor layer 410, N type doped layer 420, antifuse layer 430 can be as previously described.Then, above-mentioned each layer of patterning in regular turn, to form many parallel strip stack architectures 442,442 at each stack architecture insert insulating barrier 445 then.Wherein, conductor layer 410 is as the character line of ground floor memory cell.
Please refer to Fig. 4 B, then form another insulating barrier 450 in substrate 400, in wherein forming many parallel irrigation canals and ditches 452, its trend is perpendicular with the stack architecture 442 in the insulating barrier 445 again.Form crystal nucleation layer 454 then on the P type amorphous silicon layer 440 that irrigation canals and ditches 452 are exposed, it for example is a germanium crystal seed layer.Because the formation method of germanium crystal seed layer describes in detail in second embodiment, so no longer given unnecessary details.Then carry out a tempering step, its temperature is preferable between 500 ℃ to 550 ℃, so that the P type amorphous silicon layer 440 of crystal nucleation layer 454 below parts is transformed into p type single crystal silicon layer 440a.P type single crystal silicon layer 440a, N type doped layer 420 and antifuse layer 430 have therebetween promptly constituted the memory cell of ground floor at this moment.
Please refer to Fig. 4 C, then remove crystal nucleation layer 454, in irrigation canals and ditches 452, insert conductor layer 456, N type doped layer 458 and antifuse layer 460 more in regular turn, to form stack architecture 461, wherein conductor layer 456 is as the bit line of its below ground floor memory cell with its top second layer memory cell, and N type doped layer 458 and antifuse layer 460 are the part of second layer memory cell.That is to say that form one deck memory cell as needing only, the step of inserting that then above step proceeds to conductor layer 456 gets final product.
Please refer to Fig. 4 D, then above substrate 400, form another P type amorphous silicon layer 462, on P type amorphous silicon layer 462, form the mask layer 464 of patterning then, it exposes a plurality of parts of P type amorphous silicon layer 462, wherein each part is positioned at the top of a N type doped layer 458, so it is also strip.The material of this mask layer 464 for example is that (Low-Temperature Oxide, LTO), it forms with electric pulp vapour deposition process (PECVD) cryogenic oxidation silicon.Then, form the crystal nucleation layer 466 of strip on the strip part that P type amorphous silicon layer 462 is exposed, it for example is above-mentioned germanium crystal seed layer.Then carry out tempering, so that the P type amorphous silicon layer 462 of crystal nucleation layer 466 belows is transformed into p type single crystal silicon layer 462a.After forming p type single crystal silicon layer 462a, can remove mask layer 464 and crystal nucleation layer 466.
Please refer to Fig. 4 E, then comprising formation conductor layer 468 on the P type amorphous silicon layer 462 of monocrystalline silicon layer 462a, define conductor layer 468 and the P type amorphous silicon layer 462 that comprises monocrystalline silicon layer 462a again, to form stack architecture 469, its trend is vertical with stack architecture 461 among the last insulating barrier 450, and identical with the stack architecture 442 of the bottom.Wherein, the conductor layer after the definition 468 is as the character line of second layer memory cell.So, promptly finished second layer memory cell, the antifuse layer 460 of wherein arbitrary p type single crystal silicon layer 462a, its below, and the N type doped layer 458 of this p type single crystal silicon layer 462a below part constitutes a single programmable read-only memory cell.
Moreover as the situation of the 3rd embodiment, as long as above-mentioned steps is carried out in circulation, the single programmable read-only memory processing procedure of this 4th embodiment also can form the three-dimensional space internal memory with multilayer memory cell.Please be simultaneously with reference to Fig. 4 E and 4F, form the 3rd layer of memory cell as desire, before then must and comprising the P type amorphous silicon layer 462 of monocrystalline silicon layer 462a at definition conductor layer 468, prior to forming more N type doped layer 470, the antifuse layer 472 and P type amorphous silicon layer 474 on upper strata on the conductor layer 468, and then patterning P type amorphous silicon layer 474, antifuse layer 472, N type doped layer 470, conductor layer 468 and P type amorphous silicon layer 462 in regular turn, forming the stack architecture 475 of strip, its trend is vertical with stack architecture 461 in the last insulating barrier 450.Then, repeat the insert step of the formation step of the monocrystalline silicon layer (440a) shown in Fig. 4 B to the conductor layer (456) shown in Fig. 4 C, to form monocrystalline silicon layer 474a, insulating barrier 476 and to be embedded in conductor layer 478 in the insulating barrier 476, promptly get OTP-ROM with three layers of memory cell.
Moreover, after forming, repeat the step of the formation step of the monocrystalline silicon layer (440a) shown in Fig. 4 B to the definition character line (468) shown in Fig. 4 E at stack architecture 475, promptly get OTP-ROM with four layers of memory cell.The rest may be inferred, till the memory cell of producing predetermined number of layers.
On the other hand, with regard to the structure of the single programmable read-only memory of this 4th embodiment, as long as form the individual layer memory cell, the step of inserting that then above step proceeds to the conductor layer 456 shown in Fig. 4 C gets final product; Form two-layer memory cell as needing only, the definition step that then above step proceeds to conductor layer 468 shown in Fig. 4 E and P type amorphous silicon layer 462 gets final product.Conclude, shown in Fig. 4 E-4F, the three-dimensional space single programmable read-only memory of this 4th embodiment comprises at least three layers strip stack architecture (442,461 and 469), wherein neighbouring two-layer strip stack architecture move towards difference, situation as 442 and 461, or 461 and 469 situation.
Please continue the E-4F with reference to Fig. 4, each stack architecture in the odd-level (is example with 475) comprises P type lower silicon layer (462), conductor layer (468), n type semiconductor layer (470), the antifuse layer (472) of storehouse from the bottom to top, and P type upper silicon layer (474).Wherein, the stack architecture of ground floor does not comprise lower silicon layer, shown in Fig. 4 E-4F, there is no other layer under the conductor layer 410.In addition, when top layer person was odd-level, the stack architecture of this top layer did not comprise n type semiconductor layer, antifuse layer and P type upper silicon layer, and shown in Fig. 4 E, its top layer is the 3rd layer, and there is no other layer on the conductor layer 468.Each stack architecture in each even level (is example with 461) comprises the conductor layer of storehouse (456), n type semiconductor layer (458) from the bottom to top, and antifuse layer (460).In addition, when top layer was even level, the stack architecture of this top layer did not comprise semiconductor layer and antifuse layer, and shown in 4F, its top layer is the 4th layer, and there is no other layer on the conductor layer 478.Simultaneously, the lower silicon layer of the stack architecture of odd-level (is example with 462) is made of lower mono-crystalline silicon piece (462a) and following amorphous silico briquette therebetween, wherein arbitrary lower mono-crystalline silicon piece (462a) is positioned on the antifuse layer (460) of the stack architecture of even level once (461) that overlaps with this lower silicon layer (462), and arbitrary amorphous silico briquette down is positioned between the two lower mono-crystalline silicon pieces (462a).In addition, the upper silicon layer of the stack architecture of odd-level (being example with 440) is made of last monocrystalline silico briquette (440a) and last amorphous silico briquette therebetween, wherein arbitrary go up monocrystalline silico briquette (440a) be positioned at this upper silicon layer (440) overlap one under the conductor layer (456) of even level stack architecture (461), and arbitrary amorphous silico briquette of going up is positioned on two between the monocrystalline silico briquette (440a).
In addition, as known to persons skilled in the art, the dopant profile of each P type doped layer and N type doped layer is also interchangeable in the single programmable read-only memory of above-mentioned the 4th embodiment, to satisfy actual demand.
As mentioned above, in the single programmable read-only memory of fourth embodiment of the invention, constitute the P type doped layer and N type doped layer that PN connects face and have at least one to be monocrystalline silicon layer in the two, so that PN connects the character of face is more consistent, and the electric leakage under reverse bias also can reduce.Therefore, it is also more consistent to utilize this kind PN to connect the characteristic of single programmable read-only memory cell of face, and electrical leakage quantity also can reduce.
In addition, the monocrystalline silicon layer shown in Fig. 4 B forms the damascene process that originally promptly has in step and the processing procedure and integrates, that is forms crystal nucleation layer 454 in the opening 452 of interlayer insulating film 450, makes the amorphous silicon of its below be transformed into monocrystalline silicon again.Therefore, the sacrifice layer that this step needn't form and patterning is extra is with the formation position of definition crystal nucleation layer.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (43)
1. one kind forms the method that PN connects face, it is characterized in that comprising:
Form a stack architecture in a substrate, this stack architecture comprises one first doped layer, a dielectric layer and a crystal nucleation layer from the bottom to top;
Form the insulating barrier with an opening in this substrate, this opening exposes this crystal nucleation layer of part;
In this opening, form one second doped layer, the material of this second doped layer be polysilicon and amorphous silicon the two one of;
Carry out a tempering step, so that this second doped layer changes a monocrystalline silicon layer into; And
This dielectric layer is electrically collapsed,
This first doped layer and this second doped layer have in the two one to be that the P type mixes, and another person is the doping of N type.
2. formation PN as claimed in claim 1 connects the method for face, it is characterized in that this first doped layer comprises another monocrystalline silicon layer.
3. formation PN as claimed in claim 1 connects the method for face, it is characterized in that this first doped layer comprises a polysilicon layer.
4. formation PN as claimed in claim 3 connects the method for face, it is characterized in that the main carrier concentration of the main carrier concentration of this second doped layer less than this first doped layer.
5. formation PN as claimed in claim 1 connects the method for face, it is characterized in that this crystal nucleation layer comprises a silicon nitride layer.
6. formation PN as claimed in claim 1 connects the method for face, it is characterized in that the material of this dielectric layer comprises silica.
7. one kind forms the method that PN connects face, it is characterized in that comprising:
In a substrate, form a stack architecture, this stack architecture comprises storehouse one first doped layer, a dielectric layer and one second doped layer from the bottom to top, wherein this first with this second doped layer the two one of be P type doped layer, another is a N type doped layer, and the material of this second doped layer be polysilicon and amorphous silicon the two one of;
Form the insulating barrier with an opening in this substrate, this opening exposes this second doped layer of part;
Form a crystal nucleation layer on this second doped layer in this opening;
Carry out a tempering step, so that this second doped layer of this crystal nucleation layer below changes a monocrystalline silicon layer into; And
This dielectric layer is electrically collapsed.
8. formation PN as claimed in claim 7 connects the method for face, it is characterized in that this first doped layer comprises another monocrystalline silicon layer.
9. connect the method for face as 7 described formation PN of claim the, it is characterized in that this first doped layer comprises a polysilicon layer.
10. formation PN as claimed in claim 9 connects the method for face, it is characterized in that the main carrier concentration of the main carrier concentration of this second doped layer less than this first doped layer.
11. formation PN as claimed in claim 7 connects the method for face, it is characterized in that this crystal nucleation layer comprises a germanium crystal seed layer.
12. formation PN as claimed in claim 11 connects the method for face, it is characterized in that the method that forms this germanium crystal seed layer comprises:
Optionally on this second doped layer that this opening exposed, deposit polycrystalline germanium; And
Carry out tempering so that the polycrystalline germanium of deposition is transformed into monocrystalline germanium.
13. a single programmable read-only memory processing procedure is characterized in that comprising:
(a). a substrate is provided, be formed with an insulating barrier in this substrate, and the stack architecture of a plurality of strips that is arranged in a plurality of irrigation canals and ditches of this insulating barrier, arbitrary stack architecture comprises the from bottom to top conductor layer with one first dopant profile, semi-conductor layer, an antifuse layer of storehouse, and a crystal nucleation layer;
(b). in this substrate, form a time insulating barrier;
(c). form a plurality of irrigation canals and ditches in this time insulating barrier, the trend of these irrigation canals and ditches is vertical with irrigation canals and ditches in the last insulating barrier, and exposes a plurality of parts of each crystal nucleation layer;
(d). in these irrigation canals and ditches of this time insulating barrier, insert a polysilicon layer of tool one second dopant profile; And
(e). carry out a tempering step, so that this polysilicon layer of these part tops of each of each crystal nucleation layer is transformed into a monocrystalline silicon layer,
This crystal nucleation layer and this antifuse layer of one monocrystalline silicon layer, this monocrystalline silicon layer below, and with the overlapping part semiconductor layer of this monocrystalline silicon layer as a memory cell.
14. single programmable read-only memory processing procedure as claimed in claim 13 is characterized in that:
Each stack architecture more comprises a conductor layer that is positioned at this semiconductor layer below; And
This method more comprises:
(f). in each irrigation canals and ditches of this time insulating barrier, insert a time conductor layer.
15. single programmable read-only memory processing procedure as claimed in claim 14 is characterized in that more comprising the following steps, to form a three-dimensional space internal memory:
(g). formation has the inferior semi-conductor layer of this first dopant profile, an inferior antifuse layer and a time crystal nucleation layer on time conductive layer in each irrigation canals and ditches of this time insulating barrier, and constitutes a time stack architecture; And
Step (b)-(g) is carried out in circulation, and to form the more insulating barrier and the stack architecture on upper strata, till the memory cell that forms predetermined number of layers, the irrigation canals and ditches trend in wherein neighbouring two insulating barriers is vertical, and step (g) is not carried out in last circulation.
16. single programmable read-only memory processing procedure as claimed in claim 14 is characterized in that the method that forms this insulating barrier and these stack architectures in this substrate comprises:
In this substrate, deposit a conductor material, one first type doped semiconductor materials, an anti-fuse materials and a host material in regular turn;
This host material of patterning, this anti-fuse materials, this first type doped semiconductor materials and this conductor material are to form these stack architectures; And
Between these stack architectures, insert an insulating material.
17. single programmable read-only memory processing procedure as claimed in claim 13 is characterized in that the material of this crystal nucleation layer comprises silicon nitride.
18. single programmable read-only memory processing procedure as claimed in claim 13 is characterized in that the material of this antifuse layer comprises silica.
19. a single programmable read-only memory processing procedure is characterized in that comprising:
(a). a substrate is provided, be formed with an insulating barrier in this substrate, and the stack architecture of a plurality of strips that is arranged in a plurality of irrigation canals and ditches of this insulating barrier, arbitrary stack architecture comprises the conductor layer with one first dopant profile, semi-conductor layer, an antifuse layer of storehouse from the bottom to top, and the amorphous silicon layer with one second dopant profile;
(b). in this substrate, form a time insulating barrier;
(c). form a plurality of irrigation canals and ditches in this time insulating barrier, the trend of these irrigation canals and ditches is vertical with irrigation canals and ditches in the last insulating barrier, and exposes a plurality of parts of each amorphous silicon layer in the last insulating barrier;
(d). in these irrigation canals and ditches of this time insulating barrier, form a crystal nucleation layer;
(e). carry out a tempering step, so that these parts of each of each amorphous silicon layer are transformed into a monocrystalline silicon layer;
(f). remove this crystal nucleation layer; And
(g). in each irrigation canals and ditches of this time insulating barrier, form a conductor layer,
This antifuse layer of one monocrystalline silicon layer, this monocrystalline silicon layer below, and with the overlapping part semiconductor layer of this monocrystalline silicon layer as a memory cell.
20. single programmable read-only memory processing procedure as claimed in claim 19 is characterized in that the method that forms this crystal nucleation layer in these irrigation canals and ditches of this time insulating barrier comprises:
Optionally on these parts of these amorphous silicon layers that these irrigation canals and ditches exposed, deposit polycrystalline germanium;
Carry out tempering so that the polycrystalline germanium of deposition is transformed into monocrystalline germanium.
21. single programmable read-only memory processing procedure as claimed in claim 19 is characterized in that more comprising the following steps:
(h). form an inferior semi-conductor layer and a time antifuse layer on this conductor layer in each irrigation canals and ditches of this time insulating barrier with this first dopant profile;
(i). in this substrate, form a time amorphous silicon layer with this second dopant profile;
(j). form the crystal nucleation layer of a plurality of strips on this time amorphous silicon layer, wherein arbitrary crystal nucleation layer position is above a semi-conductor layer;
(k). carry out a tempering step, so that this time amorphous silicon layer of a plurality of parts of these crystal nucleation layer belows is transformed into monocrystalline silicon;
(l). remove these crystal nucleation layer;
(m). on this interior time amorphous silicon layer, form a time conductor layer in comprising monocrystalline silicon; And
(n). define this time conductor layer and comprise monocrystalline silicon at this interior time amorphous silicon layer, forming a plurality of strip stack architectures, the trend of these stack architectures is vertical with these irrigation canals and ditches in this time insulating barrier.
22. single programmable read-only memory processing procedure as claimed in claim 21 is characterized in that forming a plurality of crystal nucleation layer on this time amorphous silicon layer, promptly the method for step (j) comprising:
On this time amorphous silicon layer, form a mask layer;
This mask layer of patterning is to form a plurality of irrigation canals and ditches, and wherein arbitrary irrigation canals and ditches expose this time amorphous silicon layer of the strip part that is positioned at a semi-conductor layer top; And
Optionally on this time amorphous silicon layer that exposes, form monocrystalline germanium, with as these crystal nucleation layer; And
This manufacture method more comprises:
Before forming this time conductor layer, remove this mask layer.
23. single programmable read-only memory processing procedure as claimed in claim 22 is characterized in that the material of this mask layer comprises cryogenic oxidation silicon.
24. single programmable read-only memory processing procedure as claimed in claim 21 is characterized in that:
Step (m) more comprises forming in regular turn to have another semiconductor layer, the another antifuse layer of this first dopant profile and have this second another amorphous silicon layer that mixes on this time conductor layer, and step (n) defines this another amorphous silicon layer, this another antifuse layer, this another semiconductor layer, this time conductor layer and this time amorphous silicon layer in regular turn, and a plurality of strip stack architectures, the trend of these stack architectures is vertical with these irrigation canals and ditches in this time insulating barrier.
25. single programmable read-only memory as claimed in claim 21 is made, and it is characterized in that this manufacture method more comprises:
Step (o). between these stack architectures, insert another insulating barrier; And
Step (b)-(o) is carried out in circulation, and forming the more insulating barrier and the stack architecture on upper strata, till the memory cell that forms predetermined number of layers, this circulation step ends at step (g) or (n).
26. single programmable read-only memory processing procedure as claimed in claim 19, wherein each stack architecture more comprises an end conductor layer that is positioned at this semiconductor layer below.
27. single programmable read-only memory processing procedure as claimed in claim 26, the method that wherein forms these stack architectures in this substrate comprises:
In this substrate, deposit a conductor material, one first type doped semiconductor materials, an anti-fuse materials and one second type doped amorphous silicon material in regular turn;
This second type doped amorphous silicon material of patterning, this anti-fuse materials, this first type doped semiconductor materials and this conductor material are to form these stack architectures; And
Between these stack architectures, insert an insulating material.
28. single programmable read-only memory processing procedure as claimed in claim 19, wherein this crystal nucleation layer comprises a germanium crystal seed layer.
29. a single programmable read-only memory cell comprises:
One first doped layer is positioned in the substrate, and has one first dopant profile;
One antifuse layer is positioned on this first doped layer;
One crystal nucleation layer is positioned on this antifuse layer; And
One second doped layer is positioned on this crystal nucleation layer, and has one second dopant profile, and the material of this second doped layer is a monocrystalline silicon.
30. single programmable read-only memory cell as claimed in claim 29, wherein the material of this first doped layer comprises monocrystalline silicon.
31. single programmable read-only memory cell as claimed in claim 29, wherein the material of this first doped layer is a polysilicon.
32. single programmable read-only memory cell as claimed in claim 31, wherein the main carrier concentration of this second doped layer is less than the main carrier concentration of this first doped layer.
33. single programmable read-only memory cell as claimed in claim 29, wherein the material of this crystal nucleation layer comprises silicon nitride.
34. single programmable read-only memory cell as claimed in claim 29, wherein the material of this antifuse layer comprises silica.
35. a single programmable read-only memory comprises:
The stack architecture of a plurality of strips, each stack architecture all comprise the from bottom to top conductor layer with one first dopant profile, semi-conductor layer, an antifuse layer of storehouse, and a crystal nucleation layer; And
A plurality of strip silicon layers with one second dopant profile, be positioned at these stack architecture tops, and it is vertical with these stack architecture trends, each strip silicon layer all is made of a plurality of polysilicon blocks and a plurality of monocrystalline silico briquette alternately arranged, arbitrary monocrystalline silico briquette is positioned on this crystal nucleation layer of a stack architecture that overlaps with this strip silicon layer, and arbitrary polysilicon block is between two monocrystalline silico briquettes.
36. single programmable read-only memory as claimed in claim 35, wherein each stack architecture more comprises an end conductor layer that is positioned at this semiconductor layer below, and more disposes a upper conductor layer on each strip silicon layer.
37. single programmable read-only memory as claimed in claim 35, wherein the material of this crystal nucleation layer comprises silicon nitride.
38. single programmable read-only memory as claimed in claim 35, wherein the material of this antifuse layer comprises silica.
39. a single programmable read-only memory comprises:
The stack architecture of at least three layers of strip, each layer all comprises a plurality of stack architectures, and the trend of neighbouring two-layer stack architecture is vertical, and each stack architecture comprises the silicon layer with one second dopant profile, a conductor layer, the semi-conductor layer with one first dopant profile, an antifuse layer of storehouse from the bottom to top, an and crystal nucleation layer
Undermost stack architecture does not comprise this silicon layer, and the stack architecture of the superiors does not comprise this semiconductor layer, this antifuse layer and this crystal nucleation layer; And
Each silicon layer all is made of a plurality of polysilicon blocks and a plurality of monocrystalline silico briquette alternately arranged, and arbitrary monocrystalline silico briquette is positioned on this crystal nucleation layer of the structure of layer stack once that overlaps with this silicon layer, and arbitrary polysilicon block is between two monocrystalline silico briquettes.
40. a single programmable read-only memory comprises:
A plurality of strip stack architectures, it is positioned in the substrate, and each stack architecture all comprises the conductor layer with one first dopant profile, semi-conductor layer, an antifuse layer of storehouse from the bottom to top, and has one of one second dopant profile silicon layer; And
A plurality of strip conductor layers, it is positioned at these stack architecture tops, and the trend of these strip conductor layers is different with these stack architectures, and vertical with these stack architecture trends,
Each silicon layer all is made of a plurality of amorphous silico briquettes and a plurality of monocrystalline silico briquette alternately arranged, and arbitrary monocrystalline silico briquette is positioned under the strip conductor layer that overlaps with this silicon layer, and arbitrary amorphous silico briquette is between two monocrystalline silico briquettes.
41. single programmable read-only memory as claimed in claim 40, wherein each stack architecture more comprises an end conductor layer that is positioned at this semiconductor layer below.
42. single programmable read-only memory as claimed in claim 40, wherein the material of this antifuse layer comprises silica.
43. a single programmable read-only memory comprises:
The stack architecture of at least three layers of strip, each layer all comprises a plurality of stack architectures, and the trend of neighbouring two-layer stack architecture is vertical,
Each stack architecture in each odd-level all comprises the lower silicon layer with one second dopant profile, a conductor layer, the semi-conductor layer with one first dopant profile, an antifuse layer of storehouse from the bottom to top, and a upper silicon layer with this second dopant profile, the stack architecture of ground floor does not comprise this lower silicon layer, and when top layer was odd-level, the stack architecture of this top odd-level did not comprise this semiconductor layer, this antifuse layer and this upper silicon layer;
Each stack architecture in each even level all comprise storehouse from the bottom to top a conductor layer, have the semi-conductor layer of this first dopant profile, an and antifuse layer, and when top layer was even level, the stack architecture of this top even level did not comprise this semiconductor layer and this antifuse layer;
This lower silicon layer of each stack architecture in one odd-level is made of a plurality of amorphous silico briquettes down and a plurality of lower mono-crystalline silicon piece alternately arranged, arbitrary lower mono-crystalline silicon piece is positioned on this antifuse layer of the stack architecture of even level once that overlaps with this lower silicon layer, and arbitrary amorphous silico briquette down is between two lower mono-crystalline silicon pieces; And
This upper silicon layer of each stack architecture in one odd-level is made of a plurality of upward amorphous silico briquettes of alternately arranging and a plurality of monocrystalline silico briquette of going up, arbitrary go up the monocrystalline silico briquette be positioned at this upper silicon layer overlap one under this conductor layer of even level stack architecture, and arbitrary amorphous silico briquette of going up is on two between the monocrystalline silico briquette.
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| JPH05144737A (en) * | 1991-11-21 | 1993-06-11 | Sony Corp | Chemical vapor phase growth method |
| JPH0738062A (en) * | 1993-07-22 | 1995-02-07 | Nec Corp | Manufacture of semiconductor device |
| JPH0786601A (en) * | 1993-09-10 | 1995-03-31 | Hitachi Ltd | Polycrystalline silicon mos transistor and manufacture thereof |
| US6093617A (en) * | 1997-05-19 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Process to fabricate hemispherical grain polysilicon |
| JP2001237446A (en) * | 2000-02-23 | 2001-08-31 | Mitsubishi Heavy Ind Ltd | Thin-film polycrystalline silicon, silicon-based photoelectric conversion element and its manufacturing method |
-
2003
- 2003-09-01 CN CNB031564844A patent/CN1309016C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05144737A (en) * | 1991-11-21 | 1993-06-11 | Sony Corp | Chemical vapor phase growth method |
| JPH0738062A (en) * | 1993-07-22 | 1995-02-07 | Nec Corp | Manufacture of semiconductor device |
| JPH0786601A (en) * | 1993-09-10 | 1995-03-31 | Hitachi Ltd | Polycrystalline silicon mos transistor and manufacture thereof |
| US6093617A (en) * | 1997-05-19 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Process to fabricate hemispherical grain polysilicon |
| JP2001237446A (en) * | 2000-02-23 | 2001-08-31 | Mitsubishi Heavy Ind Ltd | Thin-film polycrystalline silicon, silicon-based photoelectric conversion element and its manufacturing method |
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| CN1591780A (en) | 2005-03-09 |
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