CN1307710C - Method for producing flash memory storing unit - Google Patents
Method for producing flash memory storing unit Download PDFInfo
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- CN1307710C CN1307710C CNB2004100312298A CN200410031229A CN1307710C CN 1307710 C CN1307710 C CN 1307710C CN B2004100312298 A CNB2004100312298 A CN B2004100312298A CN 200410031229 A CN200410031229 A CN 200410031229A CN 1307710 C CN1307710 C CN 1307710C
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 238000000034 method Methods 0.000 claims abstract description 96
- 238000002161 passivation Methods 0.000 claims abstract description 42
- 238000007667 floating Methods 0.000 claims description 59
- 239000000463 material Substances 0.000 claims description 41
- 239000004020 conductor Substances 0.000 claims description 39
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 abstract 3
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- 238000005516 engineering process Methods 0.000 description 21
- 230000008569 process Effects 0.000 description 18
- 238000002955 isolation Methods 0.000 description 8
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- 238000007254 oxidation reaction Methods 0.000 description 7
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Abstract
The present invention relates to a manufacturing method for a flash memory cell. The method firstly provides a substrate, and a patterned masking layer is formed on the substrate. The patterned masking layer is used as a mask, the substrate is etched, and a groove is formed in the substrate. After a first dielectric layer is formed on the substrate, and a first grid and a second grid are formed on the side wall of the groove. A first source region / drain region is formed in the substrate of the bottom of the groove. After a second dielectric layer is formed on the substrate, a passivation layer is formed on the second dielectric layer. Parts of the passivation layer, the second dielectric layer and the first dielectric layer are removed, and after a third grid is filled in the groove, the masking layer is removed. A third dielectric layer is formed on the substrate. Finally, after a fourth grid and a fifth grid are formed on the side walls of the first grid and the second grid, a second source region / drain region is formed on the substrate at the sides of the fourth grid and the fifth grid.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, and be particularly related to a kind of flash memory cell and manufacture method thereof.
Background technology
Flash element is owing to have and can repeatedly carry out the actions such as depositing in, read, wipe of information, and the information that deposits in the advantage that also can not disappear after outage.Therefore, become PC and electronic equipment a kind of non-volatile memory element of extensively adopting.
Typical flash element is made floating grid (Floating Gate) and control grid (Control Gate) (stacked grid structure) with doped polycrystalline silicon.And, be separated by with dielectric layer between grid between floating grid and the control grid, and be separated by with tunnel oxide (Tunnel Oxide) between floating grid and substrate.
When flash memory being write the operation of (Write) information, by applying bias voltage, so that electronics injects floating grid in control grid and source/drain regions.During information in reading flash memory, apply operating voltage on the control grid, this moment, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel), and the ON/OFF of this raceway groove is to judge that the value of information " 0 " or " 1 " is a foundation.When flash memory the information of carrying out wipe (Erase) time, the relative current potential of substrate, source region, drain region or control grid is improved, utilizing tunneling effect to make electronics pass tunnel oxide (Tunneling Oxide) and drain into (being Substrate Erase or Drain (Source) Side Erase) in substrate or the leakage (source) extremely, or pass dielectric layer between grid and drain in the control grid by floating grid.
Yet, during information in erasing flash memory,, therefore easily make floating grid discharge polyelectron and have positive charge because the electron amount of discharging from floating grid is wayward, this phenomenon is referred to as over-erasure (Over-Erase).When this over-erasure phenomenon was too serious, the raceway groove that can make the floating grid below promptly presented the state that continues conducting, and causes the erroneous judgement of information when the control grid does not apply operating voltage.So in order to solve the problem of element over-erasure, many flash memories can adopt the design of separated grid (SplitGate).Its architectural feature also has the selection grid that is positioned at above control grid and floating grid sidewall, the substrate (or be called wipe grid) except control grid and floating grid.Wherein, this selects to be separated by with dielectric layer between another layer grid between grid and control grid, floating grid and the substrate.So when excessively wiping phenomenon when too serious, that is floating grid below raceway groove selects the raceway groove of grid below still can keep closed condition when the control grid does not apply the state that promptly presents conducting under the operating voltage state.That is select closing of grid, and can make drain region and source region present non-conduction state, so can prevent the erroneous judgement of information.
Yet, have bigger memory cell size owing to separated grid structure needs bigger separate gate zone, thus its memory cell size to have stacked gate memory cell size big, and produce the so-called problem that can't increase the element integrated level.
In addition and since the element function of flash memory and floating grid with control grid coupling efficiency between the grid (Gate Couple Ratio, GCR) relevant, and this grid coupling efficiency is again with to control area folded between grid and the floating grid relevant.Therefore, area folded between control grid and floating grid is bigger, and its grid coupling efficiency is higher, and element function is also better certainly.Yet,, increase between control grid and the floating grid folded area and can say so and more and more be not easy along with the raising of element integrated level.
Please refer to Fig. 1, is U.S. Pat 6,130 shown in the figure, 453 disclosed flash memory unit structures.As shown in the figure, in order to improve the integrated level of element, this memory cell is formed in the groove of silicon substrate 20.This memory cell is by two rectilinear floating grid 31a, 31b, bit line 32, clearance wall 25, drain region 27, source region 28, silica cover layer 24 and 33 formation of control grid (word line).
Then please refer to Fig. 2 A to Fig. 2 D, is U.S. Pat 6,130 shown in the figure, the manufacturing process of 453 disclosed flash memory cells.At first please refer to Fig. 2 A, substrate 20 is provided, and be formed with the thick grid oxic horizon 21 and silicon nitride dielectric layer 23 of patterning on this substrate 20, to expose the groove 40 that is arranged in substrate 20.Form the thin grid oxic horizon 22 of one deck in groove 40 surfaces afterwards.Then, in groove 40, insert polysilicon layer 31 again.
Then, please refer to Fig. 2 B, in the substrate 20 of predetermined formation grid structure (being groove 40) both sides, form source region 28.Subsequently, carry out reactive ion etching (RIE), forming floating grid 31a, 31b in groove 40 sidewalls, and form groove 42.
Afterwards, please refer to Fig. 2 C, deposited silicon nitride layer 25.Then, please refer to Fig. 2 D, with after forming silicon nitride gap wall 25a, in groove 42 substrate of bottom portion 20, form drain region 27 in oxidation and etches both silicon nitride layer 25.Subsequently, in groove 42, insert polysilicon layer, to form bit line 32.
Wherein, for forming the clearance wall 25a of 32 of floating grid 31a, 31b and bit lines, according to U.S. Pat 6,130,453 disclosed contents, after floating grid 31a, 31b form, before bit line 32 forms, must deposit one dielectric layer earlier, it for example is silicon nitride layer 25, carry out oxidation technology afterwards again, and utilize reactive ion etching to remove the dielectric layer of bottom 20, to expose substrate of bottom portion 20.
Yet, in removing the process of bottom dielectric layer, also can remove the dielectric layer of partial sidewall, and then the dielectric layer of oppose side wall causes damage, influence the performance of memory cell.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of manufacture method of flash memory cell,,, and influence the problem of the performance of memory cell because of dielectric layer is subjected to damage to avoid in technology.
The present invention proposes a kind of manufacture method of flash memory cell, and the method at first provides substrate.Then, on substrate, form the mask layer of patterning.Subsequently, be mask with the mask layer of patterning, etch substrate is to form groove in this substrate.Afterwards, on substrate, form first dielectric layer.Then, respectively form first grid and second grid, this first grid and second grid be separated by a distance and first dielectric layer of exposed portion channel bottom in the groove two side.Then, in the substrate of channel bottom, form first source/drain regions.Subsequently, on substrate, form second dielectric layer.Afterwards, on second dielectric layer, form passivation layer.Wherein, the material of passivation layer for example is semi-conducting material or conductor material.Then, remove passivation layer, second dielectric layer and first dielectric layer of part, to expose the substrate surface of channel bottom.Then, on substrate, form the 3rd grid that fills up groove.Subsequently, remove mask layer.Afterwards, on substrate, form the 3rd dielectric layer.Then, the sidewall in first grid and second grid forms the 4th grid and the 5th grid respectively.Then, in the substrate of the 4th grid and the 5th grid side, form second source/drain regions.
Because the present invention after forming second dielectric layer, forms one deck undoped polycrystalline silicon passivation layer and covers this second dielectric layer.Therefore, removing step (etch process) when follow-up, so that the substrate of channel bottom is when exposing, this passivation layer can be protected second dielectric layer, is subjected to damage (Damage) to avoid second dielectric layer in technology.So, can keep characteristic so that flash memory has preferred information.
The present invention proposes the manufacture method of another kind of flash memory cell, and the method at first provides substrate, has been formed with the lining and the mask layer of opening on this substrate, and is arranged in this opening and is formed at the groove of substrate.Afterwards, form tunnel oxide in flute surfaces.Then, in groove, insert conductor layer after, carry out the etch-back step so that the top of this conductor layer is higher than the lining surface, and be lower than the mask layer surface.Then, form a pair of clearance wall, and cover the conductor layer of part in the sidewall of groove.Subsequently, be etching mask with this to clearance wall and mask layer, remove the conductor layer of part, form first floating grid and second floating grid with sidewall in groove.Afterwards, in the substrate of channel bottom, form first source/drain regions.Then, form dielectric layer between the first grid in substrate and flute surfaces.Then, on dielectric layer between the first grid, form passivation layer.Wherein, the material of passivation layer for example is semi-conducting material or conductor material.Subsequently, remove dielectric layer and tunnel oxide between part passivation layer, the first grid, to expose the substrate surface of channel bottom.Afterwards, on substrate, form the control grid that fills up groove, and the top of this control grid is higher than the top of first floating grid and second floating grid.Then, remove lining and mask layer.Then, in forming dielectric layer between second grid on the substrate.Subsequently, forming first in this sidewall to clearance wall, first floating grid and second floating grid selects grid and second to select grid.Afterwards, select grid and second to select to form second source/drain regions in the substrate of grid side in first.
Because the present invention behind dielectric layer between the formation first grid, forms one deck undoped polycrystalline silicon passivation layer and covers dielectric layer between this first grid.Therefore, removing step (etch process) when follow-up, so that the substrate of channel bottom is when exposing, this passivation layer can be protected dielectric layer between the first grid, and dielectric layer is subjected to damage between the first grid in technology to avoid.So, can keep characteristic so that flash memory has preferred information.
In addition, because first floating grid of the present invention (or second floating grid) is formed in the groove of substrate with the control grid, so its memory cell size can dwindle, and can increase the integrated level of element.And, first floating grid (or second floating grid) and control between the grid folded area and gash depth relevant, therefore can increase folded each other area by the darker groove of the formation degree of depth in technology.So grid coupling efficiency can improve by this, and then improve element operation speed and element function.In addition, its channel region length of memory cell of the present invention is also relevant with gash depth, therefore also can avoid the problem of abnormal electrical perforation (Punch Through) between first source/drain regions and second source/drain regions by in technology, forming the darker groove of the degree of depth.
In addition, utilize manufacture method of the present invention can finish the making of two memory cell of shared same control grid simultaneously.That is first floating grid, first selects grid and control grid to constitute a memory cell, and second floating grid, second selects grid and control grid to constitute another memory cell.So the element integrated level can improve by technology of the present invention, and the technology cost also can reduce.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 is the generalized section of known a kind of flash memory cell;
Fig. 2 A to Fig. 2 D is the generalized section of the manufacturing process of known a kind of flash memory cell;
Fig. 3 A to Fig. 3 J is the generalized section of the manufacturing process of a kind of flash memory cell according to a preferred embodiment of the invention;
Fig. 4 A to Fig. 4 G is the generalized section of the manufacturing process of a kind of flash memory cell according to another preferred embodiment of the invention.
Description of reference numerals
20,300,400: substrate
21,22: grid oxic horizon
23: silicon nitride dielectric layer
24,424: cover layer
25: silicon nitride layer
25a, 332,412,432: clearance wall
27: the drain region
28: the source region
31: polysilicon layer
31a, 31b, 314a, 314b, 414a, 414b: floating grid
32: bit line
33,322,422: the control grid
40,42,306,307,406: groove
301: dielectric layer
304,404: mask layer
308,408: tunnel oxide
310,310a, 330,410,410a, 430: conductor layer
316,336,416,436: source/drain regions
318,318a, 325,418,418a, 425: dielectric layer between grid
320,320a, 420,420a: passivation layer
326,426: doped polysilicon layer
334a, 334b, 434a, 434b: select grid
402: lining
428: metal silicide layer
Embodiment
Please refer to Fig. 3 A to Fig. 3 J, is the manufacture method flow chart of the flash memory cell of a preferred embodiment of the present invention shown in the figure.
At first please refer to Fig. 3 A, substrate 300 is provided, this substrate 300 has formed monobasic spare isolation structure at least, and this component isolation structure is the strip layout, and defines active area.Wherein, the formation method of component isolation structure for example be regional oxidizing process (Local Oxidation, LOCOS) or the shallow trench isolation method (Shallow Trench Iso1ation, STI).
Then, go up in substrate 300 surface and to form the thicker dielectric layers 301 of thickness, the material of this dielectric layer 301 for example is a silica, and its formation method for example be chemical vapour deposition technique (Chemicai VaporDeposition, CVD).In addition, in another preferred embodiment, also can go up the lining (not shown) that forms thinner thickness, and its formation method for example is a thermal oxidation method in substrate 300 surfaces.Then, form the mask layer 304 of patterning on dielectric layer 301, the material of the mask layer 304 of this patterning for example is a silicon nitride, and its formation method for example is to utilize chemical vapour deposition technique deposition one deck layer of mask material earlier, carry out the photoengraving carving technology afterwards again, and form.Subsequently, be mask with the mask layer 304 of patterning, etch substrate 300 is to form groove 306 in substrate 300.
Afterwards, form first dielectric layer on substrate 300, it for example is to form tunnel oxide 308 in groove 306 surfaces.Wherein, the material of tunnel oxide 308 for example is a silica, and its formation method for example is a thermal oxidation method.Then, in groove 306, insert conductor layer 310.Wherein, the material of conductor layer 310 for example is a doped polycrystalline silicon, and its formation method is for example utilized chemical vapour deposition technique to form to carry out the ion implantation step behind one deck undoped polycrystalline silicon layer and form.
Then, please refer to Fig. 3 B, remove mask layer 304 lip-deep conductor layers 310, to form conductor layer 310a.Its removing method comprises the etch-back step, and it for example is to finish in the mode of cmp.Then, carry out photoetching etching step (Patternized technique), in conductor layer 310a, form groove 307, to form two floating grid 314a and 314b, shown in Fig. 3 C.Carry out the ion implantation step afterwards, in the substrate of bottom portion 300 of groove 307, form first source/drain regions 316, shown in Fig. 3 D.
Then, please refer to Fig. 3 E, form second dielectric layer on substrate 300, it for example is a dielectric layer 318 between grid.Wherein, the material of dielectric layer 318 for example is a silicon oxide/silicon nitride/silicon oxide between grid.
Subsequently, on dielectric layer between grid 318, form passivation layer 320.Wherein, the material of passivation layer 320 comprises semi-conducting material or conductor material, and it for example is a undoped polycrystalline silicon, and its formation method for example is a chemical vapour deposition technique, and formed in addition thickness for example is to be about 100 dusts.
Then, please refer to Fig. 3 F, remove dielectric layer 318 and passivation layer 320 between the tunnel oxide 308, grid of part, exposing groove 307 substrate of bottom portion 300 surfaces, and form dielectric layer 318a and passivation layer 320a between grid.Wherein, the method for removal comprises that anisotropic etching process (for example: dry etch process).What deserves to be mentioned is,, therefore remove in step (etch process), can avoid that dielectric layer 318 suffers the damage of etching process between grid, and can keep its performance originally at this owing on dielectric layer between grid 318, be coated with passivation layer 320.
Then, on substrate 300, form the control grid 322 that fills up groove 307, shown in Fig. 3 G.Wherein, the material of control grid 322 for example is a doped polycrystalline silicon.
Afterwards, please refer to Fig. 3 H, remove mask layer 304.What deserves to be mentioned is, if previous substrate 300 tops formation lining in Fig. 3 A is then removed mask layer 304 and this lining in the lump in this step.Then, form the 3rd dielectric layer of the integral surface that covers this structure, it for example is a dielectric layer 325 between grid.Wherein, the material of dielectric layer 325 for example is a silica between grid.
Then, on dielectric layer between grid 325, form conductor layer 330.In the present embodiment, conductor layer 330 is made of doped polysilicon layer 326.And in another preferred embodiment, conductor layer 330 is made of doped polysilicon layer and metal silicide layer.Subsequently, please refer to Fig. 3 I, in the sidewall formation clearance wall 332 of floating grid 314a and floating grid 314b.
Afterwards, please refer to Fig. 3 J, is self-aligned mask with clearance wall 332, removes the conductor layer 330 of part, forms with the sidewall in floating grid 314a and floating grid 314b and selects grid 334a and select grid 334b.Wherein, the removal method of conductor layer 330 for example is an anisotropic etching process.
Then, in the substrate 300 of selecting grid 334a and selection grid 334b side, form second source/drain regions 336, and finish the making of two memory cell of shared same control grid 322.Wherein, the formation method of second source/drain regions 336 for example is an ion implantation technology.
In the above embodiment of the present invention, owing to behind dielectric layer 318 between the formation grid, form one deck undoped polycrystalline silicon passivation layer 320 and cover dielectric layer 318 between these grid.Therefore, removing step (etch process) when follow-up so that groove 307 substrate of bottom portion 300 are when exposing, this passivation layer 320 can grill-protected between dielectric layer 318, dielectric layer 318 is subjected to damage between these grid in technology to avoid.So, can keep characteristic so that flash memory has preferred information.In addition, for control grid 322, formed undoped polycrystalline silicon passivation layer 320 can be used as the usefulness of dielectric layer between grid 318 and the buffering at control grid 322 the two interface.And this passivation layer 320 uses and control grid 322 identical materials, therefore can make both be merged into same grid, and need not remove separately.
Please refer to Fig. 4 A to Fig. 4 G, is the flow chart of manufacture method of the flash memory cell of another preferred embodiment of the present invention shown in the figure.
At first please refer to Fig. 4 A, substrate 400 is provided, this substrate 400 has formed monobasic spare isolation structure at least, and this component isolation structure is the strip layout, and defines active area.Wherein, the formation method of component isolation structure for example is regional oxidizing process or shallow trench isolation method.
Then, form lining 402 in substrate 400 surfaces, the material of this lining 402 for example is a silica, and its formation method for example is a thermal oxidation method.In addition, in another preferred embodiment, also can go up and form the thicker dielectric layer (not shown) of thickness, and its formation method for example is a chemical vapour deposition technique in substrate 400 surfaces.Then, form mask layer 404 on lining 402, the material of this mask layer 404 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.Subsequently, patterned mask layer 404, lining 402 and substrate 400 are to form groove 406 in substrate 400.
Afterwards, form tunnel oxide 408 in groove 406 surfaces.Wherein, the material of tunnel oxide 408 for example is a silica, and its formation method for example is a thermal oxidation method.Then, in groove 406, insert conductor layer 410.Wherein, the material of conductor layer 410 for example is a doped polycrystalline silicon, and its formation method is for example utilized chemical vapour deposition technique to form to carry out the ion implantation step behind one deck undoped polycrystalline silicon layer and form.
Then, please refer to Fig. 4 B, carry out the etch-back step, the conductor layer 410 of etching part stays the conductor layer 410a in the groove 406, so that the top of conductor layer 410a is higher than lining 402 surfaces, and is lower than mask layer 404 surfaces.Subsequently, form clearance wall 412, and cover the upper surface of the conductor layer 410a of part in the sidewall of groove 406.Wherein, the material of clearance wall 412 for example is the material that has different etching selectivities with conductor layer 410a.The formation method of clearance wall 412 for example is to form one deck insulation material layer (not shown) earlier, utilizes anisotropic etch process to remove the SI semi-insulation material layer then and forms.
Afterwards, please refer to Fig. 4 C, is etching mask with mask layer 404 with clearance wall 412, removes the conductor layer 410a of part once more, forms floating grid 414a and floating grid 414b with the sidewall in groove 406.
Then, in groove 406 substrate of bottom portion 400, form first source/drain regions 416.Wherein, the formation method of first source/drain regions 416 for example is an ion implantation technology.
Then, please refer to Fig. 4 D, go up dielectric layer 418 between the formation grid in substrate 400 and groove 406 surfaces.Wherein, the material of dielectric layer 418 for example is a silicon oxide/silicon nitride/silicon oxide between grid.
Subsequently, on dielectric layer between grid 418, form passivation layer 420.Wherein, the material of passivation layer 420 comprises semi-conducting material or conductor material, and it for example is a undoped polycrystalline silicon, and its formation method for example is a chemical vapour deposition technique, and formed in addition thickness for example is to be about 100 dusts.
Then, please refer to Fig. 4 E, remove dielectric layer 418 and passivation layer 420 between the tunnel oxide 408, grid of part, exposing groove 406 substrate of bottom portion 400 surfaces, and form dielectric layer 418a and passivation layer 420a between grid.Wherein, the method for removal comprises that anisotropic etching process (for example: dry etch process).What deserves to be mentioned is,, therefore remove in step (etch process), can avoid that dielectric layer 418 suffers the damage of etching process between grid, and can keep its performance originally at this owing on dielectric layer between grid 418, be coated with passivation layer 420.
Then, on substrate 400, form the control grid 422 that fills up groove 406, and the top of this control grid 422 is higher than the top of floating grid 414a and floating grid 414b.Wherein, the material of control grid 422 for example is a doped polycrystalline silicon.Subsequently, form cover layer 424, filling up groove 406, and cover control grid 422.
Afterwards, please refer to Fig. 4 F, remove lining 402 and mask layer 404.What deserves to be mentioned is,, then in this step, only need to remove mask layer 404 if form the thicker dielectric layer of thickness on the previous substrate 400 in Fig. 4 A.Then, in forming dielectric layer 425 between the grid that cover substrate 400 and substrate 400 surface textures on the substrate 400.Wherein, the material of dielectric layer 425 for example is a silica between grid.
Then, on dielectric layer between grid 425, form conductor layer 430.In the present embodiment, conductor layer 430 is constituted or is made of doped polysilicon layer 426 and metal silicide layer 428 by doped polysilicon layer 426.Subsequently, the sidewall in clearance wall 412, floating grid 414a and floating grid 414b forms clearance wall 432.
Afterwards, please refer to Fig. 4 G, with clearance wall 432 is self-aligned mask, removes the conductor layer 430 (doped polysilicon layer 426 and metal silicide layer 428) of part, forms with the sidewall in clearance wall 412, floating grid 414a and floating grid 414b and selects grid 434a and select grid 434b.Wherein, the removal method of conductor layer 430 for example is an anisotropic etching process.
Then, in the substrate 400 of selecting grid 434a and selection grid 434b side, form second source/drain regions 436, and finish the making of two memory cell of shared same control grid 422.Wherein, the formation method of second source/drain regions 436 for example is an ion implantation technology.
In addition, in another preferred embodiment, also be included in and select grid 434a and select the sidewall of grid 434b to form another clearance wall (not shown), so that carry out follow-up lightly doped drain (Lightly DopedDrain, abbreviation LDD) technology, or contact hole technology.
In the above embodiment of the present invention, owing to behind dielectric layer 418 between the formation grid, form one deck undoped polycrystalline silicon passivation layer 420 and cover dielectric layer 418 between these grid.Therefore, removing step (etch process) when follow-up, so that groove 406 substrate of bottom portion are when exposing, this passivation layer 420 can be protected dielectric layer 418 between these grid, and dielectric layer 418 is subjected to damage between these grid in technology to avoid.So, can keep characteristic so that flash memory has preferred information.In addition, for control grid 422, formed undoped polycrystalline silicon passivation layer 420 can be used as the usefulness of dielectric layer between grid 418 and the buffering at control grid 422 the two interface.And this passivation layer 420 uses and control grid 422 identical materials, therefore can make both be merged into same grid, and need not remove separately.
In addition, because floating grid of the present invention is formed in the groove of substrate with the control grid, so its memory cell size can dwindle, and can increase the integrated level of element.And, floating grid and control between the grid folded area and gash depth relevant, therefore can increase folded each other area by the darker groove of the formation degree of depth in technology.So grid coupling efficiency can improve by this, and then improve element operation speed and element function.In addition, its channel region length of memory cell of the present invention is also relevant with gash depth, therefore also can avoid the problem of abnormal electrical perforation between first source/drain regions and second source/drain regions by form the darker groove of the degree of depth in technology.
In addition, utilize manufacture method of the present invention can finish the making of two memory cell of shared same control grid simultaneously, shown in Fig. 4 G.That is floating grid 414a, selection grid 434a and control grid 422 formations one memory cell, and floating grid 414b, selection grid 434b and control grid 422 constitute another memory cell.So the element integrated level can improve by technology of the present invention, and the technology cost also can reduce.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be with being as the criterion that appending claims was defined.
Claims (23)
1. the manufacture method of a flash memory cell comprises:
One substrate is provided;
On this substrate, form a mask layer of patterning;
This mask layer with patterning is a mask, and this substrate of etching is to form a groove in this substrate;
On this substrate, form one first dielectric layer;
Respectively form a first grid and a second grid in the two side of this groove, this first grid and this second grid be separated by a distance and this first dielectric layer of this channel bottom of exposed portion;
In this substrate of this channel bottom, form one first source/drain regions;
On this substrate, form one second dielectric layer;
On this second dielectric layer, form a passivation layer;
Remove this passivation layer of part, this second dielectric layer and this first dielectric layer, to expose this substrate surface of this channel bottom;
On this substrate, form one the 3rd grid that fills up this groove;
Remove this mask layer;
On this substrate, form one the 3rd dielectric layer;
Sidewall in this first grid and this second grid forms one the 4th grid and one the 5th grid respectively; And
In this substrate of the 4th grid and the 5th grid side, form second source/drain regions.
2. the manufacture method of flash memory cell as claimed in claim 1, wherein the material of this passivation layer be semi-conducting material and conductor material one of them.
3. the manufacture method of flash memory cell as claimed in claim 1, wherein the material of this passivation layer is a undoped polycrystalline silicon.
4. the manufacture method of flash memory cell as claimed in claim 3, wherein the formation method of this passivation layer is a chemical vapour deposition technique.
5. the manufacture method of flash memory cell as claimed in claim 3, wherein the thickness of this passivation layer is 100 dusts.
6. as the manufacture method of the described flash memory cell of arbitrary claim in the claim 1 to 3, wherein the material of this first grid, this second grid, the 3rd grid, the 4th grid and the 5th grid is a doped polycrystalline silicon.
7. the manufacture method of flash memory cell as claimed in claim 1, wherein this first grid and this second grid are floating grid, and the 3rd grid is the control grid, and the 4th grid and the 5th grid are for selecting grid.
8. the manufacture method of flash memory cell as claimed in claim 1, wherein the 4th grid and the 5th grid are made of a doped polysilicon layer and a metal silicide layer.
9. the manufacture method of flash memory cell as claimed in claim 1, wherein this first dielectric layer is a tunnel oxide, and this second dielectric layer and the 3rd dielectric layer are dielectric layer between grid.
10. the manufacture method of flash memory cell as claimed in claim 1 wherein comprises in the method that the sidewall of this groove forms this first grid and this second grid:
In this groove, insert a conductor layer;
Carry out an etch-back step, so that the top of this conductor layer is lower than this mask layer surface;
Sidewall in this groove forms a clearance wall, and covers this conductor layer of part; And
With this clearance wall and this mask layer is etching mask, removes this conductor layer of part, and forms this first grid and this second grid in the sidewall of this groove.
11. the manufacture method of flash memory cell as claimed in claim 1 wherein comprises in the method that the sidewall of this groove forms this first grid and this second grid:
In this groove, insert a conductor layer;
Remove lip-deep this conductor layer of this mask layer; And
This conductor layer of patterning forms this first grid and this second grid with the sidewall in this groove.
12. the manufacture method of flash memory cell as claimed in claim 1 wherein before the step of this mask layer of formation patterning, also is included in and forms a lining on this substrate on this substrate, and in the step of removing this mask layer, also comprises and remove this lining.
13. the manufacture method of flash memory cell as claimed in claim 12, wherein the material of this lining is a silica, and the material of this mask layer is a silicon nitride.
14. the manufacture method of flash memory cell as claimed in claim 1 wherein before the step of this mask layer of formation patterning, also is included in and forms one the 4th dielectric layer on this substrate on this substrate.
15. the manufacture method of a flash memory cell comprises:
One substrate is provided, has been formed with a lining and a mask layer of an opening on this substrate, and be arranged in this opening and be formed at a groove of this substrate;
Form a tunnel oxide in this flute surfaces;
In this groove, insert a conductor layer;
Carry out an etch-back step,, and be lower than this mask layer surface so that the top of this conductor layer is higher than this lining surface;
Sidewall in this groove forms a pair of clearance wall, and covers this conductor layer of part;
Is etching mask with this to clearance wall and this mask layer, removes this conductor layer of part, forms one first floating grid and one second floating grid with the sidewall in this groove;
In this substrate of this channel bottom, form one first source/drain regions;
In forming dielectric layer between a first grid on this substrate and this flute surfaces;
On dielectric layer between this first grid, form a passivation layer;
Remove dielectric layer and this tunnel oxide between this passivation layer of part, this first grid, to expose this substrate surface of this channel bottom;
Form a control grid that fills up this groove on this substrate, the top of this control grid is higher than the top of this first floating grid and this second floating grid;
Remove this lining and this mask layer;
In forming dielectric layer between one second grid on this substrate;
Forming one first in this sidewall to clearance wall, this first floating grid and this second floating grid selects grid and one second to select grid; And
In this substrate of this first selection grid and this second selection grid side, form one second source/drain regions.
16. the manufacture method of flash memory cell as claimed in claim 15, wherein the material of this passivation layer be semi-conducting material and conductor material one of them.
17. the manufacture method of flash memory cell as claimed in claim 15, wherein the material of this passivation layer is a undoped polycrystalline silicon.
18. the manufacture method of flash memory cell as claimed in claim 17, wherein the formation method of this passivation layer is a chemical vapour deposition technique.
19. the manufacture method of flash memory cell as claimed in claim 17, wherein the material of this conductor layer and this control grid is a doped polycrystalline silicon.
20. the manufacture method of flash memory cell as claimed in claim 15, wherein the material of dielectric layer is a silicon oxide/silicon nitride/silicon oxide between this first grid.
21. the manufacture method of flash memory cell as claimed in claim 15, wherein the material of dielectric layer is a silica between these second grid.
22. the manufacture method of flash memory cell as claimed in claim 15, wherein this first selection grid and this second selection grid are made of a doped polysilicon layer and a metal silicide layer.
23. the manufacture method of flash memory cell as claimed in claim 15, wherein the material of this lining is a silica, and the material of this mask layer is a silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100312298A CN1307710C (en) | 2004-03-26 | 2004-03-26 | Method for producing flash memory storing unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100312298A CN1307710C (en) | 2004-03-26 | 2004-03-26 | Method for producing flash memory storing unit |
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| CN1674255A CN1674255A (en) | 2005-09-28 |
| CN1307710C true CN1307710C (en) | 2007-03-28 |
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| CNB2004100312298A Expired - Fee Related CN1307710C (en) | 2004-03-26 | 2004-03-26 | Method for producing flash memory storing unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100781874B1 (en) | 2006-12-26 | 2007-12-05 | 주식회사 하이닉스반도체 | Method for manufacturing of semiconductor device |
| CN114121971A (en) * | 2021-11-26 | 2022-03-01 | 上海华虹宏力半导体制造有限公司 | Flash memory device and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183648A (en) * | 1996-10-22 | 1998-06-03 | 现代电子产业株式会社 | Semi-conductor memory device and manufacturing method thereof |
| CN1184337A (en) * | 1996-11-29 | 1998-06-10 | 三菱电机株式会社 | Semiconductor memory device and fabrication method thereof |
| US6130453A (en) * | 1999-01-04 | 2000-10-10 | International Business Machines Corporation | Flash memory structure with floating gate in vertical trench |
| CN1453878A (en) * | 2002-04-05 | 2003-11-05 | 硅存储技术公司 | Method for forming semiconductor memory array and memory array produced thereby |
| CN1464562A (en) * | 2002-06-25 | 2003-12-31 | 中仪科技股份有限公司 | High density flash memory |
-
2004
- 2004-03-26 CN CNB2004100312298A patent/CN1307710C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183648A (en) * | 1996-10-22 | 1998-06-03 | 现代电子产业株式会社 | Semi-conductor memory device and manufacturing method thereof |
| CN1184337A (en) * | 1996-11-29 | 1998-06-10 | 三菱电机株式会社 | Semiconductor memory device and fabrication method thereof |
| US6130453A (en) * | 1999-01-04 | 2000-10-10 | International Business Machines Corporation | Flash memory structure with floating gate in vertical trench |
| CN1453878A (en) * | 2002-04-05 | 2003-11-05 | 硅存储技术公司 | Method for forming semiconductor memory array and memory array produced thereby |
| CN1464562A (en) * | 2002-06-25 | 2003-12-31 | 中仪科技股份有限公司 | High density flash memory |
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