CN1234212C - Primary synchronous detection system for honeycomb searching of division code multiple task assess system - Google Patents
Primary synchronous detection system for honeycomb searching of division code multiple task assess system Download PDFInfo
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- CN1234212C CN1234212C CNB021202613A CN02120261A CN1234212C CN 1234212 C CN1234212 C CN 1234212C CN B021202613 A CNB021202613 A CN B021202613A CN 02120261 A CN02120261 A CN 02120261A CN 1234212 C CN1234212 C CN 1234212C
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Abstract
The present invention discloses a primary synchronization detection device which is used for the primary synchronous code detection of the honeycomb searching of a CDMA system. The primary synchronization detection device comprises a compensation unit, a first exchange interface, a plurality of minor detection units, a secondary exchange interface and a selecting unit, wherein the compensation unit is used for the phase offset compensation and the sampling frequency offset compensation of an entering signal. The first exchange interface which has a plurality of exchange ports is connected to the compensation unit and is used for outputting the entering signal to a plurality of minor detection units. A plurality of minor detection units are connected to the exchange interface and is used for detecting a primary synchronous code of the entering signal. The secondary exchange interface which has a plurality of exchange ports is connected to a plurality of minor detection units and is used for outputting the entering signal. The selecting unit is connected to the secondary exchange interface and is used for selecting a plurality of possible time slot boundaries as a plurality of candidates from the output of a plurality of minor detection units. The present invention can effectively reduced the influence of a sampling frequency offset effect in a system, and the complexity and the power consumption of the primary synchronization detection device are not increased.
Description
Invention field
The present invention is relevant for a kind of code division multiple access (code division multiple access that is used for, CDMA) the elementary sync detection device of the Cell searching of system, more be particularly to a kind of Wideband-CDMA (wideband code division multiple access that is used for, W-CDMA) the elementary sync detection device of the Cell searching of system, this detector adopt full compensation framework (fully-compensated) or part to compensate framework (partial-compensated) can lower the harmful effect of frequency shift (FS) effect to Cell searching effectively.
Background technology
Use a direct sequence type spreading codes to divide the CDMA cellular systems (cellularsystems) of multiple access (direct sequence spread spectrumcode division multiple access) technology to increase channel capacity significantly.The attention that suction phase is worked as in nearest mobile communcations system research of this system.Generally speaking, because utilization again (frequency reuse) character of frequency, the bandwidth efficiency of code division multiple access system (bandwidth efficiency) is more superior compared with other multitask access system (accessing and time division multiple access as frequency division multi-task).In addition, cellular plans (cellplanning) is quite simple at code division multiple access system.Therefore, CDMA cellular system will be following main flow.Particularly (Third generation partnershipproject, 3GPP) Wideband-CDMA/Frequency Division Duplexing (FDD) (W-CDMA/FDD) system has been used in one of standard of a kind of IMT-2000 of being used for third generation system to third generation cooperative programme.
In the cellular system of a code division multiple access, (user equipment, UE) method as the search optimum cellular is called as " Cell searching " (cell search) by user's set.Cell searching is in order to reduce this user's set start time of delay (switched-on delay) (initial ranging), to increase standby (standby time) (idle state search) and (operate condition is searched for switching (handover), active mode search) keeps the good communication link quality, so Cell searching is extremely important fast.
Now please refer to Fig. 1, this figure will help to understand the frame structure (frame structure) of third generation cooperative programme (3GPP) Wideband-CDMA/frequency division multi-task system.At first, in the Wideband-CDMA/frequency division multi-task system of third generation cooperative programme (3GPP), generally speaking Cell searching is finished by three phases (three stages), this three stage comprises two specially designed synchronizing channel (synchronization channel, SCH) and Common Pilot Channel (common pilot channel, CPICH).In the phase I 110, (primary synchronization channel, PSCH) 111 are used for time slot (slot) synchronously to elementary synchronizing channel.This elementary synchronizing channel 111 includes elementary synchronous code, and (primary synchronization code PSC) is defined as ac
p, the diversity that wherein " a " (=± 1) depends on the base station transmits (diversitytransmission) and whether exists and decide.In second stage 120, (secondary synchronization channel, SSCH) 121 are used for frame/code group (frame/codegroup) identification to the secondary synchronization channel.This secondary synchronization channel 121 includes the secondary synchronization sign indicating number, and (secondarysynchronization code SSCs) is defined as ac
s, wherein coefficient a is equal to the coefficient of elementary synchronizing channel.In the phase III 130, this Common Pilot Channel 131 is used for the decision of descending scrambler time slot scrambler (downlink scrambling code slot).As shown in the figure, in 10 milliseconds of (ms) frames (radio frame), comprise 15 time slots, and because in this system, used the speed of per second 3.84 1,000,000 chips (Mchips/sec).Therefore, comprise 38400 chips in each frame, just comprise 2560 chips in each time slot.In addition, this elementary synchronizing channel and this secondary synchronization channel length comprise 256 chips and only transmit at the beginning of this boundary of time slot.
In recent years, it is revealed to be used for fast cell search (cell search) method of the cellular system of code division multiple access.See the United States Patent (USP) number the 6th of awarding to people such as Nystrom, 185, No. 244, its title is " Cell searching is in CDMA communication system " (Cell searching in a CDMAcommunications system), be disclosed in Cell searching during CDMA communication system, more efficient code scheme needs a long code and frame time-histories.Sign indicating number set with MQ row (MQ-ary) Baud Length, wherein this code element comprises the set from a Q short code, and this yard sets definition is to specific characteristic.This initial characteristic that is satisfied does not have the cyclicity drift for this code element thereby produces an effective code element; Other the characteristic that is satisfied is between long code signal and effective code element, has mapping (mapping) one to one, and this encoder can find to appear at disturb with the code element of the moving at random of noise (thereby finding frame time-histories) and this transmission (just, be relevant to long code and represent signal (long code indication message), have the accurate and rational complexity on some degree.
Other small region search method still has:
See the United States Patent (USP) number the 6th of awarding to people such as Kim, 289, No. 007, its title is " method at the acquisition search cellular basestation of Asynchronous Code Division Multiple Access mobile communcations system " (Method for Acquiring A Cell Site Station in Asynchronous CDMACellular Communication Systems); And
See the United States Patent (USP) number the 6th of awarding to people such as Shou, 038, No. 250, its title is " receiver of the code division multiple access trunk desk asynchronous cellular systems of initialization synchronized method and direct sequence type " (Initial Synchronization Method And Receiver for DS-CDMA InterBase Station Asynchronous Cellular System).
Yet being generally used in the prior art of Cell searching of third generation cooperative programme Wideband-CDMA/frequency division multi-task has two basic assumptions.The first, the sampling point of exporting at chip-matched filter is an optimum, or is referred to as desirable sampling (ideal sampling).That is to say that sampling is at the peak value of signal.Yet in fact, the sampling of exporting at chip-matched filter is not perfect (being imperfect sampling (non-ideal sampling)).The second, in the chip time of transmitter receiver is accurately known (promptly being not have sampling frequency deviation (clockoffset)), just, this entering signal carrier frequency is all set the skew that does not have frequency.In fact, frequency shift (FS) (frequency offset) comes from the frequency instability of the crystal oscillator of user's set, and for user's set, this entering signal carrier frequency may have the side-play amount of frequency, therefore causes the uncertain region of carrier frequency.Frequency shift (FS) causes two effects at Base Band, (1) phase deviation (phase rotation) (2) sampling frequency deviation (clock offset).Wherein the part of sampling frequency deviation is not taken into account in the prior art as yet.In the past, can eliminate by the elementary synchronous code matched filter (primary synchronizationcode matched filter) of a non-people having the same aspiration and interest combining structure (non-coherentcombined structure) by the phase deviation effect that frequency shift (FS) caused.This technology is found in Y.P.E.Wang and T.Ottosson, " Initial frequency acquisition in W-CDMA, " IEEE Proc.VTC ' 99, Vol.2, pp.1013-1017, Sept.1999.
Table 1
The chip sampling point drift that in one 30 milliseconds test, is caused in the different frequency drift
| Frequency drift (kHz) | Sampling point drift (Tc) | ||
| | 20ms | 30ms | |
| 0 | 0 | 0 | 0 |
| 6 | 0.1152 | 0.2304 | 0.3456 |
| 8 | 0.1536 | 0.3072 | 0.4608 |
| 12 | 0.2304 | 0.4608 | 0.6912 |
| 24 | 0.4608 | 0.9216 | 1.3824 |
Yet the chip sampling frequency deviation that this frequency shift (FS) causes is present between base station and the user's set, but is that prior art institute does not consider.Now please refer to table 1, this table is presented at sampling point drift (clock drift) and the time relation that is produced under the situation of different frequency skew, for instance, under the appearance of 12kHz frequency shift (FS), sampling point has the skew of 0.69 times of chip time in 30 milliseconds of frames, is equivalent to the sampling frequency deviation of 6ppm.Therefore will cause control information and increase the Cell searching time.Fig. 2 a and Fig. 2 b are not prior art, but the inventor is at the observation figure that considers to export at elementary sign indicating number matched filter under the sampling point drift effect that frequency shift (FS) causes.As scheme to show, owing under the chip sampling frequency deviation effect that frequency shift (FS) caused, disturb the result who increases between signal level reduction and chip.The present inventor once proposed several methods to solve this frequency shift (FS) effect.But along with frequency offset continues to increase, the compensation of frequency shift (FS) can't be avoided.Therefore, just having needs to propose a kind of new cell search apparatus, is used for effectively solving this frequency shift (FS) effect.
Summary of the invention
Main purpose of the present invention provides a kind of elementary sync detection device of Cell searching, be used for code division multiple access system, more be used in particular for broadband CDMA system, can the reduction system in sampling frequency deviation effect to the influence of Cell searching deterioration in characteristics, and finish Cell searching fast.
Secondary objective of the present invention provides a kind of elementary sync detection device of Cell searching, the Cell searching that is used for three phase process of code division multiple access system, sampling frequency deviation effect is to the influence of Cell searching deterioration in characteristics in can the reduction system, and do not increase the complexity and the power consumption of device.
For reaching above-mentioned main purpose, the invention provides a kind of elementary sync detection device, the elementary synchronous code that is applied to the Cell searching of code division multiple access system detects, detection is from an entering signal of base station, this entering signal has a carrier frequency uncertain region because of frequency shift (FS), this elementary sync detection device comprises: a compensating unit (compensation unit) is used for the frequency compensation of this entering signal and the selection mode of the sampling point of this entering signal of decision; One first Fabric Interface is connected in this compensating unit, has a plurality of switching ports, is used for exporting this entering signal to a plurality of secondary detection unit; A plurality of secondary detection unit are connected in this Fabric Interface, are used to detect an elementary synchronous code of this entering signal, and wherein this yard is used to differentiate the boundary of time slot of this entering signal; Wherein the carrier frequency uncertain region with this entering signal is divided into a plurality of zonules (cell), one subcarrier (sub-carrier) frequency is arranged in each zone, these a plurality of sub-carrier frequencies are as the reference frequency of these a plurality of secondary detection unit, and cutting frequency uncertain region is called one fen cabinet process for these a plurality of zonules (cell); One second Fabric Interface is connected in this a plurality of secondary detection unit, has a plurality of switching ports, is used for this entering signal output; And a selected cell, be connected in this second Fabric Interface, be used for picking out a plurality of (N1) individual possible boundary of time slot as a plurality of (N1) candidate in the output of these a plurality of secondary detection unit.
According to a feature of the present invention, wherein this compensating unit comprises: a frequency compensation unit is used for phase deviation (the phase rotation compensation) compensation and sampling frequency deviation (clock offset compensation) compensation of this entering signal; And a sampling point disarrangement device, be used to determine the selection mode of the sampling point of this entering signal; Wherein this sampling point disarrangement device is selected a sampling point randomly in the digital form of this entering signal, or this sampling point disarrangement device selects an optimal sampling point in the digital form of this entering signal, and wherein this optimal sampling point has maximum sampling value in the digital form of this entering signal.
For reaching above-mentioned secondary objective, the invention provides a kind of elementary sync detection device, be applied to the elementary synchronous code synchronous detecting of the Cell searching of code division multiple access system, detection is from an entering signal of base station, this entering signal has a carrier frequency uncertain region because of frequency shift (FS), this elementary sync detection device comprises: a frequency compensation unit (frequency compensationunit) is used for the phase compensation of this entering signal; One elementary synchronous code matched filter is used for coupling and detects this elementary synchronous code; Wherein this elementary synchronous code matched filter people having the same aspiration and interest or non-people having the same aspiration and interest, and be divided into a plurality of sections, the output of each section merges with its absolute value; One sampling frequency deviation compensating unit (clock compensated unit) is used for the sampling frequency deviation compensation of this entering signal; One first Fabric Interface is connected in this sampling frequency deviation compensating unit, has a plurality of switching ports, is used for exporting this entering signal to a plurality of cyclic buffers; A plurality of cyclic buffers (circular buffer) are connected in this first Fabric Interface, are used to store the testing result from this elementary synchronous code detector, and continue to judge the preferable boundary of time slot of this entering signal; Wherein the carrier frequency uncertain region with this entering signal is divided into a plurality of zonules (cell), one subcarrier (sub-carrier) frequency is arranged in each zone, these a plurality of sub-carrier frequencies are as the reference frequency of these a plurality of cyclic buffers, and cutting frequency uncertain region is called one fen cabinet process for these a plurality of zonules (cell); One second Fabric Interface is connected in this a plurality of secondary detection unit, has a plurality of switching ports, is used for this entering signal output; One selected cell is connected in this second Fabric Interface, is used for picking out a plurality of (N1) individual possible boundary of time slot as a plurality of (N1) candidate in the output of these a plurality of secondary detection unit.
According to a feature of the present invention, wherein this sampling point disarrangement device is selected a sampling point randomly in the digital form of this entering signal, or this sampling point disarrangement device selects an optimal sampling point in the digital form of this entering signal, and wherein this optimal sampling point has maximum sampling value in the digital form of this entering signal.
The present invention has following advantage:
(1) elementary sync detection device of the present invention can the reduction system in sampling frequency deviation effect to the influence of Cell searching deterioration in characteristics.
(2) elementary sync detection device of the present invention can be made different frequency compensation structures at frequency shift (FS) degree in various degree, promptly full collocation structure and part collocation structure.
(3) elementary sync detection device of the present invention can cooperate different small region search methods, has elasticity on Design of device.
(4) in practical application, elementary sync detection device of the present invention can realize that particularly the mode with chip realizes with hardware mode, to be embedded on the Cell searching circuit.
Further feature of the present invention and advantage will be from hereinafter detailed description, appended icon and the claim scopes that is defined and apparent.
Description of drawings
Fig. 1 shows that one is used for the frame assumption diagram of the Wideband-CDMA/frequency division multi-task system of third generation cooperative programme (3GPP).
Fig. 2 a and Fig. 2 b show, under the sampling point drift effect that frequency shift (FS) causes, disturb the result who increases between signal level reduction and chip.
Fig. 3 shows that this elementary sync detection device uses full collocation structure (fully compensatedstructure) according to the structure chart of a kind of elementary sync detection device of first embodiment of the invention.
The structure chart of one embodiment of the secondary detection unit of Fig. 4 displayed map 3.
Fig. 5 shows the structure chart according to a kind of elementary sync detection device of second embodiment of the invention, and this elementary sync detection device uses part collocation structure (partially compensatedstructure).
The front-end architecture figure of the elementary sync detection device of Fig. 6 displayed map 3 and Fig. 5.
Fig. 7 a shows the schematic diagram according to a kind of minute cabinet method of the embodiment of the invention.
Fig. 7 b shows the schematic diagram according to a kind of minute cabinet method of the embodiment of the invention.
Fig. 8 is presented at frequency shift (FS) effect f
ΔUnder=the 24kHz, the different performance plots that divide the small region search method under the cabinet number.(geometrical factor (Geometry Factor) G=6dB)
Fig. 9 is presented at frequency shift (FS) effect f
ΔUnder=the 24kHz, the performance plot of the small region search method of more different candidate numbers.
Label declaration:
111 elementary synchronizing channel 121 secondary synchronization channels
131 Common Pilot Channel, 190 signals
300 elementary sync detection device 310 compensating units
320 first Fabric Interfaces 331, more than 332 secondary detection unit
340 second Fabric Interfaces, 350 selected cells
500 elementary sync detection device 510 sampling point disarrangement devices
520 elementary synchronous code matched filter 530 sampling frequency deviation compensating units
540 first Fabric Interfaces 551, more than 552 cyclic buffer
560 second Fabric Interfaces, 570 selected cells
610 analog digital converting unit, 620 chip matched filtering unit
Embodiment
Frequency shift (FS) causes two effects at Base Band, (1) phase deviation (phase rotation) (2) sampling frequency deviation (clock offset).Wherein the part of sampling frequency deviation is not taken into account in the prior art as yet.
Fig. 3 shows that this elementary sync detection device uses full collocation structure (fully compensatedstructure) according to the structure chart of a kind of elementary sync detection device of first embodiment of the invention.This elementary sync detection device 300 has compensated (1) phase deviation (phaserotation) (2) sampling frequency deviation (clock offset) simultaneously, and it comprises a compensating unit 310, one first Fabric Interface 320, a plurality of secondary detection unit 331,332, one second Fabric Interface 340 and a selected cell 350.
Owing to elementary sync detection device 300 of the present invention, be used for the Cell searching of code division multiple access system, the phase I that is used in the Cell searching with three phase process especially handles.And focus on when handling in the phase I can the reduction system in sampling frequency deviation effect to the influence of Cell searching deterioration in characteristics, and finish Cell searching fast.Therefore cooperate Fig. 6 that embodiments of the present invention are described, the front-end architecture figure of the elementary sync detection device of Fig. 6 displayed map 3.The front end of this elementary sync detection device 300 more comprises: an analog digital converting unit 610 and a chip matched filtering unit 620.
Now please refer to Fig. 3 and Fig. 6, illustrate how the first embodiment of the present invention is applied to Cell searching.From an entering signal of base station, through this analog digital converting unit 610, signal can convert digital form to by analog form, that is to say, this analog digital converting unit 610 can be one to have the unit of sampled functions.This chip matched filtering unit 620 is connected in this analog digital converting unit 610, is used to mate this entering signal, and this entering signal is sent into this elementary sync detection device 300.This compensating unit 310 is used for the frequency compensation of this entering signal and the selection mode of the sampling point of this entering signal of decision.Wherein this compensating unit 310 comprises a frequency compensation unit 311, is used for phase deviation (phase rotationcompensation) compensation and sampling frequency deviation (clock offset compensation) compensation of this entering signal; And a sampling point disarrangement device 312, be used to determine the selection mode of the sampling point of this entering signal.For instance, when this entering signal has very big sampling frequency deviation effect because of frequency shift (FS), this frequency compensation unit 311 can decision be divided into a plurality of zonules (cell) with the frequency uncertain region with this entering signal, and a subcarrier (sub-carrier) frequency is arranged in each zone; Reference frequency when wherein this sub-carrier frequencies is handled this entering signal as these a plurality of secondary detection unit 331,332.The frequency uncertain region that the number of these a plurality of secondary detection unit 331,332 relies on this entering signal is divided into the number of a plurality of zonules (cell), or says so, one fen cabinet number.Now please cooperate Fig. 7, this figure will illustrate the advantage of a plurality of secondary detection unit is selected and used to the number of a plurality of secondary detection unit 331,332 how.
Fig. 7 a shows the schematic diagram of a kind of minute cabinet method.This entering signal carrier frequency is f
0, being subject to the accuracy of the crystal oscillator of client, the frequency of the carrier frequency of this entering signal and client crystal oscillator has an error, and its error range is distributed in f
HAnd f
LBetween; Meaning promptly is that benchmark is seen it with the client, and the carrier frequency of entering signal is between f
HAnd f
LBetween.This interval is referred to herein as the carrier wave uncertain region.According to the branch cabinet method that the present inventor proposed, this carrier frequency uncertain region is divided into a plurality of zonules, a sub-carrier frequencies is arranged in each zone; Reference frequency when wherein this sub-carrier frequencies is handled this entering signal as these a plurality of secondary detection unit 331,332, and these a plurality of zonules (cell) are called cabinet (bin).This carrier frequency uncertain region of cutting is come with the identical distance or the interval of not waiting in these a plurality of zonules (cell).Shown in Fig. 7 a, this carrier frequency uncertain region of cutting is come with the interval of not waiting in these a plurality of zonules, and wherein this sub-carrier frequencies is positioned at the centre of these a plurality of zonules.Yet this carrier frequency uncertain region of five equilibrium is come with identical distance in preferable these a plurality of zonules (cell) of working as.With reference to Fig. 7 b, this figure shows the schematic diagram of another minute cabinet method.This carrier frequency uncertain region of cutting is come with the interval that equates in these a plurality of zonules, and wherein this sub-carrier frequencies is positioned at the centre of these a plurality of zonules.If this carrier frequency uncertain region is divided into N cabinet, then this n sub-carrier frequencies is expressed as f
n, wherein n is more than or equal to 1 and smaller or equal to N, and n sub-carrier frequencies f
nAs shown in Fig. 7 b.This carrier frequency uncertain region of benefit of this kind branch cabinet method is by cutting, therefore these a plurality of sub-carrier frequencies can be more near the carrier frequency of this entering signal, therefore reduce the carrier frequency and the side-play amount that is used as the reference frequency of these a plurality of secondary detection unit 331,332 of this entering signal, therefore can effectively reduce the undesirable feature of Cell searching under the effect of frequency shift (FS).Cabinet process phase I of being used in this Cell searching especially this minute handles.Basically, this minute cabinet number carrier frequency that the more more can reduce this entering signal and the side-play amount that is used as the reference frequency of these a plurality of secondary detection unit 331,332, yet branch cabinet number the more also represent need be the more secondary detection unit, so can cause the cost of device.Therefore in the present invention, more adopt this sampling point disarrangement device 312, be used to determine the selection mode of the sampling point of this entering signal.Wherein this sampling point disarrangement device 312 is selected a sampling point randomly in the digital form of this entering signal.Perhaps this sampling point disarrangement device 312 is selected an optimal sampling point in the digital form of this entering signal, and wherein this optimal sampling point has maximum sampling value in the digital form of this entering signal.The selection mode of the sampling point of this sampling point disarrangement device 312 this entering signal that determines also can effectively solve the harmful effect of the sampling frequency deviation effect of this entering signal to Cell searching.Because this frequency compensation unit 311 cooperates with this sampling point disarrangement device 312, the minimizing that the number of branch cabinet can be a large amount of, and do not need a large amount of secondary detection unit.This first Fabric Interface 320 is connected in this compensating unit, has a plurality of switching ports, is used for exporting this entering signal to a plurality of secondary detection unit behind minute cabinet.These a plurality of secondary detection unit 331,332 are connected in this first Fabric Interface, are used to detect an elementary synchronous code of this entering signal, and wherein this yard is used to differentiate the boundary of time slot of this entering signal.Now cooperate Fig. 4, the structure chart of an embodiment of the secondary detection unit of Fig. 4 displayed map 3, it comprises an elementary synchronous code matched filter 410 and a cyclic buffer (circular buffer) 420.This elementary synchronous code matched filter 410 is used for coupling and detects this elementary synchronous code.Wherein a plurality of chips that this elementary synchronous code matched filter will this elementary synchronous code are divided into a plurality of sections, and the output of each section merges with its absolute value.This cyclic buffer (circular buffer) 420, be connected in this elementary synchronous code matched filter, be used to store testing result, and the result is added up through path 421 back couplings and with next result, with the boundary of time slot of judging that this entering signal is preferable from this elementary synchronous code detector.This second Fabric Interface 340 is connected in this a plurality of secondary detection unit 331,332, has a plurality of switching ports, is used for this entering signal output.According to this elementary sync detection device 300 of the present invention, it still has this selected cell 350 at last, be connected in this second Fabric Interface 340, be used for picking out a plurality of (N1) individual possible boundary of time slot as a plurality of (N1) candidate, with next stage processing as Cell searching in the output of these a plurality of secondary detection unit 331,332.
Fig. 5 shows the structure chart according to a kind of elementary sync detection device of second embodiment of the invention, and this elementary sync detection device uses part collocation structure (partially compensatedstructure).Be different from elementary sync detection device according to first embodiment of the invention, the elementary sync detection device of this of second embodiment has only compensated sampling frequency deviation (clock offset), and a chip matched filter is transferred in the elimination work of phase deviation (phase rotation).It comprises a sampling point disarrangement device 510, one elementary synchronous code matched filter 520, a sampling frequency deviation compensating unit 530, one first Fabric Interface 540, a plurality of cyclic buffer 551,552, one second Fabric Interfaces 560, a selected cell 570 this elementary sync detection device 500.
Now please refer to Fig. 6 and Fig. 5 and illustrate how the second embodiment of the present invention is applied to Cell searching, Fig. 6 also is the front-end architecture figure of the elementary sync detection device of Fig. 5.From an entering signal of base station, through this analog digital converting unit 610, signal can convert digital form to by analog form, that is to say, this analog digital converting unit 610 can be one to have the unit of sampled functions.This chip matched filtering unit 620 is connected in this analog digital converting unit 610, is used to mate this entering signal, and this entering signal is sent into this elementary sync detection device 500.This sampling point disarrangement device 510 is used to determine the selection mode of the sampling point of this entering signal.Owing to this entering signal digital form this moment, this sampling point disarrangement device 510 is selected a sampling point randomly in the digital form of this entering signal.Perhaps this sampling point disarrangement device 510 is selected an optimal sampling point in the digital form of this entering signal, and wherein this optimal sampling point has maximum sampling value in the digital form of this entering signal.The selection mode of the sampling point of this sampling point disarrangement device 510 this entering signal that determines also can effectively be separated the harmful effect of the sampling frequency deviation effect of low this entering signal to Cell searching.This elementary synchronous code matched filter 520 is used for coupling and detects this elementary synchronous code, and wherein a plurality of chips that this elementary synchronous code matched filter will this elementary synchronous code are divided into a plurality of sections, and the output of each section is with its absolute value merging.This sampling frequency deviation compensating unit 530 is used for the sampling frequency deviation compensation of this entering signal.For instance, when this entering signal has very big sampling frequency deviation effect because of frequency shift (FS), this frequency compensation unit 530 can decision be divided into a plurality of zonules (cell) with the frequency uncertain region with this entering signal, and a subcarrier (sub-carrier) frequency is arranged in each zone; Reference frequency when wherein this sub-carrier frequencies is handled this entering signal as these a plurality of cyclic buffers 551,552.At this moment, these a plurality of cyclic buffers 551,552 are the number that the frequency uncertain region of this entering signal of dependence is divided into a plurality of zonules (cell), as previously mentioned.This first Fabric Interface 540 is connected in this sampling frequency deviation compensating unit, has a plurality of switching ports, is used for exporting this entering signal to a plurality of cyclic buffers.These a plurality of cyclic buffers 551,552, be connected in this first Fabric Interface 540, be used to store testing result, and the result is added up through path 541 back couplings and with next result, and continue to judge the preferable boundary of time slot of this entering signal from this elementary synchronous code detector.This second Fabric Interface 560 is connected in this a plurality of cyclic buffers 551,552, has a plurality of switching ports, is used for this entering signal output.This selected cell 570 is connected in this second Fabric Interface 560, is used for picking out a plurality of (N1) individual possible boundary of time slot as a plurality of (N1) candidate in the output of these a plurality of less important cyclic buffers.With next stage processing as Cell searching.
In practical application, the elementary sync detection device of the first embodiment of the present invention and second embodiment is because therefore the definite functions of each square can cooperate hardware mode to realize with software, particularly the mode with chip realizes, to be embedded on the Cell searching circuit.
Owing to elementary sync detection device of the present invention, be used for the Cell searching of code division multiple access system, the phase I that is used in the Cell searching with three phase process especially handles.And focus on when handling in the phase I can the reduction system in sampling frequency deviation effect to the influence of Cell searching deterioration in characteristics, and finish Cell searching fast.Other condition identical down (second stage as Cell searching is handled the condition of handling with the phase III), further Computer Simulation is used to inquire into the cell search apparatus of embodiments of the invention, promptly full collocation structure down with the part collocation structure under the operating characteristic comparison of checkout gear.
Fig. 8 is presented at frequency shift (FS) effect f
Δ=24kHz reaches different the branch under the cabinet number down, uses the performance plot of the cell search apparatus of full collocation structure and part collocation structure.This characteristic has a plurality of minutes cabinets in this phase I processing employing and handles.As shown in the figure, when several one of minute cabinet, weigh the pointer of Cell searching, i.e. the tangible deterioration of cumulative density function characteristic of search time.When a minute cabinet number increased to 3, the cumulative density function characteristic of search time obviously promoted.When dividing the cabinet number to increase to 4, the not better performance of the cumulative density function characteristic of search time in sight.Therefore it is not The more the better dividing the cabinet number, but patient minimum usefulness when dividing the number of cabinet to be reduced to as far as possible to keep correct Cell searching.And the operating characteristic of the elementary sync detection device of first embodiment is better than the operating characteristic of the elementary sync detection device of second embodiment.
Fig. 9 is presented at frequency shift (FS) effect f
ΔUnder=the 24kHz, the performance plot of the small region search method of more different candidate numbers.When handling in the phase I, adopts in this figure 3 branch cabinets.During this handled phase I, in this elementary synchronous code, the boundary of time slot of selecting a plurality of this sign indicating numbers was as a plurality of candidates, and should a plurality of candidates deliver to this second stage processing.As shown in the figure, 10 candidates are delivered to this second stage and are handled preferable result.And the operating characteristic of the elementary sync detection device of first embodiment also is better than the operating characteristic of the elementary sync detection device of second embodiment.
Shown in former figure, patient minimum usefulness when dividing the number of cabinet to be reduced to as far as possible to keep correct Cell searching.In addition, and the operating characteristic of the elementary sync detection device of first embodiment is better than the operating characteristic of the elementary sync detection device of second embodiment.Yet, therefore elementary sync detection device under the full collocation structure of first embodiment has higher power consumption and computational complexity compared with the elementary sync detection device under the part collocation structure of second embodiment, uses checkout gear under the full collocation structure or the checkout gear under the part collocation structure need do a measurement.
Therefore, be used for this elementary sync detection device of code division multiple access system according to the present invention, the effect that can reduce frequency shift (FS) effectively and caused at this code division multiple access system and reach initial synchronisation fast.
This elementary sync detection device that is used for code division multiple access system according to the present invention, can be under the chip sampling frequency deviation effect that frequency shift (FS) caused effective elevator system usefulness; And, in complexity based on not obvious this hardware of increase under identical minute cabinet number.The method according to this invention and device can be used for mobile device and radio individual digitlization assistant (PDA) system.
Though the present invention is open with aforementioned preferred embodiment; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing various changes and modification, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (20)
1. elementary sync detection device, the elementary synchronous code that is applied to the Cell searching of code division multiple access system detects, detection is from an entering signal of base station, this entering signal has a carrier frequency uncertain region because of frequency shift (FS), error amount between the centre carrier frequency that this frequency shift (FS) is meant the base station and the corresponding centre carrier frequency that produces of client terminal local oscillator, it is characterized in that: this elementary sync detection device comprises:
One compensating unit is used for the frequency compensation of this entering signal and the selection mode of the sampling point of this entering signal of decision;
One first Fabric Interface is connected in this compensating unit, has a plurality of switching ports, to receive the signal of this compensating unit output;
A plurality of secondary detection unit are connected in this first Fabric Interface, are used to detect an elementary synchronous code of the signal of this first Fabric Interface output, and wherein this elementary synchronous code is used to differentiate the boundary of time slot of the signal of this first Fabric Interface output;
Wherein the carrier frequency uncertain region with the signal of this first Fabric Interface output is divided into a plurality of zonules, one sub-carrier frequencies is arranged in each zone, these a plurality of sub-carrier frequencies are as the reference frequency of this a plurality of secondary detection unit, and cutting frequency uncertain region is that the process of these a plurality of zonules is called one fen cabinet process;
One second Fabric Interface is connected in this a plurality of secondary detection unit, has a plurality of switching ports, to receive the signal of these a plurality of secondary detection unit outputs;
One selected cell is connected in this second Fabric Interface, is used for picking out a plurality of possible boundary of time slot as a plurality of candidates in the output of these a plurality of secondary detection unit.
2. elementary sync detection device as claimed in claim 1 is characterized in that: wherein this compensating unit comprises:
One frequency compensation unit is used for the phase deviation compensation and the sampling frequency deviation compensation of this entering signal;
One sampling point disarrangement device is used to determine the selection mode of the sampling point of this entering signal.
3. elementary sync detection device as claimed in claim 1 is characterized in that: wherein this secondary detection unit comprises:
One elementary synchronous code matched filter is used for coupling and detects this elementary synchronous code;
One cyclic buffer is connected in this elementary synchronous code matched filter, is used to store the testing result from this elementary synchronous code matched filter, and continues to judge the preferable boundary of time slot of signal of this first Fabric Interface output.
4. elementary sync detection device as claimed in claim 2 is characterized in that: wherein this elementary sync detection device also comprises:
One analog digital converting unit is used for converting entering signal to digital form by analog form;
One chip matched filtering unit is connected between this analog digital converting unit and this compensating unit, is used to mate the output signal of this analog digital converting unit.
5. elementary sync detection device as claimed in claim 4 is characterized in that: wherein this sampling point disarrangement device is selected a sampling point randomly in the output signal of this chip matched filtering unit.
6. elementary sync detection device as claimed in claim 4, it is characterized in that: wherein this sampling point disarrangement device is selected an optimal sampling point in the output signal of this chip matched filtering unit, and wherein this optimal sampling point has maximum sampling value in the output signal of this chip matched filtering unit.
7. elementary sync detection device as claimed in claim 1, it is characterized in that: wherein the carrier frequency uncertain region of this entering signal refers to, frequency range between the maximum possible frequency of this entering signal and the minimum possibility frequency, wherein this carrier frequency uncertain region is owing to the unstable institute of the frequency of the crystal oscillator of user's set causes.
8. elementary sync detection device as claimed in claim 4 is characterized in that: wherein these a plurality of zonules are with the carrier frequency uncertain region of the signal of this first Fabric Interface output of identical distance five equilibrium.
9. elementary sync detection device as claimed in claim 5 is characterized in that: wherein this sub-carrier frequencies is positioned at the centre of these a plurality of zonules.
10. elementary sync detection device as claimed in claim 1 is characterized in that: wherein the number of these a plurality of secondary detection unit is decided by the number of a plurality of zonules of the carrier frequency uncertain region institute cutting of the signal of this first Fabric Interface output.
11. elementary sync detection device, be applied to the elementary synchronous code synchronous detecting of the Cell searching of code division multiple access system, detection is from an entering signal of base station, this entering signal has a carrier frequency uncertain region because of frequency shift (FS), error amount between the centre carrier frequency that this frequency shift (FS) is meant the base station and the corresponding centre carrier frequency that produces of client terminal local oscillator, it is characterized in that: this elementary sync detection device comprises:
One sampling point disarrangement device is used to determine the selection mode of the sampling point of this entering signal;
One elementary synchronous code matched filter connects this sampling point disarrangement device, is used to mate and detect the elementary synchronous code of this sampling point disarrangement device output signal;
One sampling frequency deviation compensating unit connects this elementary synchronous code matched filter, is used for the sampling frequency deviation compensation of the signal of this elementary synchronous code matched filter output;
One first Fabric Interface is connected in this sampling frequency deviation compensating unit, has a plurality of switching ports, to receive the signal of this sampling frequency deviation compensating unit output;
A plurality of cyclic buffers are connected in this first Fabric Interface, are used to store the testing result from the elementary synchronous code matched filter of this first Fabric Interface output, and continue to judge the preferable boundary of time slot of signal of this first Fabric Interface output;
Wherein the carrier frequency uncertain region of the signal that this first Fabric Interface is exported is divided into a plurality of zonules, one sub-carrier frequencies is arranged in each zone, these a plurality of sub-carrier frequencies are as the reference frequency of this a plurality of cyclic buffers, and cutting frequency uncertain region is that the process of these a plurality of zonules is called one fen cabinet process;
One second Fabric Interface is connected in this a plurality of cyclic buffers, has a plurality of switching ports, to receive the signal of this sampling frequency deviation compensating unit output;
One selected cell is connected in this second Fabric Interface, is used for picking out a plurality of possible boundary of time slot as a plurality of candidates in the output of these a plurality of cyclic buffers.
12. elementary sync detection device as claimed in claim 11 is characterized in that: wherein this elementary sync detection device also comprises:
One analog digital converting unit is used for the analog form of entering signal is converted to digital form;
One chip matched filtering unit is connected between this analog digital converting unit and this sampling point disarrangement device, is used to mate the output signal of this analog digital converting unit.
13. elementary sync detection device as claimed in claim 12 is characterized in that: wherein this sampling point disarrangement device is selected a sampling point randomly in the output signal of this chip matched filtering unit.
14. elementary sync detection device as claimed in claim 12, it is characterized in that: wherein this sampling point disarrangement device is selected an optimal sampling point in the output signal of this chip matched filtering unit, and wherein this optimal sampling point has maximum sampling value in the output signal of this chip matched filtering unit.
15. elementary sync detection device as claimed in claim 11, it is characterized in that: wherein the carrier frequency uncertain region of this entering signal refers to, frequency range between the maximum possible frequency of this entering signal and the minimum possibility frequency, wherein this carrier frequency uncertain region is owing to the unstable institute of the frequency of the crystal oscillator of user's set causes.
16. elementary sync detection device as claimed in claim 15 is characterized in that: wherein a plurality of zonules are with the carrier frequency uncertain region of this entering signal of identical distance five equilibrium.
17. elementary sync detection device as claimed in claim 16 is characterized in that: wherein this sub-carrier frequencies is positioned at the centre of these a plurality of zonules.
18. elementary sync detection device as claimed in claim 11 is characterized in that: wherein the number of these a plurality of cyclic buffers is decided by the number of a plurality of zonules of the carrier frequency uncertain region institute cutting of this entering signal.
19. as claim 1 or 11 described elementary sync detection devices, it is characterized in that: wherein this elementary sync detection device is used in Wideband-CDMA/frequency division duplex system.
20. as claim 1 or 11 described elementary sync detection devices, it is characterized in that: wherein this elementary sync detection device is used in mobile device and radio individual digitlization assistance system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB021202613A CN1234212C (en) | 2002-05-17 | 2002-05-17 | Primary synchronous detection system for honeycomb searching of division code multiple task assess system |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021202613A CN1234212C (en) | 2002-05-17 | 2002-05-17 | Primary synchronous detection system for honeycomb searching of division code multiple task assess system |
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| CN1458757A CN1458757A (en) | 2003-11-26 |
| CN1234212C true CN1234212C (en) | 2005-12-28 |
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| CN100405866C (en) * | 2004-01-12 | 2008-07-23 | 大唐移动通信设备有限公司 | Quick frequency scanning method for howing estate primary searching |
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