CN1208826C - Design of digital image amplifying and shrinking integrated circuit - Google Patents
Design of digital image amplifying and shrinking integrated circuit Download PDFInfo
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- CN1208826C CN1208826C CN 03111801 CN03111801A CN1208826C CN 1208826 C CN1208826 C CN 1208826C CN 03111801 CN03111801 CN 03111801 CN 03111801 A CN03111801 A CN 03111801A CN 1208826 C CN1208826 C CN 1208826C
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Abstract
The present invention relates to a method for designing a digital image zoom integrated circuit (IC), which belongs to the field of IC technology. The method comprises the following steps: a read-write control module selects a row memory and generates a read-write address, and source image data is firstly buffered by the row memory; then, RGB (Red Green Blue) values are extracted from the correspondent address, and field zoom transformation is carried out according to a field zoom factor; the field zoom factor vcoef is generated by adding a field step length at the start of every line vcoef [5: 0] by an accumulator. Afterwards, line zoom transformation is carried out to the RGB values zoomed by a field according to a line zoom factor, and the line zoom factor hcoef is similarly generated by adding a line step length at every clock rising edge hcoef [5: 0] by the accumulator. A read address is obtained by accumulating the high bits of the line zoom factor and the field zoom factor, i.e. hcoef [7: 6] and vcoef [7: 6]; finally, objective RGB values are output. The present invention has the advantage of simple structure and can simultaneously realize two functions of upward zoom and downward zoom in a single circuit; thus, the number and the area required by chips are greatly decreased, and the cost is reduced. The present invention can be widely used for image system converted circuits of various flat panel displays.
Description
Technical field
The invention belongs to integrated circuit (IC) design manufacturing technology field, more specifically to the improvement of the method for designing of digital image scaling integrated circuit.
Background technology
The existing video standard conversion circuit that is used for the various types of flat panel display is all complicated, upwards zoom function (image is transformed to HD by the low definition form) and downwards zoom function (image is transformed to HD by the low definition form) often by different circuit realizations.Tracing it to its cause, is simple in structure because of not having, and controls digital image scaling integrated circuit cleverly.
Purpose of the present invention just is to address the above problem, provide a kind of simple in structure, control the method for designing of digital image scaling integrated circuit easily.Make that upwards zoom function can be realized by single circuit with downward zoom function, thereby greatly reduce cost.
Summary of the invention
In order to achieve the above object, the present invention includes following steps: select line storage and produce read/write address by a read-write control module, with source image data elder generation process line storage buffer memory; Take out rgb value then in corresponding address and carry out a scale transformation according to the field zoom factor, its midfield zoom factor vcoef is by step-length accumulator vcoef[5:0 when the every row beginning] add the step-length of entering the court and produce; To make the row scale transformation according to the capable zoom factor of appropriate address through the rgb value of field convergent-divergent again, wherein go zoom factor hcoef equally by the step-length accumulator at each rising edge clock hcoef[5:0] add up step-length and produce; Export correct target rgb value at last.
The image convergent-divergent that makes progress, when promptly " amplifying in proportion ", target image pixel space grid point distribution is close than source images, and the distance of adjacent lattice point i.e. " step-length " is short.In contrast, the downward convergent-divergent of image, promptly when " scaled ", target image pixel space grid point distribution is rare than source images, and the distance of adjacent lattice point i.e. " step-length " is long.
No matter " amplifying in proportion " still be " scaled ", and the pixel of new generation can multiply by weight coefficient by adjacent four source pixel points sues for peace and obtain.If (level or vertical direction) unit distance is 64 between adjacent two source image vegetarian refreshments.Source image vegetarian refreshments and target pixel points are x apart from horizontal direction, and vertical direction is y (wherein x, a y value in 0～64 scope).For the linear interpolation method, the weight coefficient of certain source image vegetarian refreshments is as follows:
coef＝(64-x)(64-y) (1)
Adopt vertical direction, horizontal direction is made the method for convergent-divergent computing according to this.Horizontal direction then, the zoom factor of vertical direction is respectively:
hcoef＝(64-x)
(2)
vcoef＝(64-y)
Wherein, hcoef is the zoom factor of line direction (being horizontal direction), and vcoef is the zoom factor of field direction (vertical direction).
As the Zoom method that adopts the ortho position to duplicate, then working as x, y is less than 32 o'clock, and coefficient is 64, and all the other are zero.
The neighbor distance in object pixel space is that step-length can be obtained by following formula:
For the convergent-divergent that makes progress, (or the effective line number in field, source) counts (or the effective line number of target field) greatly than target line is effective because the source row is effectively counted, row step-length (step-length) value between 0～64; On the contrary for downward convergent-divergent because the source row is effectively counted (or the effective line number in field, source) count than target line is effective (or the effective line number of target field) little, row step-length (step-length) value between 64～128.
Whole design framework is: when data arrive, deposit at first successively and be numbered buffer memory in 0,1,2,3 the memory.Take out adjacent R, G, B gray value at 4 by adjacent two row par positions then.Earlier through the interlude convergent-divergent, again through the space convergent-divergent.If (i is that source images i is capable, the RGB gray value of j row j) to S, and (n is the RGB gray value that n is capable, m is listed as of target image m) to D, and behind the scale transformation of field, its value is D
v(n, m), behind the row scale transformation, its rgb value is D
h(n, m).Relation between them can be provided by following formula:
D
v(n，m)＝(S(i，j)vcoef(n)+S(i+1，j)vcoef(n+1))/64
D
v(n，m+1)＝(S(i，j+1)vcoef(n)+S(i+1，j+1)vcoef(n+1))/64
(4)
D
h(n，m)＝(D
v(n，m)hcoef(m)+D
v(n，m+1)hcoef(m+1))/64
D(n，m)＝D
h(n，m)
Wherein,
64*i+x＝λ
vn
(5)
64*j+y＝λ
hm
Plain position of (5) formula target image and the plain position of source images corresponding relation.I, j are λ
vN, λ
hM is divided by the merchant's of 64 gained integer part, and x, y are corresponding remainder parts.According to following formula, can take out rgb value in the corresponding address of memory and object pixel ranks position and carry out scale transformation, thereby produce correct rgb value.Concrete circuit is to be selected line storage and produced read/write address by a read-write control module.Actual circuit can be with the multiplication in a step-length accumulator (coefficient generator) the replacement following formula.In every when beginning row, to the zero clearing of row coefficient generator, when every beginning to field coefficient generator zero clearing.For the row coefficient generator, at each rising edge clock hcoef[5:0] add up step-length and obtain new hcoef[7:0]; For vcoef, at every when beginning row, vcoef[5:0] the extra show step-length obtains new vcoef[7:0].The remainder hcoef[5:0 of mould 64] and vcoef[5:0] corresponding to the convergent-divergent weight of following formula, x, y.Hcoef, vcoef's is more high-order, hcoef[7:6], vcoef[7:6] be used for controlling the address of line storage.Adding vcoef[7:6 when the every row beginning with location, the place accumulator of two bit wides] value of gained is exactly line storage reference numeral i.Again with the row address accumulator of 11 bit wides at each clock along adding hcoef[7:6] just obtain pairing storage address j.For convergent-divergent upwards, hcoef[7:6], vcoef[7:6] only may be 0 or 1; For downward convergent-divergent, hcoef[7:6], vcoef[7:6] only may be 1 or 2.
Purpose of the present invention comes to this and realizes.
The invention provides a kind of simple in structure, control the method for designing of digital image scaling integrated circuit easily.Make no matter upwards convergent-divergent still is that downward convergent-divergent can both be realized automatically by same set of circuit, and need not distinguish, reduced the complexity and the cost of chip.It can be widely used in the circuit of various types of flat panel display video standard conversion.
Description of drawings
Fig. 1 is a design principle block diagram of the present invention.
Fig. 2 is the low schematic diagram of the definition of this target image of source images.
Fig. 3 is the source images schematic diagram higher than target image definition.
Shown in Figure 1, the present invention includes following steps: select line storage and produce read/write address by a read-write control module, with source image data elder generation process line storage buffer memory; Take out rgb value in corresponding address then and carry out a scale transformation according to the field zoom factor; Again will be through the rgb value of field convergent-divergent the capable scale transformation of capable zoom factor according to correspondence; Export correct target rgb value at last.Zoom factor is produced by coefficient generator, and by row, a step-length accumulation obtains row respectively, a zoom factor.
Shown in Figure 2, source images is lower than the definition of target image.Represent the source image pixels space lattice with black circle among the figure, represent target image pixel space lattice point with spider.
Shown in Figure 3, source images is than the definition height of target image.Represent the source image pixels space lattice with black circle among the figure, represent target image pixel space lattice point with spider.
Embodiment
The method for designing of 1. 1 kinds of digital image scaling integrated circuits of embodiment.May further comprise the steps: produce read/write address by a read-write control module, source image data elder generation process line storage buffer memory; Take out rgb value then in corresponding address and carry out a scale transformation according to the field zoom factor, a zoom factor vcoef is by accumulator vcoef[5:0 when the every row beginning] add the step-length of entering the court and produce; To change according to the capable convergent-divergent of corresponding row zoom factor through the rgb value of field convergent-divergent again.Row zoom factor hcoef equally by accumulator at each rising edge clock hcoef[5:0] add up step-length and produce; Reading the address also is to add hcoef[7:6 by an accumulator at each rising edge clock] obtain.Last export target rgb value.Embodiment 1 is simple in structure, controls ingeniously, and zoom factor and storage address produce simply ingenious, can realize upwards zoom function and zoom function downwards automatically by same circuit, greatly reduce the complexity and the cost of chip.It can be widely used in the circuit of all kinds of dull and stereotyped display image standards conversions.
Claims (1)
1. the method for designing of a digital image scaling integrated circuit is characterized in that it may further comprise the steps: selected line storage and produced read/write address by a read-write control module, with source image data elder generation process line storage buffer memory; Take out rgb value in corresponding address then and carry out a scale transformation according to the field zoom factor, its midfield zoom factor vcoef by the step-length accumulator at every when beginning row vcoef[5:0] add the step-length of entering the court and produce: again at the rgb value of Jiang Jingchang convergent-divergent according to the capable scale transformation of corresponding row zoom factor, wherein go zoom factor hcoef equally by the step-length accumulator at each rising edge clock hcoef[5:0] add up step-length and produce: the generation of reading the address also is constantly with the high-order vcoef[7:6 of field zoom factor by accumulator] and the high-order hcoef[7:6 of row zoom factor] add up respectively and obtain the corresponding row memory and number and row address, export correct target rgb value at last.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03111801 CN1208826C (en) | 2003-01-01 | 2003-01-01 | Design of digital image amplifying and shrinking integrated circuit |
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| CN1208826C true CN1208826C (en) | 2005-06-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010083711A1 (en) * | 2009-01-23 | 2010-07-29 | 中兴通讯股份有限公司 | Digital image scaling method and integrated system thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7117456B2 (en) * | 2003-12-03 | 2006-10-03 | International Business Machines Corporation | Circuit area minimization using scaling |
| CN104869284B (en) * | 2015-05-14 | 2018-05-04 | 北京邮电大学 | The high efficiency FPGA implementation method and device of a kind of bilinear interpolation interpolator arithmetic |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010083711A1 (en) * | 2009-01-23 | 2010-07-29 | 中兴通讯股份有限公司 | Digital image scaling method and integrated system thereof |
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