CN1205545A - Figure measuring setting and method for measuring circuit figure dimensional accuracy and overlapping accuracy - Google Patents
Figure measuring setting and method for measuring circuit figure dimensional accuracy and overlapping accuracy Download PDFInfo
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- CN1205545A CN1205545A CN 98104464 CN98104464A CN1205545A CN 1205545 A CN1205545 A CN 1205545A CN 98104464 CN98104464 CN 98104464 CN 98104464 A CN98104464 A CN 98104464A CN 1205545 A CN1205545 A CN 1205545A
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Abstract
A measurement pattern set includes a first pattern formed on a lower layer, which is to be the basis of the measurement; and a second pattern formed on an upper layer that is the same level of the circuit pattern. The second pattern is arranged to adjoin to the first pattern. The first and second patterns are measured in size so as to calculate a dimension error of the second pattern relative to its design value and an overlay error of the second pattern relative to the first pattern at the same time. The dimension accuracy and overlay accuracy of the circuit pattern is calculated in response to the above calculated dimension error and the overlay error.
Description
The present invention relates to the photoetching process in the semiconductor device manufacturing.In more detail, relate to measurement pattern setting and be used to measure the dimensional accuracy that is transferred to the circuitous pattern on the substrate surface and the method for overlapping accuracy.
In the manufacture process of semiconductor integrated circuit, in order to improve the quality of semiconductor integrated circuit, photoetching process is important.This photoetching process uses projection aligner to carry out.
Under regular situation, use projection aligner that the circuitous pattern that forms on the master is repeatedly transferred on the Semiconductor substrate such as wafer.Measure the size of the circuitous pattern that is transferred on the wafer with respect to designing requirement, also measure overlapping accuracy with respect to the figure in the lower floor.
In the method for routine, this circuitous pattern is provided with the measurement pattern that is specifically designed to graphical measurement.This measurement pattern detects by special measurement mechanism, with the size and the comparison of its design load of this measurement, so that the scale error of this circuitous pattern to be provided.According to this scale error, determine that this circuitous pattern is whether in the predetermined allowable range of dimensional accuracy standard.When this scale error was in the dimensional accuracy critical field, this circuitous pattern was an acceptable.On the other hand, when the scale error of this circuitous pattern is outside critical field, just will comprise that the chip of this unacceptable circuitous pattern is given up as defective product.
In order to detect position, use another special measurement pattern with respect to the circuitous pattern of the figure in the lower floor.In lower floor, also form another special measurement pattern.These two measurement pattern in top layer and lower floor detect by overlapping measurement mechanism.To come comparison in the difference and the overlapping accuracy standard of the position between two special measurement pattern in top layer and the lower floor.
As mentioned above, when being transferred to circuitous pattern on the wafer according to dimensional accuracy standard and overlapping accuracy standard when being confirmed as accepting, this wafer moves on to next operation.
But above-described conventional method has following problem.
(1) for the dimensional accuracy and the overlapping accuracy of measuring circuit figure, needs two kinds of different special arrangements.
(2) for the dimensional accuracy and the overlapping accuracy of measuring circuit figure, need on substrate, form two kinds of different special measurement pattern.
(3) use different devices to determine dimensional accuracy and overlapping accuracy, therefore carry out measuring process and will expend the long time.
(4) because determine dimensional accuracy and overlapping accuracy, so need carry out another calculating so that determine the overall accuracy (graphical quality) of this circuitous pattern according to different standards.In general, in the process that overall accuracy is measured, be in the scope of dimensional accuracy standard as circuitous pattern, then the admissible scope of overlapping accuracy can broaden.
Therefore, an object of the present invention is to provide a kind of measurement pattern setting, adopt this setting can easily in the short time, determine the dimensional accuracy and the overlapping accuracy of circuitous pattern.
Another object of the present invention provides a kind of dimensional accuracy of measuring circuit figure and method of overlapping accuracy of being used for, and adopts this method can easily determine the dimensional accuracy and the overlapping accuracy of circuitous pattern in the short time.
A further object of the present invention provides a kind of dimensional accuracy of measuring circuit figure and device of overlapping accuracy of being used for, and adopts this device can easily use simple structure to determine the dimensional accuracy and the overlapping accuracy of circuitous pattern.
Other purpose of the present invention, advantage and novel characteristics will propose in the following description, will become clearly in analyzing following content for these professional personnel, or can be understood from the practice of the present invention.Objects and advantages of the present invention can and comprehensively realize and obtain by means of the means of pointing out in the accompanying Claim book especially.
Measurement pattern setting according to the 1st aspect of the present invention comprises: be intended as the 1st figure that forms in the lower floor of this based measurement; With at itself be the 2nd figure that forms on the upper strata of identical level of this circuitous pattern.The 2nd figure is configured near the 1st figure.Measure the size of the 1st and the 2nd figure, so that calculate the 2nd figure simultaneously with respect to the scale error of its design load and the 2nd figure aliasing error with respect to the 1st figure.Calculate the dimensional accuracy and the overlapping accuracy of this circuitous pattern according to above-mentioned calculated scale error and aliasing error.
In according to the method aspect the of the present invention the 2nd, form the 1st figure in the lower floor of this based measurement being intended as.Then, on the upper strata of identical level that itself is this circuitous pattern, form the 2nd figure, wherein the 2nd figure is configured near the 1st figure.Secondly, measure the size of the 1st and the 2nd figure, so that calculate the 2nd figure simultaneously with respect to the scale error of its design load and the 2nd figure aliasing error with respect to the 1st figure.Then, calculate the dimensional accuracy and the overlapping accuracy of this circuitous pattern according to above-mentioned calculated scale error and aliasing error.
The measurement mechanism that comprises the size of measuring the 1st and the 2nd figure simultaneously according to the device of the 3rd aspect of the present invention.In lower floor, form the 1st figure, on the upper strata of identical level that itself is this circuitous pattern, form the 2nd figure.This device also comprise calculate simultaneously the 2nd figure with respect to the scale error of its design load and the 2nd figure with respect to the aliasing error of the 1st figure and amount to scale error and the computing unit of aliasing error.This device also is provided with determining unit, this unit with the scale error of the 2nd figure and aliasing error and with predetermined reference point relatively, with the overall graphical quality of determining this circuitous pattern whether in the scope of standard.
According to the present invention, the dimensional accuracy of circuitous pattern and overlapping accuracy can be determined with single measurement mechanism.
In the present invention, each of the 1st and the 2nd figure all can be designed to measure simultaneously the size on X and Y direction.The size on X and Y direction of this figure can be measured simultaneously, the graphical quality of circuitous pattern can be determined independently for each direction.
Have again, the 1st figure can comprise a pair of respectively on different layers at the upwardly extending line graph of X and Y side.In this case, can determine graphical quality independently for each direction with respect to the circuitous pattern of different layers.
In addition, the 1st figure can comprise the line graph of the both sides configuration of an a pair of line that extends respectively on directions X on two different layers; With another to the line graph of the both sides configuration of a upwardly extending line on other two different layers respectively in Y side, thereby measure overlapping accuracy with respect to each of these four different layers.In this case, can determine the graphical quality of circuitous pattern, also can determine the graphical quality of circuitous pattern with respect to two the different technologies (layer) in addition on the Y direction with respect to two the different technologies (layer) on directions X.That is, can determine graphical quality with respect to four different technologies (layer).
Fig. 1 illustrates according to illustrative figure of the present invention, that be used to measure the device of the dimensional accuracy that is transferred to the circuitous pattern on the wafer and overlapping accuracy.
Fig. 2 is the plane graph that the measurement pattern setting of the 1st preferred embodiment of the present invention is shown.
Fig. 3 illustrates the operational flowchart that uses the measurement pattern setting shown in Fig. 2 to determine the graphical quality of circuitous pattern.
Fig. 4 is the plane graph that the measurement pattern setting of the 2nd preferred embodiment of the present invention is shown.
Fig. 5 is the plane graph that the measurement pattern setting of the 3rd preferred embodiment of the present invention is shown.
Fig. 6 is the plane graph that the measurement pattern setting of the 4th preferred embodiment of the present invention is shown.
Fig. 1 is used to measure the dimensional accuracy of the circuitous pattern (not shown) that is transferred on the wafer 2 and the device of overlapping accuracy, and this wafer 2 is placed on the wafer station 4.This device comprises photodetector 6, is connected to the computing unit 7 of photodetector 6 and is connected to computing unit 7 order unit 8 really.This photodetector 6 comprises image sensor, introduces electric charge in this transducer when the light from the chip region of wafer 2 is focused in its surface.That is, the 1st and the 2nd measurement pattern (11 and 12) that this photodetector 6 detects on the chip region of transferring to wafer 2 is with the size (" a ", " b " and " c ") of measuring these figures simultaneously.In each chip region of wafer 2, shift a plurality of circuitous patterns in a mode on another.
Fig. 2 illustrates the lip-deep measurement pattern setting that is transferred to wafer 2 according to the 1st preferred embodiment of the present invention.This measurement pattern setting comprises the 1st line graph 11 and the 2nd line graph 12, and these figures can be transferred to outside the circuitous pattern in the chip region.The 1st line graph 11 is to go up the etching figure that forms in lower floor's (reference layer), and this lower floor is intended as the basis of overlapping accracy measuring.The 2nd line graph 12 is the resist figures that form on the upper strata that overlaps in the lower floor.The the 1st and the 2nd line graph 11 and 12 is configured in the position of mutual vicinity.
Refer again to Fig. 1, computing unit 7 calculates the 2nd measurement pattern 12 simultaneously with respect to the scale error of its design load and the 2nd measurement pattern 12 aliasing error with respect to the 1st measurement pattern 11.This computing unit 7 also amounts to scale error and aliasing error.Scale error that determining unit 8 will provide from computing unit 7 and aliasing error and with predetermined reference point relatively, with the overall graphical quality of determining this circuitous pattern whether in the scope of standard.
The 1st line graph 11 is the figures that are specifically designed to dimensional measurement, and this graphic designs is become to have size (width) " a ".The 2nd line graph 12 also is the figure that is specifically designed to dimensional measurement, and this graphic designs is become to have size (width) " c ".The the 1st and the 2nd line graph 11 and 12 is configured to have distance " b ", so that in it forms, do not have problems.Distance between the line graph 11 and 12 " b " is design arbitrarily.For example, above-mentioned size " a ", " b " and " c " can be respectively 0.5 micron, 1 micron and 0.5 micron.As mentioned above, measure the size " a " of the 1st line graph 11, distance " b " between the line graph 11 and 12 and " c " of the 2nd line graph 12 by the photodetector shown in Fig. 16.
Fig. 3 illustrates the step of the overlapping accuracy of the dimensional accuracy that is used for definite circuitous pattern.Computing unit 7 is based on the value " a " of last planar survey, " b " and " c " determines circuitous pattern as following precision:
(1) at first computing unit 7 determines that the measured value " c " of the 2nd line graphs 12 is whether in admissible critical field.When it in admissible critical field the time, calculate poor (scale error) Δ c that departs from its design load., wafer 2 is processed again outside critical field the time as it.
(2) secondly computing unit 7 calculates the aliasing error of the 2nd line graph 12 with respect to the 1st line graph 11.Calculate aliasing error " A " according to following equation:
Aliasing error (A)=measured value [(a/2)+b+ (c/2)]-design load [(a/2)+b+ (c/2)]
Measured the size " a " of the 1st line graph 11 before forming the 2nd line graph 12, this size is always in admissible scope.Suppose that the 1st line graph 11 is Δ a ' with respect to the scale error of its design load.
Come to determine overlapping accuracy according to the following equation:
B≥a’+Δc+A
Wherein " B " is the critical field of overlapping accuracy.
If satisfy above-mentioned formula, then circuitous pattern can be accepted.
According to above-mentioned method, measure the size of the 1st and the 2nd line graph 11 and 12 simultaneously, thereby available single-measurement device (6,7 and 8) is determined the dimensional accuracy and the overlapping accuracy of circuitous pattern.
Fig. 4 illustrates the lip-deep measurement pattern setting of transferring to wafer 2 according to the 2nd preferred embodiment of the present invention.This measurement pattern setting is included in lower floor's (reference layer) and goes up the 1st measurement pattern 21 that forms and the 2nd measurement pattern 22 that forms on the upper strata.This lower floor is as the basis of the overlapping accracy measuring on upper strata.The shape of the 1st and the 2nd measurement pattern 21 and 22 is respectively made foursquare frame.The 2nd measurement pattern 22 is configured to surround at the center the 1st measurement pattern.
The 1st measurement pattern 21 is designed to have " c ", " d " that is suitable for size Control, the width of frame of " i " and " j ", and has sufficiently long length so that measurement size " c ", " d ", " i " and " j ".Width of frame " c ", " d ", " i " and " j " of the 1st measurement pattern 21 are designed to suitable dimensions, not too big also not too little, thus make this size approach the size that same one deck (upper strata) is gone up the circuitous pattern that forms.
Form the 2nd measurement pattern 22 in the mode identical with the 1st embodiment.The 2nd measurement pattern 22 is resist figures, with its be designed to have " a ", the width of frame of " f ", " g " and " l " so that size objectives is provided.Width of frame " a ", " f ", " g " and " l " of the 2nd measurement pattern 22 are designed to suitable dimensions, not too big also not too little, thus make this size approach the size that same one deck (upper strata) is gone up the circuitous pattern that forms.
The the 1st and the 2nd measurement pattern 21 and 22 is configured to have distance " b ", " e ", " h " and " k " arbitrarily, thereby can under the situation that or not 1st measurement pattern 21 is not produced any influence, forms the 2nd measurement pattern 22.In the present embodiment, the 1st and the 2nd measurement pattern 21 and 22 is designed to meet the relation of " c=d=i=j ", " a=f=g=l " and " b=e=h=k ".For example, the 1st measurement pattern 21 is designed to have 1 to 2 micron insied width D.
For dimensional accuracy and the overlapping accuracy that circuitous pattern is provided, at first measure the 1st and the 2nd measurement pattern 21 of formation like this and each size of 22.In this measurement pattern is provided with, suppose that horizontal direction is that X and vertical direction are Y.In single plane, measure the 1st and the 2nd measurement pattern 21 in the zone be configured in X-X ' and Y-Y ' and each size of 22 simultaneously.
According to the result of this measurement, as following, calculate the 2nd measurement pattern 22 scale error Δ 22x with respect to its design load on directions X:
Δ22x=(a+f)／2
Supposition the 1st measurement pattern 21 scale error with respect to its design load on directions X is Δ 21x now, and this value is measured in advance.Calculate according to the following equation at the aliasing error Δ x between the 1st and the 2nd measurement pattern 21 and 22 on the directions X:
(Δ x)=measured value [(a/2)+b+ (c/2)+(d/2)+e+ (f/2)]/the 2-design load [(a/2)+b+ (c/2)+(d/2)+e+ (f/2)]/2
When aforementioned calculation value Δ 21x, Δ 22x and Δ x meet following relation (formula), determine that promptly this circuitous pattern is an acceptable, wherein " x " is the preset range of overall accuracy standard:
x≥Δ21x+Δx+Δ22x
In the mode identical, carry out the measurement of the 2nd measurement pattern 22 on the Y direction with directions X.Adopt the figure configuration of the 2nd embodiment, can on X and Y direction, measure simultaneously, thereby the pattern precision data of circuitous pattern can be provided on each direction independently.
In the present embodiment, though get sized data, can only use the sized data of a side to determine pattern precision and have identical advantage from the right side and the left side of figure.In the mode identical, utilize device shown in Figure 1 to carry out definite process of the graphical quality of the computational process of measurement, scale error and aliasing error of figure 21 and 22 and this circuitous pattern with the 1st preferred embodiment.
As previously discussed, according to the 2nd preferred embodiment, can on X and Y direction, measure each size of the 1st and the 2nd measurement pattern 21 and 22 simultaneously, thereby can easily determine the graphical quality of this circuitous pattern each direction.
Fig. 5 illustrates the lip-deep measurement pattern setting of transferring to wafer 2 according to the 3rd preferred embodiment of the present invention.In the present embodiment, use the circuitous pattern of overlapping accuracy determine to(for) the different reference layer of X and Y direction respectively.This measurement pattern setting comprises the 1st pair of measurement pattern 31, the 2nd pair of measurement pattern 32 and the 3rd measurement pattern 33.The 1st pair of measurement pattern 31 is designed to extend on the Y direction, the 2nd pair of measurement pattern 32 is designed to extend on directions X.The 3rd measurement pattern 33 is formed foursquare frame.
Itself be the 1st layer of lowermost layer and on the 2nd layer on the 1st layer, forming the 1st and the 2nd pair of measurement pattern 31 and 32 respectively.Form the 3rd layer 33 on top layer, also shifting on this top layer has circuitous pattern.Form the 1st pair of measurement pattern 31 in the mode identical with the figure of in the 1st and the 2nd preferred embodiment, describing.
With the mode identical with the 2nd preferred embodiment calculate measurement pattern 31 with respect to the scale error Δ 31x of its design load, measurement pattern 33 with respect to the scale error Δ 33x of its design load and the aliasing error Δ x between measurement pattern 31 and 33.On directions X, determine the pattern precision of circuitous pattern according to the following equation:
x≥Δ31x+Δx+Δ33x
Wherein " x " is the preset range of the overall accuracy standard of this circuitous pattern.
On the Y direction, with directions X on identical mode carry out the measurement of figure 31 to 33 and the calculating of dimensional accuracy and overlapping accuracy.In different layers, form the 1st and the 2nd pair of measurement pattern 31 and 32, therefore can determine the overlapping accuracy of the circuitous pattern on top layer respectively with respect to two different layers independently.
Utilize the device shown in Fig. 1 to carry out definite process of the graphical quality of the computational process of measurement, scale error and aliasing error of figure 31 to 33 and circuitous pattern in the mode identical with the 1st preferred embodiment.
According to the 3rd preferred embodiment, can on X and Y direction, measure each size of measurement pattern 31 to 33 simultaneously, thereby can easily determine the graphical quality of this circuitous pattern to each direction with respect to different layers.
Fig. 6 illustrates the lip-deep measurement pattern setting of transferring to wafer 2 according to the 4th preferred embodiment of the present invention.In the present embodiment, use two circuitous pattern of overlapping accuracies determine to(for) X and the variant layer of Y direction respectively.This measurement pattern setting comprises the 1st to the 5th measurement pattern 41 to 45.Extend on the Y direction in the right side and the left side that the 1st and the 2nd measurement pattern 41 and 42 are designed to the online Y-Y ' of difference.Being designed to the 3rd and the 4th measurement pattern 43 and 44 respectively, upside and the downside of online X-X ' extend on directions X.The 5th measurement pattern 45 is formed foursquare frame, surrounded by the 1st to the 4th measurement pattern 41 to 44.
Form the 1st to the 5th measurement pattern 41 to 45 by order at different layers from minimum to the top.Form circuitous pattern with the 5th measurement pattern 45 at top layer.Measure the overlapping accuracy that layer 41 and 42 is used to measure the circuitous pattern on directions X with the 1st and the 2nd.Measure the overlapping accuracy that layer 43 and 44 is used to measure the circuitous pattern on the Y direction with the 3rd and the 4th.
In order to measure measurement pattern 41 to 45, at first measure each size on directions X (X-X ').When forming these figures, obtain the 1st measurement pattern 41 in advance with respect to the scale error Δ a of its design load and the 2nd measurement pattern 42 scale error Δ f with respect to its design load.According to the measurement result on directions X, calculate the size " c " of the 5th measurement pattern 45 and the mean value of " d ", calculate the scale error Δ 45 of the 5th measurement pattern 45 then with respect to its design load.
According to the aliasing error Δ (41-45) of formula " Δ (41-45)=(a/2)+b+ (c/2) " calculating between the 1st and the 5th measurement pattern 41 and 45.Therefore, determine the overall accuracy (graphical quality) of figure 45 according to the following equation with respect to figure 41:
x1≥Δa+Δ(41-45)+Δ45
Wherein " x1 " is the admissible scope of accuracy standard.
Figure 45 means the circuitous pattern that the forms graphical quality with respect to the lowermost layer that forms the 1st measurement pattern 41 thereon on top layer with respect to the overall accuracy of figure 41.
In the same way, according to the aliasing error Δ (42-45) of formula " Δ (42-45)=(d/2)+e+ (f/2) " calculating between the 2nd and the 5th measurement pattern 42 and 45.Therefore, determine the overall accuracy of the 5th measurement pattern 45 according to the following equation with respect to the 2nd measurement pattern 42:
x2≥Δf+Δ(42-45)+Δ45
Wherein " x2 " is the admissible scope of accuracy standard.Figure 45 means the circuitous pattern that the forms graphical quality with respect to the lower floor that forms the 2nd measurement pattern 42 thereon on top layer with respect to the overall accuracy of figure 42.
On the Y direction, measure each scale error of measurement pattern 43,44 and 45, measure the overlapping accuracy of the 5th measurement pattern 45 respectively with respect to the 3rd and the 4th measurement pattern 43 and 44.According to the result of this measurement, determine the graphical quality of circuitous pattern.
Utilize the device shown in Fig. 1 to carry out definite process of the graphical quality of the computational process of measurement, scale error and aliasing error of figure 41 to 45 and circuitous pattern in the mode identical with the 1st preferred embodiment.
According to the 4th preferred embodiment, can on directions X, determine the graphical quality of circuitous pattern with respect to two different technologies (layer), also can on the Y direction, determine the graphical quality of circuitous pattern with respect to other two different technologies (layer).That is, can on X and Y direction, measure simultaneously, can determine the graphical quality of circuitous pattern with respect to four different technologies (layer) to measurement pattern.As outside measurement pattern 41 and 42, forming other figures, then can increase the operation number of determining graphical quality.
Though for complete clearly openly the present invention with reference to certain embodiments it is narrated, but therefore do not limited accompanying Claim, and it is thought can to make one of skill in the art, fall into the enforcement that all corrections of the substance that proposes and other may structures here well.
Claims (14)
1. one kind is used to measure the dimensional accuracy of the circuitous pattern that is transferred to substrate surface and the measurement pattern setting of overlapping accuracy, comprising:
Be intended as the 1st figure that forms in the lower floor of this based measurement; With
The 2nd figure that forms on the upper strata of identical level that itself is this circuitous pattern is configured to the 2nd figure near the 1st figure, wherein
Measure the size of the 1st and the 2nd figure, so that calculate the 2nd figure simultaneously, calculate the dimensional accuracy and the overlapping accuracy of this circuitous pattern then according to above-mentioned calculated scale error and aliasing error with respect to the scale error of its design load and the 2nd figure aliasing error with respect to the 1st figure.
2. measurement pattern setting as claimed in claim 1, wherein
Amount to scale error and aliasing error, with this and with predetermined reference point relatively so that whether the overall graphical quality of determining circuitous pattern in critical field.
3. measurement pattern setting as claimed in claim 1, wherein
The the 1st and the 2nd figure all is designed to measure simultaneously size on X and Y direction.
4. measurement pattern setting as claimed in claim 3, wherein
The 1st figure comprise a pair of respectively on different layers, at the upwardly extending line graph of X and Y side.
5. measurement pattern setting as claimed in claim 4, wherein
The 1st figure comprises the line graph of the both sides configuration of an a pair of line that extends respectively on directions X on two different layers; With another to the line graph of the both sides configuration of a upwardly extending line on other two different layers respectively in Y side, thereby measure overlapping accuracy with respect to each of these four different layers.
6. one kind is used to measure the dimensional accuracy of the circuitous pattern that is transferred to substrate surface and the method for overlapping accuracy, comprising:
Be intended as formation the 1st figure in the lower floor of this based measurement;
On the upper strata of identical level that itself is this circuitous pattern, form the 2nd figure, wherein the 2nd figure is configured near the 1st figure;
Measure the size of the 1st and the 2nd figure, so that calculate the 2nd figure simultaneously with respect to the scale error of its design load and the 2nd figure aliasing error with respect to the 1st figure; With
Calculate the dimensional accuracy and the overlapping accuracy of this circuitous pattern according to above-mentioned calculated scale error and aliasing error.
7. method as claimed in claim 6, wherein
Amount to scale error and aliasing error, with this and with predetermined reference point relatively so that whether the overall graphical quality of determining circuitous pattern in critical field.
8. method as claimed in claim 6, wherein
In forming the step of the 1st and the 2nd figure, design each of the 1st and the 2nd figure so that measure simultaneously on X and Y direction size and
In the step that forms the 1st and the 2nd figure, on X and Y direction, measure the 1st and the 2nd figure simultaneously, so that be provided at dimensional accuracy and overlapping accuracy on each direction.
9. method as claimed in claim 8, wherein
In the step that forms the 1st figure, form a pair of line graph so that on different layers, on X and Y direction, extend respectively, thereby measure overlapping accuracy with respect to these two different layers.
10. method as claimed in claim 9, wherein
In the step that forms the 1st figure, a pair of line graph is configured in the both sides of a line that on directions X, extends on two different layers respectively; With another line graph is configured in addition on two different layers the both sides of a upwardly extending line in Y side respectively, thereby measures overlapping accuracy with respect to each of these four different layers.
11. one kind is used to measure the dimensional accuracy of the circuitous pattern that is transferred to substrate surface and the device of overlapping accuracy, comprises:
Measure the measurement mechanism of the 1st and the 2nd dimension of picture simultaneously, wherein in lower floor, form the 1st figure, on the upper strata of identical level that itself is this circuitous pattern, form the 2nd figure;
Computing unit, calculate simultaneously the 2nd figure with respect to the scale error of its design load and the 2nd figure with respect to the aliasing error of the 1st figure and amount to scale error and aliasing error; With
Determining unit, this unit with the scale error of the 2nd figure and aliasing error and with predetermined reference point relatively, with the overall graphical quality of determining this circuitous pattern whether in the scope of standard.
12. device as claimed in claim 11, wherein
Design each of the 1st and the 2nd figure, so as to measure simultaneously on X and Y direction size and
This measurement mechanism is measured the 1st and the 2nd figure simultaneously on X and Y direction, so that be provided at dimensional accuracy and overlapping accuracy on each direction.
13. device as claimed in claim 12, wherein
The 1st figure comprise a pair of on different layers at the upwardly extending line graph of X and Y side, thereby measure overlapping accuracies with respect to these two different layers.
14. device as claimed in claim 13, wherein
The 1st figure comprises the line graph of the both sides configuration of an a pair of line that extends respectively on directions X on two different layers; With another to respectively on other two different layers in Y side the line graph of the both sides of upwardly extending line configurations, thereby measure overlapping accuracy with respect to each of these four different layers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 98104464 CN1205545A (en) | 1997-07-11 | 1998-02-18 | Figure measuring setting and method for measuring circuit figure dimensional accuracy and overlapping accuracy |
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| JP186954/97 | 1997-07-11 | ||
| CN 98104464 CN1205545A (en) | 1997-07-11 | 1998-02-18 | Figure measuring setting and method for measuring circuit figure dimensional accuracy and overlapping accuracy |
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| CN1205545A true CN1205545A (en) | 1999-01-20 |
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| CN101135556B (en) * | 2006-08-31 | 2011-08-31 | 株式会社日立高新技术 | Pattern deviation measuring method and device |
| US8173962B2 (en) | 2006-08-31 | 2012-05-08 | Hitachi High-Technologies Corporation | Pattern displacement measuring method and pattern measuring device |
| CN103839847A (en) * | 2012-11-23 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Graphics detection method |
| CN103839847B (en) * | 2012-11-23 | 2017-09-26 | 中芯国际集成电路制造(上海)有限公司 | Graph testing method |
| CN106574832A (en) * | 2014-09-11 | 2017-04-19 | 株式会社日立高新技术 | Overlay measurement method, device and display device |
| CN106574832B (en) * | 2014-09-11 | 2018-11-02 | 株式会社日立高新技术 | It is overlapped measurement method, device and display device |
| CN106019860A (en) * | 2016-07-27 | 2016-10-12 | 京东方科技集团股份有限公司 | Determining method of alignment precision |
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