CN1205114A - Process for single mask C4 solder bump fabrication - Google Patents

Abstract

A method for removing Ball Limiting Metallurgy (BLM) layers from the surface of a wafer in the presence of Pb/Sn solder bumps. In one embodiment, the BLM comprises two layers: titanium and copper. After Pb/Sn solder-bumps have been formed over the electrical contact pads of the wafer, the BLM copper layer is etched with a H2SO4+H2O2+H2O solution. While removing the copper layer, the H2SO4+H2O2+H2O etchant also reacts with the Pb/Sn solder bumps to form a thin PbO protective layer over the surface of the bumps. When the copper layer has been etched away, the titanium layer is etched with a CH3COOH+NH4F+H2O solution. The PbO layer formed over the surface of the Pb/Sn solder bumps remains insoluble when exposed to the CH3COOH+NH4F+H2O etchant, thereby preventing the solder bumps from being etched in the presence of the CH3COOH+NH4F+H2O etchant. When the titanium etch is complete, the PbO layer is removed from the surface of the Pb/Sn solder bumps by exposing the bumps to an HCl+NH2CSNH2+N

Description

Method for single mask C4 solder bump fabrication

Background

1. Field of the invention

The invention relates to the technical field of semiconductor packaging. More particularly, the present invention relates to a process for fabricating Controlled Collapse chip connection (C4) Pb/Sn microbumps on a wafer surface.

2. Reference to related patent applications

The following co-pending patent applications are referred to:

U.S. patent application Ser. No. 08/347,873, filed concurrently herewith, entitled "method for manufacturing solder bumps for Single mask C4", was made by the inventors: douglas e.crafts, Venkatesan Murali, carorime s.lee.

3. Description of the related Art

Currently in silicon technology, microprocessor performance is limited by the chip-to-package connections. Three main processes are used for chip-to-package connections, namely Wire Bonding (WB), Tape Automated Bonding (TAB), and controlled collapse chip connection (C4). This C4 technique has many advantages over TAB and WB. One advantage is the high input/output density of the C4 process, which enables the bumps to be placed anywhere on the chip, making it easier to connect the chip to the circuit at these points. In addition, the short solder bumps improve the overall electrical performance and allow for better control of the chip size. Also, the higher I/O density per chip can allow a higher degree of integration at the first package level than end-connected packages such as WB or TAB.

The C4 technique also has a Self-alignment (Self-alignment) feature, whereby the surface tension of the solder allows the solder ball to form a Self-aligned metallurgical bond with the substrate. Which is not possible for WB or TAB.

There are two types of solder bumping processes used in the C4 technology: evaporation and electroplating. The C4 technology was originally developed by IBM to address issues involving manual wire bonding. In implementing the C4 technology, the IBM method utilizes an evaporation process. After the passivation pattern is formed, the evaporation process includes forming a bump metallization bottom (UMB) layer, such as chromium/copper/gold, which is sequentially deposited on the wafer surface through the holes of the metal mask using an evaporator. The chromium layer acts as an adhesion promoter and as a diffusion barrier metal layer which contacts the aluminum-silicon electrical contact pads of the wafer. A copper layer is then deposited on the chromium layer to promote complete wetting of the solder on the electrical contact pads. To prevent oxidation of the copper, a layer of gold is deposited on the copper layer. Finally, Pb/Sn solder is deposited on the metal coated electrical contact pads through the same mask with another evaporator. The wafer including the solder bumps was then placed in a hydrogen atmosphere furnace at a temperature of 365 c for reflow. During reflow, the solder bumps become spherical and wet onto the electrical contact pad surfaces of the wafer. The entire evaporation process was performed in vacuum.

Although evaporation processes are well established, the costs associated with deposition processes are high. In addition, since the thermal expansion coefficient is different between the silicon wafer and the metal mask, it is difficult to control the dimensional accuracy of the solder bump as the size of the wafer increases.

Another method of depositing solder bumps is electroplating. The method includes sputter forming a cladding or Ball Limiting Metallurgy (BLM) layer on a surface of a wafer. In a more general sense, electroplating is the deposition of a metal coating on an electrically conductive object in an electrolytic cell. Using this end as an anode, a DC current is passed through the cell solution, which is capable of transporting metal ions to the cathode surface. In the C4 technique, BLM denotes the cathode surface of the wafer. Once the BLM is formed, a photoresist is coated on the BLM and patterned with a photolithography process to form Vias (Vias). The wafer is then placed in a Pb/Sn electrolytic bath in which Pb/Sn bumps are formed in the vias of the resist pattern. After the resist is stripped, the BLM is selectively etched using the bumps as a mask to electrically isolate the bumps from each other. This electroplating method is problematic because the solder dissolves in almost all acids and is vulnerable to damage from the BLM etching solution. Although this plating process is more convenient and economical than the evaporation method, the etching of the BLM without etching away the solder bumps in implementing the plating process is still a challenge.

Current electroplating processes require a secondary photoresist mask to be formed over the solder bumps to protect the bumps from BLM etching. This method is not suitable for high volume manufacturing because of the increased process cost and reduced quality because of the complexity of obtaining a complete bump coating with a photoresist mask.

What is needed is a way to solve the problems involved in etching BLM in the presence of Pb/Sn bumps. It will be seen that the present invention provides an improved Pb/Sn plating process for forming solder bumps of C4, wherein the ability to etch BLM in the presence of Pb/Sn bumps can be obtained.

Summary of The Invention

An improved method for preparing collapse-controlled die attach (C4) Pb/Sn bumps on a wafer surface is disclosed.

The improved method of fabricating C4 solder bumps on a wafer surface includes a Pb/Sn plating process in which Pb/Sn solder bumps are formed on electrical contact pads of the wafer. Since electroplating requires a conductive surface, the wafer surface is metallized. The metallization layer is generally referred to as a Ball Limiting Metallurgy (BLM) layer and includes a plurality of metal stacks. The BLM serves a secondary purpose by providing suitable metallurgy (properties) between the Pb/Sn bump and the electrical contact pads of the wafer.

In one embodiment of the present invention, the BLM layer comprises two layers: titanium and copper. Titanium forms an inner layer of the BLM layer and covers the electrical contact pads and passivation layer regions of the wafer. Copper is coated on the titanium layer and constitutes the outer surface of the BLM layer.

The vias are formed once the BLM is formed by applying a photoresist to the BLM layer and patterning the resist using a photolithographic process. The wafer is placed in a Pb/Sn electrolytic bath in which Pb/Sn bumps are formed in the passages of the resist pattern. After the resist is stripped, the BLM layer is etched to electrically isolate the bumps from each other. Using a catalyst containing H₂SO₄+H₂O₂+H₂O to remove the outer copper layer of the BLM. While removing the copper layer, H₂SO₄+H₂O₂+H₂The O etchant also reacts with the Pb/Sn bump to form a PbO protective layer on the bump surface. After the copper is etched away, the wafer surface is exposed to CH₃COOH+NH₄F+H₂O etchant, which removes any exposed titanium from the wafer surface. When exposed to CH₃COOH+NH₄F+H₂The PbO layer formed on the surface of the Pb/Sn bump remains undissolved while in the O etchant, thereby preventing the solder bump from dissolving in the presence of CH₃COOH+NH₄F+H₂Is etched in an O etchant. After the etching of the titanium is complete, the bump is etched by exposing the bump to HCl + NH₄CSNH₂+NH₄Cl+H₂And removing the PbO layer from the surface of the Pb/Sn bump in the O solution. The wafer is then passed through a reflow furnace where the Pb/Sn bumps become spherical. Accordingly, the present invention provides a Pb/Sn plating process for forming C4 solder bumps in which the ability to etch BLM in the presence of Pb/Sn bumps is achieved without the need for an additional masking step.

Brief description of the drawings

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 illustrates a cross-sectional view of one embodiment of the present invention after metallization of the wafer substrate and the surface of the electrical contact pads.

Fig. 2 is a cross-sectional view of the embodiment shown in fig. 1 after patterning the resist to form vias.

Fig. 3 is a cross-sectional view of the configuration shown in fig. 2 after Pb/Sn solder bumps are formed on the vias of the resist pattern.

FIG. 4 is a cross-sectional view of the configuration shown in FIG. 3 after the resist has been stripped from the wafer substrate surface.

Fig. 5 is a cross-sectional view of the configuration of fig. 4 after etching the BLM outer layer.

Fig. 6 is a cross-sectional view of the configuration of fig. 5 after etching the BLM inner layer.

Fig. 7 is a cross-sectional view of the configuration shown in fig. 6 after the protective layer has been removed from the Pb/Sn solder bump.

Fig. 8 is a configuration of the wafer substrate, electrical contact pads, metal underlayer, and solder bumps of fig. 7 after reflow.

Detailed description of the preferred embodiments

A method for forming collapse-controlled chip connection (C4) Pb/Sn bumps on a wafer surface is disclosed. In the following description, specific details are set forth, such as material types, dimensions, process steps, etc., in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. On the other hand, well-known elements and process techniques have not been described in particular detail in order to avoid obscuring the present invention.

As previously mentioned, there are two solder formation processes used in the C4 technology: evaporation and electroplating. The invention is particularly applicable to Pb/Sn electroplating processes in which Pb/Sn solder bumps are formed on electrical contact pads of a semiconductor substrate. Since electroplating requires an electrically conductive surface to facilitate the transport of metal ions, the surface of the substrate is metallized. The metallization layer is generally referred to as Ball Limiting Metallurgy (BLM) and typically includes a plurality of metal stacks. The BLM serves a second purpose of providing suitable metallurgical properties between the Pb/Sn solder bump and the electrical pad of the wafer.

Figure 1 shows a substrate 10, electrical contact pads 12, passivation layer 13, and BLM layers 14 and 15 in accordance with one embodiment of the present invention. The substrate 10 represents a cross-section of a semiconductor device. The substrate includes electrical contact pads 12 for coupling the semiconductor device to other external devices. The substrate 10 is made of any temperature-resistant, semiconductor material, such as polysilicon, germanium, and the like. The electrical contact pad 12 represents a typical electrical contact pad that includes an electrically conductive material such as an aluminum/copper alloy. The passivation layer 13 typically comprises a polyamide layer. It should be understood that any dielectric material that provides an electrically insulating layer may be used.

As previously mentioned, this BLM serves two functions: a conductive surface is provided to facilitate the transport of metal ions to the substrate surface during the Pb/Sn solder plating process. And also as an adhesive layer between the electrical contact pads 12 and the solder bumps 17. As shown in fig. 1, in one embodiment, the BLM includes two layers: a first layer 14 comprising titanium and a second layer 15 comprising copper. An inner layer 14 of titanium covers the surfaces of the electrical contact pads 12 and passivation layer 13. Titanium is a very good adhesion metal and adheres well to the aluminum contact pads 12 and the passivation layer 13. But unfortunately titanium does not bond well to lead. Also, titanium does not provide a good diffusion barrier between lead and aluminum. Thus, in the embodiment shown in fig. 1, a copper-containing second layer 15 is coated on the surface of titanium layer 14 to form an outer layer of BLM. Copper is chosen because of its good adhesion to titanium and lead, and because it acts as a good diffusion barrier between lead and aluminum. A titanium layer 14 and a copper layer 15 are formed on the surfaces of the substrate 10 and the electrical contact pads 12 by Physical Vapor Deposition (PVD).

Once layers 14 and 15 are formed, photoresist is applied to the BLM and a resist pattern is formed by a photolithography process to form via 11 (see fig. 2). The substrate is then placed in a Pb/Sn electrolytic bath in which Pb/Sn bumps 17 are formed in the vias 11 of the resist pattern 16.

Once the resist is stripped from the substrate surface (see fig. 4), the BLM layers 14 and 15 must be etched to electrically isolate the Pb/Sn bumps 17 from each other. As previously mentioned, etching the BLM layer without etching away the Pb/Sn solder bumps is still a challenge in implementing the plating process. Current electroplating processes require the formation of a second photoresist mask on the solder bump surface to protect the Pb/Sn solder bump during etching of the BLM. This process is not suitable for mass production because of the increased process cost and reduced quality because it is complicated to completely cover the solder bumps with a photoresist mask. To reduce production costs and increase reliability, the present invention uses a series of process steps to eliminate the need to mask the Pb/Sn solder bumps when etching the BLM layer.

The ability to etch the BLM layers 14 and 15 in the presence of the solder bumps 17 is achieved in the present invention by the selection of the combined etchants. To remove the copper outer layer 15 of the BLM, one embodiment of the present invention is to use a copper containing layer containing H₂SO₄+H₂O₂+H₂An etching solution of O. The H is removed while the exposed portion of the copper layer 15 is removed₂SO₄+H₂O₂+H₂The O etchant also reacts with the Pb/Sn solder bump 17 to form a thin PbO cap layer 18 on the bump surface. (see FIG. 5). The formation of the PbO layer 18 is governed by the following equation: . Exposing the substrate surface to CH when the copper is completely etched₃COOH+NH₄F+H₂O etchant that removes all exposed portions of titanium layer 14 from the surface of substrate 10. When exposed to CH₃COOH+NH₄F+H₂The PbO layer 18 remains insoluble in O etchant, thereby in the presence of CH₃COOH+NH₄F+H₂The O etchant prevents the solder bumps 18 from being etched away. Fig. 6 illustrates a cross-sectional view of the present invention after BLM etching. As shown in fig. 6, when the titanium is completely etched, the layers 14 and 15 are only present under the solder bump 17.

Since the PbO layer 18 reduces solderability of the solder bump 17 to an exposed state, the layer should be removed prior to reflow. Thus, after the titanium is completely etched, the solder bumps are etched by exposing them to HCl + NH₄CSNH₂+NH₄Cl+H₂O solution to remove the PbO layer 18 from the surface of the Pb/Sn bump 17. Fig. 7 shows a cross-sectional view of the invention after removal of the PbO layer 18. After the PbO layer 18 is removed, the substrate 10 is passed through a soft-melting furnace where the Pb/Sn bumps 17 are formed into solder balls 19, as shown in fig. 8.

In one embodiment of the invention, titanium layer 14 and copper layer 15 have thicknesses of about 0.43 and 0.05 microns, respectively. The solder bumps 18 typically contain 97/3 Pb/Sn composition having a melting point of about 315 c. It should be understood that any Pb/Sn composition that does not melt during the plating and etching processes may be used. In an embodiment of a solder bump having a composition of 97/3 Pb/Sn, the reflow oven temperature is set to about 325 deg.C (+ -5 deg.C). The thickness and diameter of the solder bump 17 after the plating process is complete are about 63 and 200 microns, respectively. After reflow, the solder balls 19 are approximately 125 microns in diameter.

In one embodiment of the invention, the H is₂SO₄+H₂O₂+H₂O etchant containing 8 parts of H₂O, 6 parts of H₂SO₄And 1 part of H₂O₂. For this concentration of H₂SO₄+H₂O₂+H₂The time required for the O etchant to etch the copper layer 15 and form the PbO layer 17 is about 3 minutes. CH for titanium etch₃COOH+NH₄F+H₂O etchant solution containing 1 part of CH₃COOH, 1 part NH₄F and 18 parts of H₂And O. For a titanium layer 14 having a thickness of 0.43 microns, the required etch time is about 2 minutes. Final etching of the PbO layer with HCl + NH₂CSNH₂+NH₄Cl+H₂O solution contains 25 parts HCl, 3 parts NH₂CSNH₂25 parts of NH₄Cl and 47 parts of H₂O, the etch time required to remove the PbO layer 18 at room temperature is about 1 minute. The etchant concentration and the etching time are variable to achieve substantially the same results.

In a second embodiment of the invention, a first layer 14 comprising titanium and a second layer 15 comprising nickel are included. With hydrogen containing H₂SO₄+H₂O₂+H₂The etching solution of O removes the nickel outer layer. While removing the exposed portion of the nickel layer 15, H₂SO₄+H₂O₂+H₂The O etchant reacts with the Pb/Sn solder bump 17 in the manner described above to form a PbO layer. After the nickel layer is completely etched, HF + H is used₂The O etchant removes the exposed portion of titanium layer 14, PbO layer 18, after exposure to HF + H₂O etchingRemains insoluble in the agent, thereby preventing the solder bump 17 from being exposed to HF + H₂And O etchant. By exposure to HCH₃SO₃The PbO layer 18 is removed from the surface of the Pb/Sn bump 17 in a (MSA) solution. The removal of the PbO layer 18 from the surface of the solder bump 17 is governed by the following equation:

。

in a second embodiment of the invention, H₂SO₄+H₂O₂+H₂Etchant solution of O containing 8 parts of H₂O, 6 parts of H₂SO₄And 1 part of H₂O₂. For a given such H₂SO₄+H₂O₂+H₂The O etchant concentration, the time required to etch the nickel layer 15 and form the PbO layer 17 was approximately 5 minutes. HF + H for etching titanium layer₂O etchant solution containing 1 part HF and 200 parts H₂And O. For a given titanium layer 14 thickness of 0.43 microns, the required etch time is about 2 minutes. 2HCH for final MSA etch₃SO₃+H₂O solution containing 1 part of 2HCH₃SO₃And 5 parts of H₂O, the etch time required to remove the PbO layer 18 is approximately 3 minutes. It should be noted that the etchant concentration andthe etching time may be varied to obtain substantially the same results.

In the foregoing embodiments of the invention, disclosed are BLM layers 14 having titanium and or BLM layers 15 having copper or nickel. It should be understood that a stack of titanium and copper or titanium and nickel containing BLM metals is not necessary to practice the invention, and the invention is not limited to these two metal layers. The invention can be practiced using only the BLM overcoat etchant which is capable of forming a protective layer on the surface of the solder bumps 17 which either does not penetrate into any subsequent BLM layer etchant or if the protective layer is etched when exposed to the etchant, but during subsequent BLM layer etching. The protective layer has an etch rate that does not substantially etch the solder bumps. By way of example, any metal may be used for layer 15, provided that the metal bonds well to titanium, acts as a good diffusion barrier, and is etched by the solution while forming a protective layer on the surface of solder bump 17. Thus another embodiment of the invention comprises a platinum or palladium containing metal layer 15. Of course, the use of other metal layers requires changes in the etchant concentrations and etching times identified above.

It should be noted that the method of the present invention can be used to form solder connections in other techniques. It is also to be understood that the relative dimensions, geometries, materials, and process parameters set forth above are merely examples of the disclosed embodiments. Other embodiments may use different sizes, shapes, materials, etchant concentrations, and process conditions to achieve substantially the same results.

Claims (28)

1. A method of removing a metal layer from a wafer surface in the presence of a Pb/Sn solder bump, the method comprising the steps of:

(a) removing the first metal layer from the surface of the wafer by exposing the wafer to a first etchant, wherein the first metal layer is removed from the surface of the wafer, and wherein a protective layer is formed over the Pb/Sn solder bump;

(b) removing a second metal layer from the surface of the wafer by exposing the wafer to a second etchant, wherein the second metal layer is removed from the surface of the wafer, and wherein at least a portion of the protective layer remains on the Pb/Sn solder bump surface after exposure to the second etchant;

(c) removing the protective layer from the surface of the Pb/Sn solder bump by exposing the wafer to a third etchant, wherein the protective layer is removed from the Pb/Sn bump.

2. The method of claim 1 wherein said first metal layer comprises copper.

3. The method of claim 1, wherein said first metal layer comprises nickel.

4. The method of claim 1, wherein the first metal layer comprises palladium.

5. The method of claim 1 wherein said first metal layer comprises platinum.

6. The method of claim 1 wherein said second metal layer comprises titanium.

7. The method of claim 1, wherein said first etchant comprises H₂SO₄+H₂O₂+H₂O。

8. The method of claim 1, wherein the second etchant comprises CH₃COOH+NH₄F+H₂O。

9. The method of claim 1, wherein said second etchant comprises HF + H₂O。

10. The method of claim 1, wherein the third etchant comprises HCl + NH₂CSNH₂+NH₄Cl+H₂O。

11. The method of claim 1, wherein the third etchant comprises 2HCH₃SO₃+H₂O。

12. The method of claim 1 wherein said Pb/Sn solder bump comprises 97/3 Pb/Sn.

13. The method of claim 1, wherein the protective layer comprises PbO.

14. A method for removing a spherical limiting metallurgy from a substrate surface in the presence of a Pb/Sn bump, the method comprising the steps of:

(a) exposing the surface of the substrate and the Pb/Sn bump to a first etchant, wherein the first metal layer is removed from the substrate surface and wherein a PbO layer is formed on the surface of the Pb/Sn bump.

(b) Exposing the surface of the substrate and the Pb/Sn bump to a second etchant, wherein a second metal layer is removed from the substrate surface, and wherein at least a portion of the PbO layer remains on the Pb/Sn bump after exposure to the second etchant;

(c) exposing the Pb/Sn bump to a third etchant, wherein the PbO layer is removed from the Pb/Sn bump.

15. The method of claim 14 wherein said first metal layer comprises copper.

16. The method of claim 14, wherein said first metal layer comprises nickel.

17. The method of claim 14, wherein the first metal layer comprises palladium.

18. The method of claim 14 wherein said first metal layer comprises platinum.

19. The method of claim 14 wherein said second metal layer comprises titanium.

20. The method of claim 14, wherein said first etchant comprises H₂SO₄+H₂O₂+H₂O。

21. The method of claim 14, wherein the second etchant comprises CH₃COCH+NH₄F+H₂O。

22. The method of claim 14, wherein said second etchant comprises HF + H₂O。

23. In the application ofThe method of claim 14, wherein the third etchant comprises HCl + NH₂CSNH₂+NH₄Cl+H₂O。

24. The method of claim 14, wherein the third etchant comprises 2HCH₃SO₃+H₂O。

25. The method of claim 14 wherein the Pb/Sn solder bump comprises 97/3 Pb/Sn.

26. A method for removing a spherical limiting metallurgy from a substrate surface in the presence of a Pb/Sn bump, the method comprising the steps of:

(a) exposing the substrate and the Pb/Sn bump to H₂SO₄+H₂O₂+H₂O etchant, wherein a copper layer is removed from the substrate surface, and wherein a PbO layer is formed on the Pb/Sn bump surface;

(b) exposing the substrate and the Pb/Sn bump to CH₃COOH+NH₄F+H₂O etchant, wherein a titanium layer is removed from the substrate surface, and wherein the titanium layer is exposed to the CH₃COOH+NH₄F+H₂At least a portion of the PbO layer remains on the Pb/Sn bump after being exposed to an O etchant;

(c) exposing the Pb/Sn bump to HCl + NH₂CSNH₂+NH₄Cl+H₂O solution, wherein the PbO layer is removed from the Pb/Sn bump.

27. A method for removing a spherical limiting metallurgy from a substrate surface in the presence of a Pb/Sn bump, the method comprising the steps of:

(a) exposing the substrate and the Pb/Sn bump to H₂SO₄+H₂O₂+H₂O etchant, wherein a copper layer is removed from the substrate surface, and wherein a PbO layer is formed on the Pb/Sn bump surface;

(b) exposing the substrate and the Pb/Sn bump to HF + H₂O etchant, wherein a titanium layer is removed from the substrate surface, and wherein the titanium layer is exposed to the HF + H₂At least a portion of the PbO layer remains on the Pb/Sn bump after being exposed to an O etchant;

(c) exposing the Pb/Sn bump to 2HCH₃SO₃+H₂O solution, wherein the PbO layer is removed from the Pb/Sn bump.

28. A method for removing a spherical limiting metallurgy from a substrate surface in the presence of a Pb/Sn bump, the method comprising the steps of:

(a) exposing the surface of the substrate and the Pb/Sn bump to a first etchant, wherein the first metal layer is removed from the substrate surface and wherein a PbO layer is formed on the surface of the Pb/Sn bump.

(b) Exposing the surface of the substrate and the Pb/Sn bump to a second etchant, wherein the second metal layer is removed from the surface of the substrate and the protective layer is removed from the Pb/Sn bump such that the Pb/Sn bump is not substantially etched.

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