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CN113990922A - Semiconductor longitudinal device and production method thereof - Google Patents

Semiconductor longitudinal device and production method thereof Download PDF

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Publication number
CN113990922A
CN113990922A CN202111213878.XA CN202111213878A CN113990922A CN 113990922 A CN113990922 A CN 113990922A CN 202111213878 A CN202111213878 A CN 202111213878A CN 113990922 A CN113990922 A CN 113990922A
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region
heavily doped
gate electrode
doped region
conductive type
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CN113990922B (en
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姜春亮
李伟聪
雷秀芳
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Vanguard Semiconductor Co Ltd
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Vanguard Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a semiconductor longitudinal device and a production method thereof, wherein a device main body part of the semiconductor longitudinal device is sequentially divided into a first conductive type heavily doped region, a second conductive type lightly doped region and a first conductive type drift region, and a deep groove is concavely arranged on the device main body part so as to respectively place a control gate electrode and a shielding gate electrode in an insulating manner; the resistor control grid is arranged in the shallow groove in an insulating mode, the resistor control grid is arranged on the shallow groove, the resistor control grid is arranged in the shallow groove in a spaced mode, and the resistor control grid is used for controlling the characteristics of the resistor area. The temperature coefficient of the punch-through breakdown voltage of the existing power semiconductor longitudinal device can be effectively reduced, and the whole power consumption of the device during working is low.

Description

Semiconductor longitudinal device and production method thereof
Technical Field
The application relates to the technical field of power semiconductors, in particular to a semiconductor longitudinal device and a production method thereof.
Background
Power Semiconductor vertical devices such as Shield-gate trench-Semiconductor Field Effect transistors (SGT-MOSFETs) operate in a severe temperature environment, the punch-through breakdown voltage of the power Semiconductor vertical devices is greatly affected by temperature, and the devices have a large positive temperature coefficient (i.e., the temperature of the punch-through breakdown voltage of the devices gradually increases with the increase of current), so that the devices have temperature-dependent instability problems, which will seriously affect the reliability of the power Semiconductor vertical devices. In the prior art, a common method is to compensate the temperature coefficient of the punch-through breakdown voltage of the device by building an external circuit so as to ensure that the device has the punch-through breakdown voltage with zero temperature coefficient when in use, but the built external circuit not only has a complex structure, but also can increase the overall power consumption of the device during operation.
Disclosure of Invention
The embodiment of the application provides a semiconductor longitudinal device and a production method thereof, and aims to solve the problems that the structure is complex and the overall power consumption of the device during working is increased when the conventional power semiconductor longitudinal device is used for compensating the temperature coefficient of the punch-through breakdown voltage of the device by building an external circuit.
In a first aspect, the present application provides a semiconductor vertical device comprising a first conductivity type substrate, a device body portion, a metalized drain, a metalized source, a control gate electrode, a shield gate electrode, and a resistive control gate;
the bottom end of the device main body part is sequentially covered with the first conductive type substrate and the metalized drain, and the top end of the device main body part is covered with the metalized source;
the device main body part is sequentially divided into a first conductive type heavily doped region, a second conductive type lightly doped region and a first conductive type drift region from top to bottom, and a deep groove is concavely arranged at the top end of the device main body part so as to respectively place the control gate electrode and the shielding gate electrode in an insulating manner;
the resistor control grid comprises a first conductive type heavily doped region, a second conductive type heavily doped region, a shallow groove, a resistor region and a resistor control grid, wherein a gap is formed in a region on one side of the top layer of the first conductive type heavily doped region, the gap is filled with the second conductive type heavily doped region, the region on the other side of the top layer of the first conductive type heavily doped region is concavely arranged to form the shallow groove, the second conductive type heavily doped region is tightly attached to the deep groove, the shallow groove is located in a region on the outer side of the top layer of the first conductive type heavily doped region, a preset distance is arranged between the shallow groove and the second conductive type heavily doped region at intervals to form the resistor region between the shallow groove and the second conductive type heavily doped region, and the resistor control grid for controlling the characteristics of the resistor region is arranged in an insulating mode in the shallow groove.
Optionally, the first conductive type substrate is a heavily doped first conductive type substrate, and the first conductive type drift region is a lightly doped first conductive type drift region.
Optionally, the deep trench divides the first conductive type heavily doped region into a first heavily doped half region and a second heavily doped half region, divides the second conductive type lightly doped region into a first lightly doped half region and a second lightly doped half region, and forms a U-shaped trench region at the top end of the first conductive type drift region in sequence from top to bottom.
Optionally, one side region of the top layer of the first heavily doped half region is provided with one notch, one notch is filled with one second conductivity type heavily doped region, the other side region of the top layer of the first heavily doped half region is concavely provided with one shallow trench, the second conductivity type heavily doped region is arranged to be tightly attached to the deep trench, a preset distance is arranged between the shallow trench and the second conductivity type heavily doped region to form one resistor region therebetween, and one resistor control gate for controlling the characteristic of the resistor region is arranged in the shallow trench in an insulating manner.
Optionally, another gap is formed in a region on one side of the top layer of the second heavily doped half region, another gap is filled with another heavily doped region of the second conductivity type, another shallow trench is concavely formed in a region on the other side of the top layer of the second heavily doped half region, the another heavily doped region of the second conductivity type is arranged to be close to the deep trench, a preset distance is arranged between the another shallow trench and the another heavily doped region of the second conductivity type to form another resistor region therebetween, and another resistor control gate for controlling the characteristic of the another resistor region is placed in the another shallow trench in an insulating manner.
Optionally, the shield gate electrode is disposed in a U-shaped groove region of the deep groove, and an insulating layer is interposed between the shield gate electrode and an inner wall of the U-shaped groove region, so that the shield gate electrode is disposed in the deep groove in an insulating manner.
Optionally, the control gate electrode is disposed in the deep trench, and the control gate electrode is located above the shield gate electrode, and the insulating layers are respectively interposed between the bottom end of the control gate electrode and the shield gate electrode, between the top end of the control gate electrode and the metalized source, and between the sidewall of the control gate electrode and the inner wall of the deep trench, so that the control gate electrode is disposed in the deep trench in an insulating manner.
Optionally, a bottom end of the control gate electrode extends into the U-shaped trench region.
Optionally, a top end of the control gate electrode is higher than a top end of the second conductive type lightly doped region.
Optionally, insulating dielectric layers are respectively sandwiched between the resistance control gate and the inner wall of the adjacent shallow trench and between the resistance control gate and the adjacent metalized source.
Optionally, the first conductivity type is P-type, and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type.
In a second aspect, the present application provides a method for producing a semiconductor vertical device, comprising the steps of:
providing a single crystal semiconductor substrate, wherein the single crystal semiconductor substrate is used as a first conductive type substrate, and epitaxial growth is carried out on the top side of the semiconductor substrate to form a device main body part;
etching the device main body part to form a deep groove inwards at the top end of the device main body part;
depositing and etching a polycrystalline semiconductor for multiple times in the deep groove to form a shielding gate electrode and a control gate electrode which are arranged in an insulating manner in the deep groove respectively;
different regions of the device main body part are subjected to different ion implantation, so that the device main body part is sequentially divided into a first conduction type heavily doped region, a second conduction type lightly doped region and a first conduction type drift region from top to bottom, meanwhile, a gap is formed in a region on one side of the top layer of the first conduction type heavily doped region, the gap is filled with the second conduction type heavily doped region, and the second conduction type heavily doped region is tightly attached to the deep groove;
etching the other side region of the top layer of the first conductive type heavily doped region to form a shallow trench in a concave manner in the other side region of the top layer of the first conductive type heavily doped region, and meanwhile, a preset distance is arranged between the shallow trench and the second conductive type heavily doped region to form a resistor region between the shallow trench and the second conductive type heavily doped region;
depositing and etching a polycrystalline semiconductor in the shallow trench to form an insulated resistance control grid for controlling the characteristics of the resistance area in the shallow trench;
and carrying out metallization processing on the top end of the device main body part and the bottom end of the single crystal semiconductor substrate so as to form a metalized source electrode on the top end of the device main body part and a metalized drain electrode on the bottom end of the single crystal semiconductor substrate, and thus obtaining the semiconductor vertical device.
Optionally, the depositing and etching of the polycrystalline semiconductor in the deep trench to form the shield gate electrode and the control gate electrode which are placed in an insulated manner in the deep trench specifically includes:
carrying out first thermal growth of an oxidation material in the deep groove to form a first oxidation layer in a first preset region on the inner wall of the deep groove;
carrying out first deposition and etching of a polycrystalline semiconductor in the deep groove to form a shielding gate electrode, wherein the first oxidation layer is clamped between the inner wall of the deep groove and the shielding gate electrode;
performing first deposition of an oxide material in the deep trench to deposit a second oxide layer with a preset thickness on the top end of the shielding gate electrode;
carrying out second thermal growth of an oxidation material in the deep groove to form a third oxidation layer on the inner wall of the deep groove;
carrying out second deposition and etching on a polycrystalline semiconductor in the deep trench to form a control gate electrode, wherein the second oxide layer is clamped between the top end of the shielding gate electrode and the bottom end of the control gate electrode, and the third oxide layer is clamped between the inner wall of the deep trench and the control gate electrode;
and carrying out second deposition of an oxidation material in the deep groove so as to deposit a fourth oxidation layer with a preset thickness at the top end of the control gate electrode.
Optionally, the performing different ion implantations on different regions of the device main body portion makes the device main body portion sequentially divided into a first conductive type heavily doped region, a second conductive type lightly doped region and a first conductive type drift region from top to bottom, and meanwhile, a region on one side of a top layer of the first conductive type heavily doped region is provided with a notch, the notch is filled with the second conductive type heavily doped region, and the step of setting the second conductive type heavily doped region in close proximity to the deep trench specifically includes:
performing no ion implantation in a lower portion of the device body portion to form the first conductivity type drift region;
implanting first ions into the middle of the device main body part to form the second conductive type lightly doped region;
injecting second ions into a first preset region on the upper part of the device main body part to form the first conduction type heavily doped region;
and injecting third ions into a second preset region on the upper part of the device main body part to form the second conductive type heavily doped region.
Optionally, the depositing and etching of the polycrystalline semiconductor in the shallow trench to form an insulated resistance control gate for controlling the characteristic of the resistance region in the shallow trench specifically includes:
carrying out thermal growth of an oxidation material in the shallow trench to form a fifth oxidation layer on the inner wall of the shallow trench;
depositing and etching a polycrystalline semiconductor in the shallow trench to form a resistance control grid, wherein the fifth oxidation layer is clamped between the inner wall of the shallow trench and the resistance control grid;
and depositing an oxidation material in the shallow trench to deposit a sixth oxidation layer with a preset thickness on the top end of the resistance control grid.
In the application, the connection mode of the electrodes of the semiconductor longitudinal device during reverse voltage withstanding is that the resistance control grid is connected with a positive potential according to the application, the control grid electrode, the shielding grid electrode and the metalized source are in short circuit and connected with a zero potential, and the metalized drain is connected with a negative potential. When the control gate electrode is zero-biased, the inversion layer channel does not exist in the second conduction type lightly doped region, and the conduction path of the multi-sub-hole is pinched off. When the reverse voltage on the metalized drain electrode is increased, the boundary of the depletion layer simultaneously expands towards the two sides of the first conduction type drift region and the second conduction type lightly doped region to bear the reverse voltage until the device is subjected to punch-through breakdown when the boundary of the depletion region in the second conduction type lightly doped region reaches the vicinity of the interface of the second conduction type lightly doped region and the first conduction type heavily doped region. At this time, due to the introduction of the resistance region, when the semiconductor longitudinal device is reverse voltage-resistant, the internal potential between the second conductivity type heavily doped region and the first conductivity type heavily doped region is reduced along with the temperature rise, so that the depletion region generated by the PN junction formed between the second conductivity type heavily doped region and the first conductivity type heavily doped region is reduced, the resistance control gate can be connected with zero potential, positive potential or negative potential to adjust the width of the depletion region in the resistance region, accurately control the resistance value of the resistance region (reduce the resistance value of the resistance region as much as possible), further control the compensation degree of the resistance region on the punch-through voltage temperature coefficient of the SGT-MOSFET, finally make the punch-through voltage temperature coefficient of the semiconductor longitudinal device extremely small, even if the semiconductor longitudinal device does not need to build an external circuit to reduce the temperature coefficient of the punch-through breakdown voltage, the punch-through breakdown voltage is basically unchanged along with the temperature change, so that the structure of the semiconductor longitudinal device is simplified, and the overall power consumption of the device during working is reduced. Therefore, the temperature coefficient of the punch-through breakdown voltage of the conventional power semiconductor longitudinal device can be effectively reduced on the basis of the SGT-MOSFET structure, so that the reliability of the power semiconductor longitudinal device such as the SGT-MOSFET in application is improved, the structure is simple, and the overall power consumption of the device during working is low.
Drawings
The technical solutions and advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor vertical device provided in an embodiment of the present application.
Fig. 2 is a graph of simulation of punch-through breakdown voltage of conventional SGT-MOSFET devices as a function of temperature at temperatures of 300K, 350K, 400K.
Fig. 3 is a graph of simulation of punch-through breakdown voltage of the semiconductor vertical device shown in fig. 1 as a function of temperature at temperatures of 300K, 350K, and 400K.
Fig. 4 is a flow chart of a method for producing a semiconductor vertical device according to an embodiment of the present disclosure.
Fig. 5-1 to 5-10 are schematic views showing changes in the state of the manufacturing process of the semiconductor vertical device manufactured by the manufacturing method shown in fig. 4.
Fig. 6 is a block diagram showing a specific flow of step S130 in the manufacturing method shown in fig. 4.
Fig. 7 is a block diagram showing a specific flow of step S140 in the manufacturing method shown in fig. 4.
Fig. 8 is a block diagram showing a specific flow of step S160 in the manufacturing method shown in fig. 4.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
A power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a multi-sub conductive device, and has the advantages of high switching speed, high input impedance, easy driving, and the like. To further improve the performance of power MOSFETs, SGT structures are proposed. Compared with a traditional Trench Metal-Oxide-Semiconductor Field Effect Transistor (Trench-MOSFET) device, the SGT-MOSFET device has a deeper Trench, the overlapping area of the capacitor between the grid and the drain is greatly reduced through a special Field plate structure, the grid leakage capacitor is reduced, the device has lower grid charges, the switching speed of the working power MOSFET can be increased, the switching loss is reduced, and the concept of building a resource-saving and environment-friendly society in the current era is met.
Power semiconductor vertical devices such as SGT-MOSFETs, which operate in a severe temperature environment, have a large temperature-dependent punch-through breakdown voltage, have a large positive temperature coefficient (i.e. the temperature of the punch-through breakdown voltage of the device gradually increases with increasing current), resulting in temperature-dependent instability of the device, which will seriously affect the reliability of these power semiconductor vertical devices, and at the same time, because the temperature coefficient of the punch-through breakdown voltage of the power semiconductor vertical device is mainly determined by the material characteristics of the device and is difficult to improve in a simple manner, this will make the device face a severe reliability challenge.
The breakdown characteristics of punch-through breakdown make the breakdown voltage temperature coefficient of punch-through breakdown devices more easily compensated than avalanche breakdown. The above problems are solved if a structure can be introduced into such a device such that the temperature coefficient of the punch-through breakdown voltage of the device is very small and the punch-through breakdown voltage is substantially constant with temperature.
Based on this, in one embodiment, as shown in fig. 1, the present embodiment provides a semiconductor vertical device 100, the semiconductor vertical device 100 including a first conductivity type substrate 110, a device main body portion 120, a metalized drain 130, a metalized source 140, a control gate electrode 150, a shield gate electrode 160, and a resistance control gate 170. The bottom of the device body 120 is sequentially covered with the first conductive type substrate 110 and the metalized drain 130, and the top of the device body 120 is covered with the metalized source 140. The device body 120 is sequentially divided into a first conductive type heavily doped region 121, a second conductive type lightly doped region 122 and a first conductive type drift region 123 from top to bottom, and a deep trench (not shown) is recessed at the top end of the device body 121 to separately place the control gate electrode 150 and the shield gate electrode 160 in an insulating manner. A notch (not shown) is formed in a region on one side of the top layer of the first-conductivity-type heavily doped region 121, the notch is filled with the second-conductivity-type heavily doped region 124, a shallow trench (not shown) is concavely formed in a region on the other side of the top layer of the first-conductivity-type heavily doped region 121, the second-conductivity-type heavily doped region 124 is tightly attached to the deep trench, the shallow trench is located in a region on the outer side of the top layer of the first-conductivity-type heavily doped region 121, a preset distance is formed between the shallow trench and the second-conductivity-type heavily doped region 124 to form a resistor region (not shown) therebetween, and a resistor control gate 170 for controlling the characteristics of the resistor region is placed in the shallow trench in an insulating manner.
It should be noted that the semiconductor vertical device 100 in this embodiment may be a P-channel SGT-MOSFET device, and may also be an N-channel SGT-MOSFET device. When the semiconductor vertical device 100 is a P-channel SGT-MOSFET device, the first conductivity type mentioned above is P-type, and the second conductivity type is N-type. When the semiconductor vertical device 100 is an N-channel SGT-MOSFET device, the first conductivity type mentioned above is N-type, and the second conductivity type is P-type.
In some examples, the above-mentioned first conductive type substrate 110 is preferably a heavily doped first conductive type substrate, and the above-mentioned first conductive type drift region 123 is preferably a lightly doped first conductive type drift region.
The operation principle of the SGT-MOSFET device with P-channel, in which the semiconductor vertical device 100 is a P-channel, will be described in detail below by taking the SGT-MOSFET device with P-channel as an example. At this time, the first conductive type substrate 110 is a P + substrate, the first conductive type heavily doped region 121 is a P + doped region, the second conductive type lightly doped region 122 is an N-doped region, the first conductive type drift region 123 is a P-drift region, and the second conductive type heavily doped region 124 is an N + doped region. The doping concentration of the P-drift region in this embodiment is preferably 7.5 × 1015cm-3The doping concentration of the N-doped region is preferably 2.56X 1016cm-3The doping concentration of the P + doped region is preferably 6.8 × 1017cm-3The doping concentration of the N + doping region is preferably 6X 1019cm-3。
When the semiconductor vertical device 100 is conducted in the forward direction, the electrode connection mode is as follows: the control gate electrode 150 and the resistance control gate 170 are connected to the same negative potential, the metalized drain 130 is connected to the negative potential, and the metalized source 140 and the shield gate electrode 160 are connected to zero potential. At this time, when the negative voltage applied on the control gate electrode 150 reaches the threshold voltage of the device, an inversion layer channel is formed in the N-doped region (i.e., the second conductive type lightly doped region 122) on the side close to the deep trench, a multi-sub hole accumulation layer is formed in the P + doped region (i.e., the first conductive type heavily doped region 121) on the side close to the deep trench, and under the reverse bias of the metalized drain 130, holes are used as carriers to inject the P-drift region (i.e., the first conductive type drift region 123) from the P + doped region (i.e., the first conductive type heavily doped region 121) through the inversion layer channel in the N-doped region (i.e., the second conductive type lightly doped region 122) and reach the metalized drain 130 to form a forward current, so that the semiconductor vertical device 100 is turned on. At this time, the resistance control gate 170 is connected to the same negative potential as the control gate electrode 150, so that an accumulation layer can be formed in the resistance region, thereby effectively reducing the resistance of the resistance region.
When the semiconductor vertical device 100 is reversely blocked, the electrode connection mode is as follows: the resistive control gate 170 is connected to a positive potential, the control gate electrode 150, the shield gate electrode 160, and the metalized source 160 are shorted and connected to a zero potential, and the metalized drain 130 is connected to a negative potential, depending on the application. At this time, since there is no inversion layer channel in the N-doped region (i.e., the second conductive type lightly doped region 122) when the control gate electrode 150 is zero-biased, the conduction path of the majority hole is pinched off. When the reverse voltage on the metalized drain 130 is increased, the depletion layer boundary will expand towards both sides of the P-drift region (i.e., the drift region 123 of the first conductivity type) and the N-doped region (i.e., the lightly doped region 122 of the second conductivity type) to withstand the reverse voltage, until the punch-through breakdown of the device occurs when the boundary of the depletion region in the N-doped region (i.e., the lightly doped region 122 of the second conductivity type) reaches the vicinity of the interface between the N-doped region (i.e., the lightly doped region 122 of the second conductivity type) and the P + doped region (i.e., the heavily doped region 121 of the first conductivity type). At this time, due to the introduction of the resistance region, when the semiconductor longitudinal device 100 is reverse voltage-resistant, the internal potential between the N + doped region (i.e., the second conductivity type heavily doped region 124) and the P + doped region (i.e., the first conductivity type heavily doped region 121) decreases with the increase of temperature, so that the depletion region generated by the PN junction formed between the N + doped region (i.e., the second conductivity type heavily doped region 124) and the P + doped region (i.e., the first conductivity type heavily doped region 121) decreases, the resistance control gate can be connected to a zero potential, a positive potential or a negative potential to adjust the width of the depletion region in the resistance region, precisely control the resistance value of the resistance region (so that the resistance value of the resistance region decreases as much as possible), further control the compensation degree of the resistance region for the punch-through voltage temperature coefficient of the SGT-MOSFET, and finally make the punch-through voltage temperature coefficient of the semiconductor longitudinal device 100 extremely small, namely, the temperature coefficient of the punch-through breakdown voltage of the semiconductor longitudinal device 100 can be reduced without building an external circuit, the punch-through breakdown voltage is basically unchanged along with the temperature change, the structure of the semiconductor longitudinal device 100 is simplified, and the overall power consumption of the device during working is reduced.
Under the withstand voltage of about-60V, the temperature coefficient of the punch-through breakdown voltage of the traditional SGT-MOSFET device is about 35mV/K, the temperatures of 300K, 350K and 400K are respectively selected, and the curves of the punch-through breakdown voltage along with the temperature change are respectively shown in FIG. 2. Meanwhile, the semiconductor vertical device 100 of the present embodiment is optimized based on an SGT-MOSFET device (the cell width is preferably 3.4 μm, the width of the deep trench is preferably 1 μm, the depth of the deep trench is preferably 2.8 μm, the width of the shallow trench is preferably 0.3 μm, the depth of the shallow trench is preferably 0.25 μm, the dielectric filled in the trench is silicon dioxide, the width of the resistive region is preferably 0.03 μm, the semiconductor used is monocrystalline silicon, when the reverse voltage resistance is achieved, the metalized source 140 is connected to zero potential, the control gate electrode 150 is connected to zero potential, and the resistive control gate 170 is connected to-0.5V), the temperatures of 300K, 350K and 400K are also selected respectively, the curves of the punch-through breakdown voltage along with the temperature change are respectively shown in fig. 3, and the temperature coefficient is 4 mV/K. It can be seen that the present semiconductor vertical device 100 can effectively reduce the temperature coefficient of the punch-through breakdown voltage of the existing power semiconductor vertical device such as SGT-MOSFET.
Therefore, in the present embodiment, the semiconductor vertical device 100 provided therein can effectively reduce the temperature coefficient of the punch-through breakdown voltage of the conventional power semiconductor vertical device on the basis of the SGT-MOSFET structure, so as to increase the reliability of the power semiconductor vertical device such as the SGT-MOSFET in application, and has a simple structure and lower overall power consumption when the device operates.
In some examples, as shown in fig. 1, the deep trench divides the heavily doped region 121 of the first conductivity type into a heavily doped half region and a heavily doped half region, divides the lightly doped region 122 of the second conductivity type into a lightly doped half region and a lightly doped half region, and forms a U-shaped trench region at the top of the drift region 123 of the first conductivity type sequentially from top to bottom. Meanwhile, a gap is formed in one side region of the top layer of the first heavily doped half region, the second conductive type heavily doped region 124 is filled in the gap, a shallow trench is formed in a concave manner in the other side region of the top layer of the first heavily doped half region, the second conductive type heavily doped region 124 is arranged in a manner of being tightly attached to the deep trench, a preset distance is formed between the shallow trench and the second conductive type heavily doped region 124 so as to form a resistance region between the shallow trench and the second conductive type heavily doped region, and a resistance control grid 170 for controlling the characteristics of the resistance region is arranged in an insulating manner in the shallow trench. Another gap is formed in a region on one side of the top layer of the second heavily doped half region, another second conductive type heavily doped region 124 is filled in the another gap, another shallow trench is formed in a concave manner in the region on the other side of the top layer of the second heavily doped half region, the another second conductive type heavily doped region 124 is arranged in a manner of being tightly attached to the deep trench, a preset distance is formed between the another shallow trench and the another second conductive type heavily doped region 124 so as to form another resistance region therebetween, and another resistance control gate 170 for controlling the characteristics of the another resistance region is placed in the another shallow trench in an insulating manner. By the structural arrangement, the semiconductor vertical device 100 can integrally form a left-right symmetrical structure, and the stability of the semiconductor vertical device is improved.
In some examples, as shown in fig. 1, the shield gate electrode 160 mentioned above is disposed in a U-shaped trench region of the deep trench, and an insulating layer 180 is sandwiched between the shield gate electrode 160 and an inner wall of the U-shaped trench region, so that the shield gate electrode 160 is disposed in the deep trench in an insulated manner. Meanwhile, the control gate electrode 150 is disposed in the deep trench, the control gate electrode 150 is disposed above the shielding gate electrode 160, and insulating layers 180 are respectively interposed between the bottom end of the control gate electrode 150 and the shielding gate electrode 160, between the top end of the control gate electrode 150 and the metalized source 140, and between the sidewall of the control gate electrode 150 and the inner wall of the deep trench, so that the control gate electrode 150 is disposed in the deep trench in an insulating manner. The insulating layer 180 of the present embodiment is specifically an oxide layer, and the oxide layer can perform a good insulating function between the two layers. The oxide layer may be thermally grown from silicon dioxide (SiO 2), silicon oxynitride (SiON), or other materials.
In some examples, as shown in fig. 1, the bottom end of the above-mentioned control gate electrode 150 extends into the U-shaped trench region, so that the bottom vertical depth of the second conductivity type lightly doped region 122 is higher than the bottom vertical depth of the control gate electrode 150, which can ensure that an inversion layer channel communicating between the first conductivity type drift region 123 and the first conductivity type heavily doped region 121 can be formed at the side of the second conductivity type lightly doped region 122 close to the oxide layer 180 when the present semiconductor vertical device 100 is in forward conduction.
In some examples, as shown in fig. 1, the top end of the above-mentioned control gate electrode 150 is preferably higher than the top ends of the second conductive type lightly doped regions 122 at the left and right sides, so that the control gate electrode 150 sequentially covers a portion of the first conductive type heavily doped region 121, a portion of the second conductive type lightly doped region 122 and a portion of the first conductive type drift region 123 in a vertical direction for realizing a control function of the device switch.
In some examples, as shown in fig. 1, an insulating dielectric layer 170 is sandwiched between the resistance control gate 170 and the inner wall of the adjacent shallow trench and the adjacent metalized source 140. The insulating dielectric layer 170 of this embodiment is specifically an oxide layer, and the oxide layer can perform a good insulating and isolating function between the two layers. The oxide layer may be thermally grown from silicon dioxide (SiO 2), silicon oxynitride (SiON), or other materials.
In one embodiment, as shown in fig. 4, the present embodiment provides a method for manufacturing a semiconductor vertical device, specifically including the steps of:
step S110: a single crystal semiconductor substrate is provided as a first conductivity type substrate, and epitaxial growth is performed on the top side of the semiconductor substrate to form a device body portion.
Specifically, the method for producing the semiconductor vertical device in the present embodiment is mainly used for producing the semiconductor vertical device 100 in the above-described embodiment. As can be seen from the above description, the semiconductor vertical device 100 may be a P-channel SGT-MOSFET device, or may be an N-channel SGT-MOSFET device. When the semiconductor vertical device 100 is a P-channel SGT-MOSFET device, the first conductivity type mentioned above is P-type, and the second conductivity type is N-type. When the semiconductor vertical device 100 is an N-channel SGT-MOSFET device, the first conductivity type mentioned above is N-type, and the second conductivity type is P-type.
It should be noted that the semiconductor in this embodiment may be bulk silicon, or may be a semiconductor material such as silicon carbide, gallium arsenide, or germanium silicon. Each method step of the method for producing a semiconductor vertical device in this embodiment is further described in detail by taking a semiconductor as bulk silicon, and taking a produced semiconductor vertical device as an SGT-MOSFET device with a P-channel as an example.
As shown in fig. 5-1, the single crystal semiconductor substrate provided in the steps of the method may be a heavily doped single crystal silicon substrate with a crystal orientation of <100>, the heavily doped single crystal silicon substrate is a P + substrate 210 (i.e., a heavily doped substrate of a first conductivity type), and at the same time, epitaxial growth is performed on the top side of the heavily doped single crystal silicon substrate, and a device body 220 with a certain thickness and doping concentration may be grown by methods such as vapor phase epitaxy VPE (at this time, all regions of the device body 220 are P-drift regions)
Step S120: and etching the device main body part to form a deep groove inwards at the top end of the device main body part.
Specifically, as shown in fig. 5-2, the device main body 220 is etched, a hard mask (e.g., silicon nitride) 20 is deposited on the top end of the device main body 220 to serve as a barrier layer for subsequent trench digging, and a photolithography plate is used to perform deep trench etching, so as to form a deep trench 21 (i.e., a trench gate region) at the top end of the device main body by recessing inward, wherein the specific etching process may use reactive ion etching or plasma etching. After the deep trench 21 is etched, the hard mask 20 is removed.
Step S130: and depositing and etching the polycrystalline semiconductor for multiple times in the deep groove to respectively form a shielding gate electrode and a control gate electrode which are arranged in an insulating way in the deep groove.
Specifically, the polycrystalline semiconductor in the steps of the method may be polysilicon, and multiple depositions and etches of polysilicon are performed in the deep trench 21 to form a shield gate electrode and a control gate electrode, respectively. In order to isolate the shield gate electrode and the control gate electrode in the deep trench 21 from each other and to isolate the shield gate electrode and the control gate electrode from the device main body portion 220, an oxide layer is further formed in the deep trench 21. The oxide layer may be thermally grown from silicon dioxide (SiO 2), silicon oxynitride (SiON), or other materials, and silicon dioxide is preferably used in this embodiment.
Thus, in some examples, as shown in fig. 6, the method step "performing multiple depositions and etches of polycrystalline semiconductor in the deep trench to form the shield gate electrode and the control gate electrode respectively" is performed as follows:
step S131: and carrying out first thermal growth of an oxidation material in the deep trench to form a first oxidation layer in a first preset region on the inner wall of the deep trench.
Specifically, as shown in fig. 5-3, after the hard mask 20 is removed, a first thermal growth of an oxide material (specifically, silicon dioxide) is performed in the deep trench 21 to form a first oxide layer 281 (specifically, a silicon dioxide layer) in a first predetermined region on the inner wall of the deep trench 21.
Step S132: and carrying out first deposition and etching of a polycrystalline semiconductor in the deep trench to form a shielding gate electrode, wherein the first oxide layer is clamped between the inner wall of the deep trench and the shielding gate electrode.
Specifically, as shown in fig. 5-3, after a first oxide layer 281 is formed in a first predetermined region on an inner wall of the deep trench 21, a first deposition and etching of a polycrystalline semiconductor (specifically, polysilicon) is performed in the deep trench 21 to form a shield gate electrode 260, and the first oxide layer 281 is sandwiched between the inner wall of the deep trench 21 and the shield gate electrode 260, so that the two are isolated and insulated from each other.
Step S133: a first deposition of an oxide material is performed within the deep trench to deposit a second oxide layer of a predetermined thickness on top of the shield gate electrode.
Specifically, as shown in fig. 5-4, after forming the shield gate electrode 260 within the deep trench 21, a first deposition of an oxide material (specifically, silicon dioxide) is performed within the deep trench 21 to deposit a second oxide layer 282 (specifically, a silicon dioxide layer) of a predetermined thickness on top of the shield gate electrode 260.
It should be noted that there is no clear boundary between the second oxide layer 282 and the first oxide layer 281 on both sides of the shield gate electrode 260, and if it is hard to distinguish the two, it can also be said that the second oxide layer 282 covers the top side of the first oxide layer 281 on both sides of the shield gate electrode 260.
Step S134: and carrying out second thermal growth of an oxidation material in the deep groove to form a third oxidation layer on the inner wall of the deep groove.
Specifically, as shown in fig. 5-5, after depositing a second oxide layer 282 with a predetermined thickness on top of the shield gate electrode 260, a second thermal growth of an oxide material (specifically, silicon dioxide) is performed in the deep trench 21 to form a third oxide layer 283 (specifically, a silicon dioxide layer) on the inner wall of the deep trench 21.
It should be noted that there is also no clear boundary between the third oxide layer 283 and the second oxide layer 282, and the third oxide layer 283 may be thermally grown to diffuse around the opening of the deep trench 21, such that the top side of the device body 220 is also covered with the third oxide layer 283.
Step S135: and carrying out second deposition and etching on the polycrystalline semiconductor in the deep trench to form a control gate electrode, wherein the second oxide layer is clamped between the top end of the shielding gate electrode and the bottom end of the control gate electrode, and the third oxide layer is clamped between the inner wall of the deep trench and the control gate electrode.
Specifically, as shown in fig. 5 to 6, after a third oxide layer 283 is formed on the inner wall of the deep trench 21, a second deposition and etching of a polycrystalline semiconductor (specifically, polysilicon) is performed in the deep trench 21 to form a control gate electrode 250, the second oxide layer 282 is sandwiched between the top end of the shield gate electrode 260 and the bottom end of the control gate electrode 250, and the third oxide layer 283 is sandwiched between the inner wall of the deep trench 260 and the control gate electrode 250.
Step S136: and performing second deposition of an oxidation material in the deep trench to deposit a fourth oxidation layer with a preset thickness at the top end of the control gate electrode.
Specifically, as shown in fig. 5-6, after the control gate electrode 250 is formed in the deep trench 21, the second deposition of the oxide material (specifically, silicon dioxide) may be directly performed in the deep trench 21, so as to deposit a fourth oxide layer 284 (specifically, a silicon dioxide layer) with a predetermined thickness on the top of the control gate electrode 250. After the next step S140 or the next step 150 is completed, a second deposition of an oxide material (specifically, silicon dioxide) may be performed in the deep trench 21 to deposit a fourth oxide layer 284 (specifically, a silicon dioxide layer) with a predetermined thickness on the top of the control gate electrode 250, which only needs to be ensured that the timing of the method step is before the step S170. After depositing the fourth oxide layer 284 with a predetermined thickness on the top of the control gate electrode 250, the excess oxide layers on both sides need to be etched away, so that the insulating layer 280 is finally formed by the first oxide layer 281, the second oxide layer 282, the third oxide layer 283 and the fourth oxide layer 284 as shown in fig. 4-8.
Step S140: different regions of the main body part of the device are implanted with different ions, so that the main body part of the device is sequentially divided into a first conduction type heavily doped region, a second conduction type lightly doped region and a first conduction type drift region from top to bottom, meanwhile, a gap is arranged in a region on one side of the top layer of the first conduction type heavily doped region, the gap is filled with the second conduction type heavily doped region, and the second conduction type heavily doped region is tightly attached to the deep trench.
Specifically, as shown in fig. 5 to 7, different ion implantations are performed on different regions of the device main body portion 220 to form different doped regions, so that the device main body portion 220 is sequentially divided into a first conductive type heavily doped region 221, a second conductive type lightly doped region 222, and a first conductive type drift region 223 from top to bottom, meanwhile, a gap (not shown) is formed in a region on one side of a top layer of the first conductive type heavily doped region 121, the gap is filled with the second conductive type heavily doped region 124, and the second conductive type heavily doped region 124 is disposed close to the deep trench 21, as shown in fig. 7, the specific process is as follows:
step S141: no ion implantation is performed in a lower portion of the device body portion to form a first conductivity type drift region.
Specifically, as can be seen from the above steps of the method, the entire region of the device main body portion 220 of the present embodiment is the P-drift region (i.e., the drift region of the first conductivity type), and the P-drift region is mainly located at the lower portion of the device main body portion 220, so as shown in fig. 4 to 8, it is only necessary to perform no ion implantation at the lower portion of the device main body portion 220 to keep the lower portion of the device main body portion 220 still as the P-drift region (i.e., the drift region of the first conductivity type).
Step S142: and implanting first ions into the middle part of the main body part of the device to form a second conductive type lightly doped region.
Specifically, as shown in fig. 5-7, the lightly doped region of the second conductivity type is mainly located in the middle of the device main body 220, so that the implantation of the first ions (specifically, phosphorus ions) in the middle of the device main body 220 can form the N-doped region (i.e., the lightly doped region of the second conductivity type), and the doping concentration of the N-doped region is preferably 2.56 × 1016cm-3。
Step S143: and injecting second ions into the first preset region on the upper part of the device main body part to form a first conduction type heavily doped region.
Specifically, as shown in fig. 5 to 7, the heavily doped region of the first conductivity type is mainly located in the upper first predetermined region of the device body 220 (mainly including the whole upper lower layer region and the upper top layer portion region), so that the P + doped region (i.e. the heavily doped region of the first conductivity type) can be formed by implanting second ions (specifically, boron ions) into the upper first predetermined region of the device body 220, and the doping concentration of the P + doped region is preferably 6.8 × 1017cm-3。
Step S144: and injecting third ions into a second preset region on the upper part of the device main body part to form a second conductive type heavily doped region.
Specifically, as shown in fig. 5 to 7, the heavily doped region of the second conductivity type is mainly located in the upper second predetermined region (mainly including the upper top layer portion region) of the device body 220, so that the N + doped region (i.e., the heavily doped region of the second conductivity type) can be formed by implanting third ions (specifically, arsenic ions) into the upper second predetermined region of the device body 220, and the doping concentration of the N + doped region is preferably 6 × 1019cm-3。
Step S150: and etching the other side region of the top layer of the first conductive type heavily doped region to form a shallow trench in a concave manner in the other side region of the top layer of the first conductive type heavily doped region, and meanwhile, a preset distance is arranged between the shallow trench and the second conductive type heavily doped region to form a resistor region between the shallow trench and the second conductive type heavily doped region.
Specifically, as shown in fig. 5-8, the other side region of the top layer of the first conductive type heavily doped region 221 (mainly the outer side region of the top layer) is etched, a hard mask (e.g., silicon nitride) is deposited on the top end of the first conductive type heavily doped region 221 as a barrier layer for subsequent trench digging, and a photolithography plate is used to perform deep trench etching, so as to form a deep trench 21 (i.e., a trench gate region) at the top end of the device body portion and to form a shallow trench 22 at the other side region of the top layer of the first conductive type heavily doped region 221, and meanwhile, the shallow trench 22 and the second conductive type heavily doped region 224 are spaced apart by a predetermined distance to form a resistor region (specifically, the middle region of the top layer of the first conductive type heavily doped region 221) therebetween. The specific etching process may use reactive ion etching or plasma etching. After the shallow trench 22 is etched, the hard mask is removed.
Step S160: and depositing and etching a polycrystalline semiconductor in the shallow trench to form an insulated resistance control grid for controlling the characteristics of the resistance region in the shallow trench.
Specifically, the polycrystalline semiconductor of the method step may be polysilicon, and the deposition and etching of the polysilicon in the shallow trench 22 may form the resistor control gate. In order to insulate the resistor control gate in the shallow trench 22, an oxide layer is also formed in the shallow trench 22. The oxide layer may be thermally grown from silicon dioxide (SiO 2), silicon oxynitride (SiON), or other materials, and silicon dioxide is preferably used in this embodiment.
Thus, in some examples, as shown in fig. 8, the method steps of "performing deposition and etching of polycrystalline semiconductor in the shallow trench to form an insulatively disposed resistive control gate within the shallow trench to control the characteristics of the resistive region" are performed as follows:
step S161: and carrying out thermal growth of an oxide material in the shallow trench to form a fifth oxide layer on the inner wall of the shallow trench.
Specifically, as shown in fig. 5-8, thermal growth of an oxide material (specifically, silicon dioxide) is performed within the shallow trench 22 to form a fifth oxide layer 291 (specifically, a silicon dioxide layer) on the inner wall of the shallow trench 22.
It should be noted that the fifth oxide layer 291 may be thermally grown to diffuse around the opening of the shallow trench 22, such that the top side of the device body 220 is also covered with the fifth oxide layer 291.
Step S162: and depositing and etching a polycrystalline semiconductor in the shallow trench to form a resistance control grid, wherein the fifth oxide layer is clamped between the inner wall of the shallow trench and the resistance control grid.
Specifically, as shown in fig. 5-9, after forming a fifth oxide layer 291 on the inner wall of the shallow trench 22, a polycrystalline semiconductor (specifically, polysilicon) is deposited and etched in the shallow trench 22 to form a resistance control gate 270, and the fifth oxide layer 291 is sandwiched between the inner wall of the shallow trench 22 and the resistance control gate 270, so that the fifth oxide layer 291 and the resistance control gate 270 are isolated and insulated from each other.
Step S163: and depositing an oxide material in the shallow trench to deposit a sixth oxide layer with a preset thickness on the top of the resistance control grid.
Specifically, as shown in fig. 5-9, after forming the resistance control gate 270 in the shallow trench 22, the deposition of the oxide material (specifically, silicon dioxide) may be directly continued in the shallow trench 22 to deposit a sixth oxide layer 292 (specifically, a silicon dioxide layer) with a predetermined thickness on top of the resistance control gate 270.
It should be noted that the sixth oxide layer 292 may be thermally grown to diffuse toward the sidewall of the resistance control gate 270, there is no clear boundary between the fifth oxide layer 291 and the sixth oxide layer 292, after the sixth oxide layer 292 with a predetermined thickness is deposited on the top of the control gate 270, the excess oxide layers on both sides need to be etched away, so as to make it as shown in fig. 5-9, at this time, the fifth oxide layer 291 and the sixth oxide layer 292 together form the insulating dielectric layer 290.
Step S170: and carrying out metallization processing on the top end of the device main body part and the bottom end of the single crystal semiconductor substrate so as to form a metalized source electrode on the top end of the device main body part and a metalized drain electrode on the bottom end of the single crystal semiconductor substrate, thus obtaining the semiconductor vertical device.
Specifically, as shown in fig. 5-10, after the above-mentioned method steps are performed, metallization is performed on the top end of the device body portion 220 and the bottom end of the single-crystal semiconductor substrate 210 to form a metalized source 240 on the top end of the device body portion 220 and a metalized drain 230 on the bottom end of the single-crystal semiconductor substrate 210, so as to obtain the semiconductor vertical device to be produced.
In the embodiment, the semiconductor vertical device produced by the method for producing the semiconductor vertical device can effectively reduce the temperature coefficient of the punch-through breakdown voltage of the conventional power semiconductor vertical device on the basis of the SGT-MOSFET structure, so that the reliability of the power semiconductor vertical device such as the SGT-MOSFET in application is improved, the structure is simple, and the overall power consumption of the device during operation is low.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, in the description of the present application, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be considered as limiting the present application. In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make and use the present application. In the foregoing description, various details have been set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (15)

1. A semiconductor vertical device is characterized by comprising a first conductive type substrate, a device main body part, a metalized drain, a metalized source, a control gate electrode, a shielding gate electrode and a resistance control gate;
the bottom end of the device main body part is sequentially covered with the first conductive type substrate and the metalized drain, and the top end of the device main body part is covered with the metalized source;
the device main body part is sequentially divided into a first conductive type heavily doped region, a second conductive type lightly doped region and a first conductive type drift region from top to bottom, and a deep groove is concavely arranged at the top end of the device main body part so as to respectively place the control gate electrode and the shielding gate electrode in an insulating manner;
the resistor control grid comprises a first conductive type heavily doped region, a second conductive type heavily doped region, a shallow groove, a resistor region and a resistor control grid, wherein a gap is formed in a region on one side of the top layer of the first conductive type heavily doped region, the gap is filled with the second conductive type heavily doped region, the region on the other side of the top layer of the first conductive type heavily doped region is concavely arranged to form the shallow groove, the second conductive type heavily doped region is tightly attached to the deep groove, the shallow groove is located in a region on the outer side of the top layer of the first conductive type heavily doped region, a preset distance is arranged between the shallow groove and the second conductive type heavily doped region at intervals to form the resistor region between the shallow groove and the second conductive type heavily doped region, and the resistor control grid for controlling the characteristics of the resistor region is arranged in an insulating mode in the shallow groove.
2. The semiconductor vertical device according to claim 1, wherein the first conductivity type substrate is a heavily doped first conductivity type substrate and the first conductivity type drift region is a lightly doped first conductivity type drift region.
3. The vertical semiconductor device as claimed in claim 1, wherein the deep trench divides the heavily doped region of the first conductivity type into a first heavily doped half region and a second heavily doped half region, divides the lightly doped region of the second conductivity type into a first lightly doped half region and a second lightly doped half region, and forms a U-shaped trench region at a top end of the drift region of the first conductivity type in sequence from top to bottom.
4. The vertical semiconductor device as claimed in claim 3, wherein one side region of the top layer of the first heavily doped half region is provided with the notch, one of the notches is filled with the second heavily doped region, the other side region of the top layer of the first heavily doped half region is recessed to form the shallow trench, one of the second heavily doped regions is disposed closely to the deep trench, a predetermined distance is provided between one of the shallow trench and the second heavily doped region to form the resistor region therebetween, and one of the shallow trenches is insulated with one of the resistor control gates for controlling the characteristics of one of the resistor regions.
5. The vertical semiconductor device as claimed in claim 4, wherein another gap is formed in a region on one side of the top layer of the second heavily doped half region, the another gap is filled with another heavily doped region of the second conductivity type, another shallow trench is recessed in a region on the other side of the top layer of the second heavily doped half region to form another shallow trench, the another heavily doped region of the second conductivity type is disposed closely to the deep trench, the another shallow trench and the another heavily doped region of the second conductivity type are spaced apart by a predetermined distance to form another resistor region therebetween, and another resistor control gate for controlling the characteristics of the another resistor region is disposed in the another shallow trench in an insulating manner.
6. The semiconductor vertical device of claim 3, wherein the shield gate electrode is disposed in a U-shaped groove region of the deep groove, and an insulating layer is sandwiched between the shield gate electrode and an inner wall of the U-shaped groove region, so that the shield gate electrode is disposed in the deep groove in an insulated manner.
7. The semiconductor vertical device of claim 6, wherein the control gate electrode is disposed in the deep trench and the control gate electrode is disposed above the shield gate electrode, and the insulating layers are sandwiched between the bottom end of the control gate electrode and the shield gate electrode, between the top end of the control gate electrode and the metalized source, and between the sidewall of the control gate electrode and the inner wall of the deep trench, so that the control gate electrode is disposed in the deep trench in an insulated manner.
8. The semiconductor vertical device of claim 7, wherein a bottom end of the control gate electrode extends into the U-shaped trench region.
9. The semiconductor vertical device according to claim 7, wherein a top end of the control gate electrode is higher than a top end of the second conductive-type lightly doped region.
10. The semiconductor vertical device of claim 1, wherein an insulating dielectric layer is sandwiched between the resistance control gate and the adjacent inner wall of the shallow trench and the adjacent metalized source.
11. The semiconductor vertical device according to any of claims 1 to 10, characterized in that the first conductivity type is P-type and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type.
12. A method for producing a semiconductor vertical device, comprising the steps of:
providing a single crystal semiconductor substrate, wherein the single crystal semiconductor substrate is used as a first conductive type substrate, and epitaxial growth is carried out on the top side of the semiconductor substrate to form a device main body part;
etching the device main body part to form a deep groove inwards at the top end of the device main body part;
depositing and etching a polycrystalline semiconductor for multiple times in the deep groove to form a shielding gate electrode and a control gate electrode which are arranged in an insulating manner in the deep groove respectively;
different regions of the device main body part are subjected to different ion implantation, so that the device main body part is sequentially divided into a first conduction type heavily doped region, a second conduction type lightly doped region and a first conduction type drift region from top to bottom, meanwhile, a gap is formed in a region on one side of the top layer of the first conduction type heavily doped region, the gap is filled with the second conduction type heavily doped region, and the second conduction type heavily doped region is tightly attached to the deep groove;
etching the other side region of the top layer of the first conductive type heavily doped region to form a shallow trench in a concave manner in the other side region of the top layer of the first conductive type heavily doped region, and meanwhile, a preset distance is arranged between the shallow trench and the second conductive type heavily doped region to form a resistor region between the shallow trench and the second conductive type heavily doped region;
depositing and etching a polycrystalline semiconductor in the shallow trench to form an insulated resistance control grid for controlling the characteristics of the resistance area in the shallow trench;
and carrying out metallization processing on the top end of the device main body part and the bottom end of the single crystal semiconductor substrate so as to form a metalized source electrode on the top end of the device main body part and a metalized drain electrode on the bottom end of the single crystal semiconductor substrate, and thus obtaining the semiconductor vertical device.
13. The method according to claim 12, wherein the step of depositing and etching a polycrystalline semiconductor in the deep trench to form a shield gate electrode and a control gate electrode respectively disposed in an insulated manner in the deep trench comprises:
carrying out first thermal growth of an oxidation material in the deep groove to form a first oxidation layer in a first preset region on the inner wall of the deep groove;
carrying out first deposition and etching of a polycrystalline semiconductor in the deep groove to form a shielding gate electrode, wherein the first oxidation layer is clamped between the inner wall of the deep groove and the shielding gate electrode;
performing first deposition of an oxide material in the deep trench to deposit a second oxide layer with a preset thickness on the top end of the shielding gate electrode;
carrying out second thermal growth of an oxidation material in the deep groove to form a third oxidation layer on the inner wall of the deep groove;
carrying out second deposition and etching on a polycrystalline semiconductor in the deep trench to form a control gate electrode, wherein the second oxide layer is clamped between the top end of the shielding gate electrode and the bottom end of the control gate electrode, and the third oxide layer is clamped between the inner wall of the deep trench and the control gate electrode;
and carrying out second deposition of an oxidation material in the deep groove so as to deposit a fourth oxidation layer with a preset thickness at the top end of the control gate electrode.
14. The production method according to claim 12 or 13, wherein the step of performing different ion implantations on different regions of the device main body portion to sequentially divide the device main body portion into a first conductivity type heavily doped region, a second conductivity type lightly doped region and a first conductivity type drift region from top to bottom, wherein a region on one side of a top layer of the first conductivity type heavily doped region is provided with a gap filled with the second conductivity type heavily doped region, and the step of disposing the second conductivity type heavily doped region in close proximity to the deep trench specifically includes:
performing no ion implantation in a lower portion of the device body portion to form the first conductivity type drift region;
implanting first ions into the middle of the device main body part to form the second conductive type lightly doped region;
injecting second ions into a first preset region on the upper part of the device main body part to form the first conduction type heavily doped region;
and injecting third ions into a second preset region on the upper part of the device main body part to form the second conductive type heavily doped region.
15. The method according to claim 14, wherein the step of depositing and etching the polycrystalline semiconductor in the shallow trench to form an insulated resistive control gate in the shallow trench for controlling the characteristics of the resistive region comprises:
carrying out thermal growth of an oxidation material in the shallow trench to form a fifth oxidation layer on the inner wall of the shallow trench;
depositing and etching a polycrystalline semiconductor in the shallow trench to form a resistance control grid, wherein the fifth oxidation layer is clamped between the inner wall of the shallow trench and the resistance control grid;
and depositing an oxidation material in the shallow trench to deposit a sixth oxidation layer with a preset thickness on the top end of the resistance control grid.
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