CN113948478A

CN113948478A - Package carrier and method for manufacturing the same

Info

Publication number: CN113948478A
Application number: CN202010679023.5A
Authority: CN
Inventors: 陈柏玮; 林纬廸; 简俊贤
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2020-07-15
Filing date: 2020-07-15
Publication date: 2022-01-18

Abstract

The invention provides a package carrier and a manufacturing method thereof. The package carrier includes a build-up circuit structure, a first insulating passivation layer, a plurality of bonding pads, and a plurality of metal balls. The build-up circuitry structure has an upper surface. The first insulating protection layer is configured on the upper surface of the build-up circuit structure and is provided with a plurality of first openings. The connecting pads are respectively arranged in the first openings of the first insulating protective layer and are structurally and electrically connected to the layer-adding circuit structure. Each connecting pad has an arc-shaped groove. The metal balls are respectively arranged in the arc-shaped grooves of each connecting pad. The metal balls and the corresponding connecting pads define a plurality of bump structures, and a plurality of top surfaces of the bump structures are positioned on the same plane. The packaging carrier plate provided by the invention has better flatness, and the manufacturing method of the packaging carrier plate can improve the packaging yield of chips.

Description

Package carrier and method for manufacturing the same

Technical Field

The present invention relates to a substrate structure and a method for fabricating the same, and more particularly, to a package carrier and a method for fabricating the same.

Background

In order to achieve the chip stacking structure, a copper pillar structure formed by electroplating is disposed on a circuit substrate or a carrier of a Flip chip (Flip chip) or a package-on-package (POP) package. However, the coplanarity is not good due to the electroplating and layer-adding processes required in the process of manufacturing the circuit substrate or the carrier, and the height of the electroplated copper pillar structure is affected to be varied accordingly. That is, the surface Coplanarity (Coplanarity) of the circuit substrate or the carrier having the copper pillar structure is not good. In order to solve the above problems, before the chip is packaged on the circuit substrate or the carrier having the copper pillar structure, an additional grinding process is required to be performed on the copper pillar structure to improve the yield of the chip package. However, the polishing process is required to be added, which results in a long process and high manufacturing cost.

Disclosure of Invention

The invention is directed to a package carrier having a better flatness.

The invention aims at a manufacturing method of a packaging carrier plate, which is used for manufacturing the packaging carrier plate and can improve the packaging yield of chips.

According to an embodiment of the invention, the package carrier includes a build-up circuit structure, a first insulating passivation layer, a plurality of bonding pads, and a plurality of metal balls. The build-up circuitry structure has an upper surface. The first insulating protection layer is configured on the upper surface of the build-up circuit structure and is provided with a plurality of first openings. The connecting pads are respectively arranged in the first openings of the first insulating protective layer and are structurally and electrically connected to the layer-adding circuit structure. Each connecting pad has an arc-shaped groove. The metal balls are respectively arranged in the arc-shaped grooves of each connecting pad. The metal balls and the corresponding connecting pads respectively define a plurality of bump structures, and a plurality of top surfaces of the bump structures are positioned on the same plane.

In the package carrier according to the embodiment of the invention, the package carrier further includes a second insulating passivation layer disposed on a lower surface of the build-up circuit structure opposite to the upper surface and having a plurality of second openings, wherein the second openings expose a portion of the build-up circuit structure.

In the package carrier according to the embodiment of the invention, each metal ball includes a copper core, a first metal layer and a second metal layer. The first metal layer covers the surface of the copper core, and the second metal layer covers the first metal layer.

In the package carrier according to the embodiment of the invention, the second metal layer completely covers the first metal layer, and the metal balls and the corresponding connecting pads respectively define a plurality of flat bump structures.

In the package carrier according to the embodiment of the invention, the second metal layer covers a portion of the first metal layer, and the metal balls and the corresponding connecting pads define a plurality of convex-top-type bump structures.

According to an embodiment of the present invention, a method for manufacturing a package carrier includes the following steps. A substrate is provided. The substrate comprises a core layer, two first copper foil layers and two second copper foil layers. The two first copper foil layers are arranged on the two opposite surfaces of the core layer and are positioned between the core layer and the two second copper foil layers. Two photoresist layers are formed on the two second copper foil layers of the substrate respectively. The two photoresist layers are respectively provided with a plurality of openings, and the openings expose part of the two second copper foil layers. And bonding a plurality of metal balls on the two second copper foil layers exposed by the openings. Two first insulating protective layers are formed on the two photoresist layers respectively. The two first insulating protective layers are respectively provided with a plurality of first openings, and the metal balls are respectively exposed out of the first openings. A plurality of connection pads are formed in the first openings of the two first insulation protection layers and extend to the two first insulation protection layers. The connecting pads cover the metal balls respectively, and an arc-shaped junction is formed between each connecting pad and the corresponding metal ball. Two build-up circuit structures are formed on the two first insulating protective layers respectively. The connecting pad is electrically connected to the two build-up circuit structures. The substrate and the photoresist layer are removed to expose the two first insulating protective layers and the metal balls. The metal balls and the corresponding connecting pads respectively define a plurality of bump structures, and a plurality of top surfaces of the bump structures are positioned on the same plane.

In the method for manufacturing a package carrier according to an embodiment of the invention, the method for manufacturing a package carrier further includes forming two second insulating protective layers on the two build-up circuit structures after forming the two build-up circuit structures on the two first insulating protective layers respectively and before removing the substrate and the photoresist layer. The two second insulating protective layers are respectively provided with a plurality of second openings, and the second openings respectively expose part of the two layer-adding circuit structures.

In the method for manufacturing a package carrier according to an embodiment of the invention, each metal ball includes a copper core, a first metal layer, and a second metal layer. The first metal layer covers the surface of the copper core, and the second metal layer covers the first metal layer.

In the method for manufacturing a package carrier according to an embodiment of the invention, the step of removing the substrate and the photoresist layer by completely covering the first metal layer with the second metal layer includes: and stripping the two first copper foil layers and the two second copper foil layers of the substrate to remove the core layer and the two first copper foil layers. The two second copper foil layers are removed to expose the photoresist layer and a surface of the second metal layer of each metal ball. The photoresist layer is removed to expose the two first insulating passivation layers and the metal balls. The metal balls and the corresponding connecting pads respectively define a plurality of flat bump structures.

In the method for manufacturing a package carrier according to the embodiment of the invention, after the photoresist layer is removed, a portion of the second metal layer of each metal ball is removed to expose a portion of the first metal layer. The metal balls and the corresponding connecting pads respectively define a plurality of convex top type bump structures.

In view of the above, in the design of the package carrier of the present invention, the metal balls are respectively disposed in the arc-shaped grooves of each of the connecting pads, and the metal balls and the corresponding connecting pads can define a plurality of bump structures, wherein top surfaces of the bump structures are located on the same plane. That is, the bump structure of the present invention has better Coplanarity (Coplanarity). Therefore, the package carrier plate of the invention has better flatness and can improve the packaging yield of subsequent chips. In addition, compared with the conventional copper pillar structure formed by electroplating and grinding processes, the manufacturing method of the package carrier plate of the invention defines the bump structure by the connecting pad and the metal ball, so that the grinding process is not required to be performed before the chip package, the manufacturing process can be simplified, and the production cost can be reduced.

Drawings

Fig. 1A to fig. 1L are schematic partial cross-sectional views illustrating a method for manufacturing a package carrier according to an embodiment of the invention;

fig. 2 is a schematic partial cross-sectional view illustrating a package carrier according to an embodiment of the invention;

fig. 3A is a schematic top view illustrating a package carrier according to another embodiment of the invention;

fig. 3B is a schematic sectional view taken along line I-I of fig. 3A.

Description of the reference numerals

10: a substrate;

12, a core layer;

13. 15, surface;

14: a first copper foil layer;

16: a second copper foil layer;

20, photoresist layer;

22, an opening;

100a, 100b, a package carrier;

110. 110b, metal balls;

112, copper core;

114 a first metal layer;

116. 116b a second metal layer;

117: a surface;

120, a first insulating protection layer;

122, a first opening;

130a copper layer;

130, connecting pads;

140, a layer-adding circuit structure;

141, an upper surface;

143 lower surface;

142, a dielectric layer;

144, a circuit layer;

146, conductive vias;

150, a second insulating protection layer;

152: a second opening;

170, a bump;

b1, flat bump structure;

b2 convex top type bump structure;

c, an arc-shaped groove;

d1, chip configuration area;

d2, peripheral area;

h1: first height;

h2, second height;

p1, P2 are plane;

s is an arc junction;

t is the top surface.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1A to fig. 1L are schematic partial cross-sectional views illustrating a manufacturing method of a package carrier according to an embodiment of the invention. For convenience of description, fig. 1K and 1L only show one package carrier board after being detached from the substrate 10.

Referring to fig. 1A, a substrate 10 is provided. In detail, the substrate 10 of the present embodiment includes a core layer 12, two first copper foil layers 14, and two second copper foil layers 16. The first copper foil layer 14 is disposed on the

opposite surfaces

13, 15 of the core layer 12 and located between the core layer 12 and the second copper foil layer 16. Here, the substrate 10 is, for example, a peelable copper foil substrate, and the material of the core layer 12 is, for example, glass fiber, but the invention is not limited to the substrate 10. In other embodiments not shown, the substrate may also be a BT resin substrate or other suitable substrate.

Next, referring to fig. 1B, two photoresist layers 20 are formed on the second copper foil layer 16 of the substrate 10, wherein the photoresist layers 20 have a plurality of openings 22, respectively, and a portion of the second copper foil layer 16 is exposed by the openings 22. Here, the photoresist layer 20 is formed by, for example, pressing a photoresist material layer (not shown) onto the second copper foil layer 16 of the substrate 10 (see fig. 1A) by a pressing method (plating), and then forming the photoresist layer 20 with the opening 22 by a laser drilling (laser drilling).

Next, referring to fig. 1D, a plurality of metal balls 110 are bonded on the second copper foil layer 16 exposed by the openings 22 of the photoresist layer 20. In detail, the step of bonding the metal balls 110 on the second copper foil layer 16 exposed by the openings 22 is to provide the metal balls 110 in the openings 22 of the photoresist layer 20, in which each metal ball 110 includes a copper core 112, a first metal layer 114 and a second metal layer 116, referring to fig. 1C. First metal layer 114 covers the surface of copper core 112, and second metal layer 116 covers first metal layer 114. Here, the thickness of the first metal layer 114 is thinner than that of the second metal layer 116, and the first metal layer 114 can be regarded as a protection layer to protect the surface of the copper core 112. The first metal layer 114 is, for example, a nickel layer or a gold layer, and the second metal layer 116 is, for example, a pure tin layer, a tin alloy layer, a tin-silver-copper alloy layer, a tin-antimony alloy layer, a tin-lead alloy layer, and the like, but not limited thereto. Then, referring to fig. 1D, a reflow process is performed on the metal balls 110, so that the metal balls 110 are bonded to the second copper foil layer 16 exposed by the opening 22 through an interface metal Compound (interfacial metal Compound). More specifically, after the reflow process, the second metal layer 116 is molten and flows to fill the opening 22 of the photoresist layer 20. At this time, the metal ball 110 is bonded to the second copper foil layer 16 through the molten second metal layer 116.

Next, referring to fig. 1E, two first insulating protective layers 120 are formed on the two photoresist layers 20, respectively, wherein the first insulating protective layers 120 have a plurality of first openings 122, respectively, and the first openings 122 expose the metal balls 110, respectively. Here, the material of the first insulating protection layer 120 is, for example, dry film type solder resist, and the types thereof are, for example, Taiyo AUS SR1, SR 3; hitachi SR7300, SRFA; sumitomo LAZ-7751, 7752, etc., but not limited thereto.

Next, referring to fig. 1G, a plurality of connecting pads 130 are formed in the first openings 122 of the first insulating protection layer 120 and extend to the first insulating protection layer 120. Here, the connecting pads 130 respectively cover the metal balls 110, and each connecting pad 130 has an arc-shaped junction S with the corresponding metal ball 110. In detail, referring to fig. 1F, first, two copper layers 130a are electroplated on the first insulating passivation layer 120, respectively, wherein the copper layers 130a cover the metal balls 110, fill the first openings 122, and extend to the first insulating passivation layer 120. Since the copper layer 130a covers the surface of the metal ball 110, the connection interface between the connection pad 130 and the metal ball 110 formed subsequently is an arc-shaped junction S (see fig. 1G). Then, referring to fig. 1G, two copper layers 130a are patterned, and connection pads 130 are formed on the metal balls 110, respectively. That is, the connecting pads 130 are separated from each other and expose a portion of the first insulating protection layer 120.

Next, referring to fig. 1H, two build-up circuit structures 140 are formed on the first insulating passivation layer 120, wherein the connecting pads 130 are structurally and electrically connected to the build-up circuit structures 140. Here, the build-up circuitry 140 includes at least one dielectric layer 142 (schematically illustrated as a tri-layer dielectric layer 142), at least one circuitry layer 144 (schematically illustrated as a tri-layer circuitry layer 144), and at least one conductive via 146 (schematically illustrated as a plurality of conductive vias 146), respectively. The dielectric layer 142 covers the connecting pad 130, the circuit layer 144 is disposed on the dielectric layer 142, and the conductive via 146 penetrates the dielectric layer 142 to electrically connect the connecting pad 130 and the circuit layer 144. The build-up circuit structure 140 is formed by a pressing method and a copper electroplating method, and the number of layers of the dielectric layer 142 and the circuit layer 144 can be increased or decreased according to the requirement, which is not limited herein.

Then, referring to fig. 1I, two second insulating protective layers 150 are formed on the build-up circuit structure 140, wherein the second insulating protective layers 150 have a plurality of second openings 152, and the second openings 152 expose a portion of the circuit layer 144 of the build-up circuit structure 140. Here, the material of the second insulating protection layer 150 is, for example, dry film type solder resist, and the types thereof are, for example, Taiyo AUS SR1, SR 3; hitachi SR7300, SRFA; sumitomo LAZ-7751, 7752, etc., but not limited thereto.

Finally, referring to fig. 1J and fig. 1L, the substrate 10 and the photoresist layer 20 are removed to expose the first insulating protection layer 120 and the metal balls 110. In detail, referring to fig. 1J, the step of removing the substrate 10 and the photoresist layer 20 includes, first, stripping the first copper foil layer 14 and the second copper foil layer 16 of the substrate 10 to remove the core layer 12 and the first copper foil layer 14. Then, referring to fig. 1J and fig. 1K, the second copper foil layer 16 is removed to expose the photoresist layer 20 and the surface 117 of the second metal layer 116, wherein the surface 117 of the second metal layer 116 is coplanar with the photoresist layer 20. Finally, referring to fig. 1L, the photoresist layer 20 is removed to expose the first insulating protection layer 120 and the peripheral surface of the second metal layer 116 of the metal ball 110. Here, the metal balls 110 and the corresponding connecting pads 130 define a plurality of flat bump structures B1. Thus, the package carrier 100a having the flat bump structure B1 and being coreless is completed.

In structure, referring to fig. 1L, the package carrier 100a of the present embodiment includes a build-up circuit structure 140, a first insulating layer 120, a bonding pad 130, and a metal ball 110. Build-up circuitry 140 has a top surface 141 and includes a dielectric layer 142, a circuitry layer 144, and a conductive via 146. The first insulating protection layer 120 is disposed on the upper surface 141 of the build-up circuit structure 140 and has a first opening 122. The connecting pads 130 are respectively disposed in the first openings 122 of the first insulating protective layer 120 and are structurally and electrically connected to the build-up circuit structure 140. Each connecting pad 130 has an arc-shaped groove C, and the metal balls 110 are respectively disposed in the arc-shaped grooves C of each connecting pad 130. Here, the dielectric layer 142 covers the connecting pad 130, the circuit layer 144 is disposed on the dielectric layer 141, and the conductive via 146 penetrates the dielectric layer 142 to electrically connect the connecting pad 130 and the circuit layer 144. Each metal ball 110 includes a copper core 112, a first metal layer 114, and a second metal layer 116, wherein the first metal layer 114 covers the surface of the copper core 112, and the second metal layer 116 covers the first metal layer 114.

Furthermore, the metal ball 110 and the corresponding connecting pad 130 of the present embodiment define a flat bump structure B1, wherein the surface 117 of the second metal layer 116 of the metal ball 110 is located on the same plane P1. In addition, the package carrier 100a of the present embodiment further includes a second insulating protection layer 150 disposed on the lower surface 143 of the build-up circuit structure 140 opposite to the upper surface 141 and having a second opening 152, wherein the second opening 152 exposes a portion of the circuit layer 144 of the build-up circuit structure 140.

Since the bump structure B1 of the present embodiment is composed of the metal ball 110 and the corresponding connecting pad 130, the copper pillar structure is not formed by electroplating a copper layer, and the surface 117 of the second metal layer 116 of the metal ball 110 is located on the same plane P1. Therefore, the flat bump structure B1 of the present embodiment has better coplanarity, so that the package carrier 100a of the present embodiment has better flatness, which is beneficial to the yield of subsequent chip packages. In addition, the embodiment can obtain better flatness without additionally adding a grinding procedure before the chip packaging, thereby effectively simplifying the processing steps and reducing the production cost.

It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 2 is a schematic partial cross-sectional view of a package carrier according to an embodiment of the invention. The package carrier 100a of the present embodiment is similar to the package carrier 100b, and the difference between the two is: after the step shown in fig. 1L, i.e., removing the photoresist layer 20 to expose the first insulating protection layer 120 and the metal balls 110, referring to fig. 1L and fig. 2, an etching process is performed to remove a portion of the second metal layer 116 of the metal balls 110 to expose a portion of the first metal layer 114, thereby forming the metal balls 110 b. Here, the second metal layer 116B only covers a portion of the first metal layer 114, and the second metal layer 116B may be coplanar with the first insulating passivation layer 120, and the metal balls 110B including the copper core 112, the first metal layer 114 and the second metal layer 116B and the corresponding connecting pads 130 may define a plurality of bump structures B2, wherein the top surfaces T of the bump structures B2 are located on the same plane P2. Thus, the package carrier 100B having the top bump structure B2 and being coreless is completed.

In the package carrier 100B of the present embodiment, the metal balls 110B are disposed in the arc-shaped grooves C of the bonding pads 130, and the metal balls 110B and the corresponding bonding pads 130 can define a bump structure B2, wherein the top surfaces T of the bump structures B2 are located on the same plane P2. That is, the convex top type bump structure B2 of the present embodiment may have better coplanarity. Therefore, the package carrier 100b of the present embodiment has a better flatness, and the yield of the subsequent chip package can be improved. In addition, since the embodiment can achieve better flatness without a grinding process, the process steps can be effectively simplified and the manufacturing cost can be reduced.

Fig. 3A is a schematic top view illustrating a package carrier according to another embodiment of the invention. Fig. 3B is a schematic sectional view taken along line I-I of fig. 3A. Referring to fig. 3A and fig. 3B, the package carrier 100c of the present embodiment has a chip layout area D1 and a peripheral area D2 surrounding the chip layout area D1. The peripheral region D2 is provided with a flat bump structure B1 as shown in fig. 1L, and the chip arrangement region D1 is provided with bumps 170. For example, the chip configuration region D1 may be configured as a chip with logic computation processing capability, and the peripheral region D2 may be configured as a chip with memory storage function, but not limited thereto. The bump structures B1 to the first passivation layer 120 have a first height H1, and the bumps 170 to the first passivation layer 120 have a second height H2, wherein the first height H1 is 3 times to 5 times the second height H2.

In summary, in the design of the package carrier of the present invention, the metal balls are respectively disposed in the arc-shaped grooves of each of the bonding pads, and the metal balls and the corresponding bonding pads can define a plurality of bump structures, wherein top surfaces of the bump structures are located on the same plane. That is, the bump structure of the present invention has better coplanarity. Therefore, the package carrier plate of the invention has better flatness and can improve the packaging yield of subsequent chips. In addition, compared with the conventional copper pillar structure formed by electroplating and grinding processes, the manufacturing method of the package carrier plate of the invention defines the bump structure by the connecting pad and the metal ball, so that the grinding process is not required to be performed before the chip package, the manufacturing process can be simplified, and the production cost can be reduced.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A package carrier, comprising:

a build-up circuitry structure having an upper surface;

the first insulating protection layer is configured on the upper surface of the layer-adding circuit structure and is provided with a plurality of first openings;

a plurality of connection pads respectively disposed in the first openings of the first insulating passivation layer and structurally and electrically connected to the build-up circuit structure, wherein each of the connection pads has an arc-shaped groove; and

and a plurality of metal balls respectively arranged in the arc-shaped grooves of each of the plurality of connecting pads, wherein the plurality of metal balls respectively define a plurality of bump structures with the corresponding plurality of connecting pads, and a plurality of top surfaces of the plurality of bump structures are positioned on the same plane.

2. The package carrier of claim 1, further comprising:

the second insulating protection layer is arranged on the lower surface of the layer-adding circuit structure opposite to the upper surface and is provided with a plurality of second openings, and the second openings expose part of the layer-adding circuit structure.

3. The package carrier of claim 1 wherein each of the metal balls comprises a copper core, a first metal layer, and a second metal layer, the first metal layer covers a surface of the copper core, and the second metal layer covers the first metal layer.

4. The package carrier according to claim 3, wherein the second metal layer completely covers the first metal layer, and the plurality of metal balls and the corresponding connecting pads define a plurality of flat bump structures.

5. The package carrier according to claim 3, wherein the second metal layer covers a portion of the first metal layer, and the metal balls and the corresponding bonding pads define a plurality of bump structures.

6. A method for manufacturing a package carrier includes:

providing a substrate, wherein the substrate comprises a core layer, two first copper foil layers and two second copper foil layers, and the two first copper foil layers are arranged on two opposite surfaces of the core layer and positioned between the core layer and the two second copper foil layers;

forming two photoresist layers on the two second copper foil layers of the substrate respectively, wherein the two photoresist layers are provided with a plurality of openings respectively, and part of the two second copper foil layers are exposed out of the openings;

bonding a plurality of metal balls on the two second copper foil layers exposed by the openings;

forming two first insulating protective layers on the two photoresist layers respectively, wherein the two first insulating protective layers are provided with a plurality of first openings respectively, and the plurality of metal balls are exposed out of the plurality of first openings respectively;

forming a plurality of connection pads in the first openings of the two first insulating passivation layers and extending to the two first insulating passivation layers, wherein the connection pads cover the metal balls respectively, and an arc-shaped joint surface is formed between each of the connection pads and each of the corresponding metal balls;

forming two build-up circuit structures on the two first insulating protective layers respectively, wherein the connecting pads are electrically connected to the two build-up circuit structures; and

and removing the substrate and the photoresist layer to expose the two first insulating protective layers and the plurality of metal balls, wherein the plurality of metal balls and the corresponding connecting pads respectively define a plurality of bump structures, and a plurality of top surfaces of the plurality of bump structures are positioned on the same plane.

7. The method for manufacturing a package carrier of claim 6, further comprising:

after the two build-up line structures are formed on the two first insulating protective layers respectively and before the substrate and the photoresist layer are removed, two second insulating protective layers are formed on the two build-up line structures respectively, the two second insulating protective layers are provided with a plurality of second openings respectively, and the second openings expose parts of the two build-up line structures respectively.

8. The method of claim 6, wherein each of the metal balls comprises a copper core, a first metal layer, and a second metal layer, wherein the first metal layer covers a surface of the copper core, and the second metal layer covers the first metal layer.

9. The method of claim 8, wherein the step of removing the substrate and the photoresist layer by completely covering the first metal layer with the second metal layer comprises:

stripping the two first copper foil layers and the two second copper foil layers of the substrate to remove the core layer and the two first copper foil layers;

removing the two second copper foil layers to expose the photoresist layers and the surface of the second metal layer of each of the metal balls; and

and removing the photoresist layers to expose the two first insulating protective layers and the metal balls, wherein the metal balls and the corresponding connecting pads respectively define a plurality of flat bump structures.

10. The method as claimed in claim 9, wherein after removing the photoresist layers, a portion of the second metal layer of each of the metal balls is removed to expose a portion of the first metal layer, and the metal balls and the corresponding connecting pads define a plurality of bump structures.