CN113851579A

CN113851579A - Semiconductor structure and method for forming semiconductor structure

Info

Publication number: CN113851579A
Application number: CN202010597695.1A
Authority: CN
Inventors: 杨成成
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2021-12-28

Abstract

A semiconductor structure and a method of forming a semiconductor structure, wherein the semiconductor structure comprises: a substrate; a lower electrode layer on the surface of the substrate; a magnetic tunnel junction located on the surface of the lower electrode layer; an upper electrode layer on a surface of the magnetic tunnel junction; an inversion enhancement layer located between the magnetic tunnel junction and the upper electrode layer or between the magnetic tunnel junction and the lower electrode layer; the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer, when the overturning enhancement layer is positioned between the magnetic tunnel junction and the upper electrode layer, the piezoelectric layer is positioned between the overturning enhancement layer and the upper electrode layer, when the overturning enhancement layer is positioned between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is positioned between the overturning enhancement layer and the lower electrode layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction. By the piezoelectric layer, the reliability and the stability of the magnetic random access memory can be improved while the writing power consumption of the magnetic random access memory is reduced.

Description

Semiconductor structure and method for forming semiconductor structure

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the semiconductor structure.

Background

Mram (magnetic Random Access memory) is a non-volatile magnetic Random Access memory. The Dynamic Random Access Memory (DRAM) has high-speed reading and writing capabilities of a Static Random Access Memory (SRAM) and high integration of the DRAM, has power consumption far lower than that of the DRAM, and does not degrade with the increase of service time compared with a Flash Memory (Flash). Because of the above-described characteristics of MRAM, it is considered to be able to replace SRAM, DRAM, EEPROM, and Flash.

Unlike conventional random access memory chip fabrication techniques, data in MRAM is not stored in the form of an electrical charge or current, but rather is stored in a magnetic state, and is sensed by measuring resistance without disturbing the magnetic state. MRAM uses Magnetic Tunnel Junction (MTJ) structures for data storage, generally, MRAM cells are composed of a transistor (1T) and a Magnetic Tunnel Junction (MTJ) together to form a memory cell, and the Magnetic Tunnel Junction (MTJ) structure includes at least two magnetic layers and a tunneling layer for isolating the two magnetic layers. Current flows perpendicularly from one magnetic layer through the tunneling layer or "through" the other magnetic layer. One of the magnetic layers is a pinned magnetic layer, which fixes the electrode in a specific direction through a strong pinning field. And the other magnetic layer is a freely rotatable magnetic layer holding one of the electrodes.

However, the reliability and stability of the existing magnetic random access memory still remain to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance and the reliability of a magnetic random access memory.

To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate; a lower electrode layer on the surface of the substrate; a magnetic tunnel junction located on the surface of the lower electrode layer; an upper electrode layer on a surface of the magnetic tunnel junction; an inversion enhancement layer located between the magnetic tunnel junction and the upper electrode layer or between the magnetic tunnel junction and the lower electrode layer; the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer, when the overturning enhancement layer is positioned between the magnetic tunnel junction and the upper electrode layer, the piezoelectric layer is positioned between the overturning enhancement layer and the upper electrode layer, when the overturning enhancement layer is positioned between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is positioned between the overturning enhancement layer and the lower electrode layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction.

Optionally, the material of the piezoelectric layer is a piezoelectric material.

Optionally, the material of the piezoelectric layer includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

Optionally, the thickness of the piezoelectric layer is greater than 0 nm, and the thickness of the piezoelectric layer is less than 10 nm.

Optionally, the magnetic moment direction of the switching enhancement layer is perpendicular to or parallel to the normal direction of the substrate surface.

Optionally, the method further includes: a first insertion layer between the switching enhancement layer and the magnetic tunnel junction.

Optionally, the method further includes: a second interposer layer between the flip enhancement layer and the piezoelectric layer.

Optionally, when the switching enhancement layer is located between the magnetic tunnel junction and the upper electrode layer, the semiconductor structure further includes: a seed layer located between the lower electrode layer and the magnetic tunnel junction.

Optionally, when the switching enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the semiconductor structure further includes: a buffer layer between the lower electrode layer and the piezoelectric layer.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a lower electrode layer on the surface of the substrate; forming a piezoelectric layer on the surface of the lower electrode layer; forming an overturning enhancement layer on the surface of the piezoelectric layer, wherein the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer; forming a magnetic tunnel junction on the surface of the overturning enhancement layer, wherein the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction when no external voltage is applied to the piezoelectric layer; and forming an upper electrode layer on the surface of the magnetic tunnel junction.

Optionally, the method further includes: a first insertion layer is formed between the magnetic tunnel junction and the switching enhancement layer.

Optionally, the method further includes: a second interposer layer is formed between the flip enhancing layer and the piezoelectric layer.

Optionally, the method further includes: a buffer layer is formed between the piezoelectric layer and the lower electrode layer.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a lower electrode layer on the surface of the substrate; forming a magnetic tunnel junction on the surface of the lower electrode layer; forming a turnover enhancement layer on the surface of the magnetic tunnel junction; forming a piezoelectric layer on the surface of the overturning enhancement layer, wherein the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer, and the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction when no external voltage is applied to the piezoelectric layer; and forming an upper electrode layer on the surface of the piezoelectric layer.

Optionally, the method further includes: a first insertion layer is formed between the switching enhancement layer and the magnetic tunnel junction.

Optionally, the method further includes: a second intervening layer is formed between the piezoelectric layer and the flip reinforcement layer.

Optionally, the method further includes: a seed layer is formed between the magnetic tunnel junction and the lower electrode layer.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the semiconductor structure provided by the technical scheme of the invention, when data is not written, namely when external voltage is not applied to the piezoelectric layer, the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction. Because the semiconductor structure further comprises the piezoelectric layer which is positioned between the turnover enhancement layer and the upper electrode layer or between the turnover enhancement layer and the lower electrode layer and used for controlling the magnetic moment direction of the turnover enhancement layer, when data are written, stress can be generated on the piezoelectric layer through an applied bias voltage, and the magnetic moment direction of the turnover enhancement layer is turned over for 90 degrees through the stress, namely, the magnetic moment direction of the turnover enhancement layer is perpendicular to the magnetic moment direction of the magnetic tunnel junction, so that the turnover enhancement layer can provide an additional bias magnetic field for the magnetic tunnel junction when the data are written, and the writing power consumption is reduced; meanwhile, when data is not written in, due to the fact that no bias voltage is applied, stress generated by the piezoelectric layer disappears, the magnetic moment direction of the overturning enhancement layer is enabled to overturn for 90 degrees again, namely the magnetic moment direction of the overturning enhancement layer returns to a state parallel to the magnetic moment direction of the magnetic tunnel junction, and the overturning enhancement layer does not generate a bias magnetic field influencing the magnetic moment direction of the free layer of the magnetic tunnel junction, so that the influence of the overturning enhancement layer on the magnetic moment direction of the free layer of the magnetic tunnel junction can be reduced when data is not written in, and the reliability and the stability of the magnetic random access memory are improved. In summary, the reliability and stability of the magnetic random access memory can be improved while the write power consumption of the magnetic random access memory is reduced by turning over the enhancement layer and the piezoelectric layer.

Further, because the second insertion layer is arranged between the overturning enhancement layer and the piezoelectric layer, on one hand, the overturning enhancement layer made of the magnetic material can be isolated from the piezoelectric layer made of the non-magnetic material through the second insertion layer, so that the mutual influence of diffusion and the like between the material of the overturning enhancement layer and the material of the piezoelectric layer is reduced, and on the other hand, the overturning enhancement layer can better form a magnetic moment in a specific direction through the second insertion layer.

Drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor structure;

FIGS. 2-4 are schematic structural diagrams illustrating steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

FIGS. 5-7 are schematic diagrams illustrating the operation of a semiconductor structure according to an embodiment of the present invention;

FIGS. 8-10 are schematic structural views of steps in a method of forming a semiconductor structure in accordance with another embodiment of the present invention;

fig. 11 to 13 are schematic views illustrating the operation of a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, the reliability and stability of existing magnetic random access memories still remain to be improved.

The reason why the performance and reliability of the conventional magnetic random access memory still remain to be improved is described in detail below with reference to the accompanying drawings.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure.

Referring to fig. 1, the semiconductor structure includes: a substrate 100; a lower electrode layer 110 on the substrate surface; a magnetic tunnel junction 120 located on the surface of the lower electrode layer 110, wherein the magnetic tunnel junction 120 includes a first magnetic film 121, an insulating film 122 located on the surface of the first magnetic film 121, and a second magnetic film 123 located on the surface of the insulating film 122, the first magnetic film 121 is a reference layer, and the second magnetic film 123 is a free layer; an inversion enhancement layer 130 disposed on a surface of the magnetic tunnel junction 120, wherein the inversion enhancement layer 130 provides a bias magnetic field for the magnetic tunnel junction 120; an upper electrode layer 140 on the surface of the turning enhancement layer 130.

In the above method, since the switching enhancement layer 130 having a magnetic moment direction perpendicular to the magnetic moment direction of the second magnetic film 123 is added, an additional bias magnetic field is provided to the magnetic tunnel junction 120, so that power consumption required for switching the magnetic moment direction of the second magnetic film 123 is reduced when data is written, that is, the write power consumption of the magnetic random access memory can be reduced.

However, since the magnetic moment direction of the switching enhancement layer 130 is always perpendicular to the magnetic moment direction of the second magnetic film 123, that is, an additional bias magnetic field provided by the switching enhancement layer 130 exists regardless of whether data is written or not, when data is not written, the bias magnetic field may affect the magnetic moment direction of the second magnetic film 123, and especially when the magnetic tunnel junction 130 is simultaneously affected by an ambient temperature (e.g., a temperature rise) and the like and the bias magnetic field, the magnetic moment direction of the second magnetic film 123 is easily switched, thereby resulting in poor reliability and stability of the magnetic random access memory.

In order to solve the above technical problems, embodiments of the present invention provide a semiconductor structure, which can reduce write power consumption of a magnetic random access memory when data is written through an inversion enhancement layer and a piezoelectric layer located between the inversion enhancement layer and an upper electrode layer or between the inversion enhancement layer and a lower electrode layer, and improve reliability and stability of the magnetic random access memory when data is not written.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 4 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 2, a substrate 200 is provided.

In this embodiment, the substrate 200 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

The material of the substrate 200 includes a semiconductor material.

In the present embodiment, the material of the substrate 200 includes silicon.

In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

Subsequently, a lower electrode layer is formed on the surface of the substrate 200; forming a piezoelectric layer on the surface of the lower electrode layer; forming an overturning enhancement layer on the surface of the piezoelectric layer; forming a magnetic tunnel junction on the surface of the overturning enhancement layer, wherein the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction when no external voltage is applied to the piezoelectric layer; fig. 3 to 4 are referred to a process of forming an upper electrode layer on the surface of the magnetic tunnel junction, and specifically forming the lower electrode layer, the piezoelectric layer, the flip enhancement layer, the magnetic tunnel junction, and the upper electrode layer.

Referring to fig. 3, a bottom electrode material layer 210 is formed on the surface of the substrate 200; forming a piezoelectric material layer 220 on the surface of the lower electrode material layer 210; forming an inversion enhancement material layer 230 on the surface of the piezoelectric material layer 220; forming a magnetic tunnel junction material layer 240 on the surface of the switching enhancement material layer 230; forming an upper electrode material layer 250 on the surface of the magnetic tunnel junction material layer 240; a patterned layer 260 is formed on the surface of the upper electrode material layer 250.

The lower electrode material layer 210 provides a material for forming a lower electrode layer.

In the present embodiment, the process of forming the lower electrode material layer 210 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The layer of piezoelectric material 220 provides material for forming a piezoelectric layer.

In the present embodiment, the process of forming the piezoelectric material layer 220 includes an electroplating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The layer of turn-up enhancement material 230 provides material for forming the turn-up enhancement layer.

In the present embodiment, the process of forming the switching enhancement material layer 230 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The magnetic tunnel junction material layer 240 provides a material for forming a magnetic tunnel junction.

In this embodiment, the magnetic tunnel junction material layer 240 includes: a first magnetic material layer 241 on the surface of the switching enhancement material layer 230, a tunneling material layer 242 on the surface of the first magnetic material layer, and a second magnetic material layer 243 on the surface of the tunneling material layer.

In this embodiment, the process of forming the first magnetic material layer 241, the tunneling material layer 242, and the second magnetic material layer 243 includes: a chemical vapor deposition process or an atomic layer deposition process.

In other embodiments, a method of forming the tunneling material layer includes: forming an initial tunneling material layer on the surface of the first magnetic material layer by adopting a deposition process; and carrying out an oxidation process on the initial tunneling material layer to form a tunneling material layer.

The first magnetic material layer 241 provides a material for forming a first magnetic film, the second magnetic material layer 243 provides a material for forming a second magnetic film, and the tunneling material layer 242 provides a material for forming a tunneling layer.

The upper electrode material layer 250 provides a material for forming an upper electrode layer.

In the present embodiment, the process of forming the upper electrode material layer 250 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, before the piezoelectric material layer 220 is formed, a buffer material layer 290 is formed on the surface of the lower electrode material layer 210.

The buffer material layer 290 provides a material for forming a buffer layer.

In this embodiment, a second interposer material layer 280 is formed on the surface of the piezoelectric material layer 220 before the inversion enhancing material layer 230 is formed.

The second interposer material layer 280 provides material for forming a second interposer layer.

In the present embodiment, the process of forming the second insertion material layer 280 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, before forming the magnetic tunnel junction material layer 240, a first insertion material layer 270 is formed on the surface of the switching enhancement material layer 230.

The first interposer layer 270 provides material for forming a first interposer layer.

In the present embodiment, the process of forming the first interposer material layer 270 includes a spin coating process, a plating process, or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

Referring to fig. 4, the upper electrode material layer 250, the magnetic tunnel junction material layer 240, the inversion enhancing material layer 230, the piezoelectric material layer 220 and the lower electrode material layer 210 are etched by using the patterning layer 260 as a mask until the surface of the substrate 200 is exposed, so as to form an upper electrode layer 251, a magnetic tunnel junction 300, an inversion enhancing layer 231, a piezoelectric layer 221 and a lower electrode layer 211.

Specifically, in the present embodiment, the lower electrode material layer 210 is etched to form a lower electrode layer 211 on the surface of the substrate 200; etching the piezoelectric material layer 220 to form a piezoelectric layer 221 on the surface of the lower electrode layer 211; etching the inversion enhancement material layer 230 to form an inversion enhancement layer 231 on the surface of the piezoelectric layer 221; etching the magnetic tunnel junction material layer 240 to form a magnetic tunnel junction 300 on the surface of the flip enhancement layer 231; the upper electrode material layer 250 is etched to form an upper electrode layer 251 on the surface of the magnetic tunnel junction 300.

The piezoelectric layer 221 is used to control the magnetic moment direction of the switching enhancement layer 231.

When no applied voltage is applied to the piezoelectric layer 221, the magnetic moment direction of the switching enhancement layer 231 is parallel to the magnetic moment direction of the magnetic tunnel junction 300.

In this embodiment, the process of etching the upper electrode material layer 250, the magnetic tunnel junction material layer 240, the switching enhancement material layer 230, the piezoelectric material layer 220, and the lower electrode material layer 210 includes a reactive ion etching process or an ion beam etching process.

In the present embodiment, the material of the lower electrode layer 211 includes tantalum, aluminum, or copper.

In this embodiment, the material of the piezoelectric layer 221 includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

In this embodiment, the thickness of the piezoelectric layer 221 ranges from 1 nm to 2 nm, and when the thickness of the piezoelectric layer 221 ranges from 1 nm to 2 nm, the magnetic moment direction of the flip enhancement layer 231 can be better controlled.

In other embodiments, the thickness of the piezoelectric layer 221 is between 0 nm and 1 nm, or greater than 2 nm and less than 10 nm.

In this embodiment, the material of the piezoelectric layer 221 is a piezoelectric material.

In this embodiment, the flip reinforcement layer 231 includes: 1 or more layers of inversion enhancement films (not shown) stacked in the substrate normal direction.

When the inversion enhancement layer 231 includes 2 or more layers of the inversion enhancement film, the inversion enhancement layer 231 further includes a non-magnetic layer (not shown) between adjacent inversion enhancement films.

In this embodiment, the material of the flip enhancement layer 231 includes one or more of cofe, cofeb, or nife in combination.

In this embodiment, the magnetic moment direction of the switching enhancing layer 231 is perpendicular or parallel to the normal direction of the surface of the substrate 200.

In the present embodiment, the magnetic tunnel junction 300 includes: a first magnetic film 301 on the surface of the switching enhancing layer 231; a tunneling layer 302 on the surface of the first magnetic film 301; and a second magnetic film 303 on the surface of the tunneling layer 302.

In this embodiment, the first magnetic film 301 is a free layer, and the second magnetic film 303 is a fixed layer.

The material of the first magnetic film 301 includes one or a combination of several of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron, or nickel-iron.

The material of the second magnetic film 303 includes one or a combination of several of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron, or nickel-iron.

The material of the tunneling layer 302 includes magnesium oxide.

The magnetic tunnel junction 300 may be a perpendicular anisotropic magnetic tunnel junction, or an in-plane anisotropic magnetic tunnel junction.

In the present embodiment, the material of the upper electrode layer 251 includes tantalum, aluminum, or copper.

In this embodiment, the patterning layer 260 is used as a mask to etch the upper electrode material layer 250, the magnetic tunnel junction material layer 240, the inversion enhancement material layer 230, the piezoelectric material layer 220, and the lower electrode material layer 210, and at the same time, etch the first insertion material layer 270, the second insertion material layer 280, and the buffer material layer 290 to form a first insertion layer 271, a second insertion layer 281, and a buffer layer 291.

Specifically, in the present embodiment, a first insertion layer 271 is formed between the magnetic tunnel junction 300 and the inversion enhancement layer 231, a second insertion layer 281 is formed between the inversion enhancement layer 231 and the piezoelectric layer 221, and a buffer layer 291 is formed between the piezoelectric layer 221 and the lower electrode layer 211.

In this embodiment, the material of the first insertion layer 271 includes a nonmagnetic metallic material or a nonmagnetic dielectric material, and the nonmagnetic metallic material includes ruthenium or tantalum.

In other embodiments, the first insertion layer is not formed.

In this embodiment, the material of the second insertion layer 281 includes a non-magnetic metal material including ruthenium or tantalum.

In other embodiments, the second insertion layer is not formed.

In other embodiments, no buffer layer is formed.

It should be noted that the patterning layer 260 is removed by being worn out during the etching process for forming the upper electrode layer 251, the magnetic tunnel junction 300, the inversion enhancement layer 231, the piezoelectric layer 221 and the lower electrode layer 211.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the method for forming a semiconductor structure, with reference to fig. 4, including: a substrate 200; a lower electrode layer 211 on the surface of the substrate 200; a magnetic tunnel junction 300 on the surface of the lower electrode layer 211; an upper electrode layer 251 on a surface of the magnetic tunnel junction 300; a switching enhancement layer 231 located between the magnetic tunnel junction 300 and the lower electrode layer 211; and a piezoelectric layer 221 positioned between the switching enhancement layer 231 and the lower electrode layer 211, wherein the piezoelectric layer 221 is used for controlling a magnetic moment direction of the switching enhancement layer 231, and the magnetic moment direction of the switching enhancement layer 231 is parallel to the magnetic moment direction of the magnetic tunnel junction 300 when no external voltage is applied to the piezoelectric layer 221.

The material of the substrate 200 includes a semiconductor material.

In the present embodiment, the material of the substrate 200 includes silicon.

The material of the tunneling layer 302 includes magnesium oxide.

In this embodiment, the semiconductor structure further includes: a first insertion layer 271 located between the magnetic tunnel junction 300 and the switching enhancement layer 231.

Since the first insertion layer 271 is provided between the magnetic tunnel junction 300 and the switching enhancement layer 231, the coupling between the switching enhancement layer 231 and the magnetic tunnel junction 300 can be reduced.

The material of the first insertion layer 271 includes a nonmagnetic metallic material or a nonmagnetic dielectric material, and the nonmagnetic metallic material includes ruthenium or tantalum.

In other embodiments, the semiconductor structure does not include a first insertion layer.

In this embodiment, the semiconductor structure further includes: a second insertion layer 281 between the flip enhancement layer 231 and the piezoelectric layer 221.

Since the second insertion layer 281 is further disposed between the flip enhancement layer 231 and the piezoelectric layer 221, on one hand, the flip enhancement layer 231 made of a magnetic material can be isolated from the piezoelectric layer 221 made of a non-magnetic material by the second insertion layer 281, so that mutual influence of diffusion and the like between the material of the flip enhancement layer 231 and the material of the piezoelectric layer 221 is reduced, and on the other hand, the flip enhancement layer 231 can be better made to form a magnetic moment in a specific direction by the second insertion layer 281.

The material of the second insertion layer 281 includes a non-magnetic metal material including ruthenium or tantalum.

In other embodiments, the semiconductor structure does not include a second insertion layer.

In this embodiment, the semiconductor structure further includes: a buffer layer 291 between the piezoelectric layer 221 and the lower electrode layer 211.

In other embodiments, the semiconductor structure does not include a buffer layer.

Fig. 5 to 7 are schematic diagrams illustrating the operation of the semiconductor structure according to the embodiment of the present invention.

It should be noted that fig. 5 to fig. 7 schematically show the magnetic moment directions of the switching enhancement layer 231 and the magnetic tunnel junction 300 when the magnetic tunnel junction 300 is a perpendicular anisotropic magnetic tunnel junction, and when the magnetic tunnel junction 300 is an in-plane anisotropic magnetic tunnel junction, the working principle of the semiconductor structure is the same as that when the magnetic tunnel junction 300 is a perpendicular anisotropic magnetic tunnel junction, and the description thereof is omitted here.

Referring to fig. 5, fig. 5 schematically shows an initial state of the semiconductor structure. When data is not written, i.e., when no applied bias voltage is applied to the piezoelectric layer 221, the magnetic moment direction of the switching enhancement layer 231 is parallel to the magnetic moment direction of the magnetic tunnel junction 300.

Specifically, at this time, the magnetic moment directions of the flip enhancement layer 231 are parallel to the magnetic moment directions of the first magnetic film 301, the tunneling layer 302, and the second magnetic film 303, respectively.

Referring to fig. 6 and 7, fig. 6 schematically shows a state of the semiconductor structure during writing data, and fig. 7 schematically shows a state of the semiconductor structure after completing writing data. When writing data, an applied bias voltage is applied to the upper electrode layer 251 and the piezoelectric layer 221. The piezoelectric layer 221 can be stressed by an applied bias voltage, and the magnetization direction of the switching enhancement layer 231 is switched by 90 degrees by the stress, that is, the magnetization direction of the switching enhancement layer 231 is perpendicular to the magnetization direction of the magnetic tunnel junction 300, so that the switching enhancement layer 231 can provide an additional bias magnetic field for the magnetic tunnel junction 300 when data is written.

Specifically, on the one hand, a bias magnetic field is applied to the magnetic tunnel junction 300 by an applied bias voltage, and on the other hand, an additional bias magnetic field is applied to the magnetic tunnel junction 300 by the switching enhancement layer 231 whose magnetic moment direction has been switched by 90 degrees, so that the magnetic moment direction of the first magnetic film 301 as a free layer is switched by 180 degrees, and data writing is completed.

After the data writing is completed, the semiconductor structure is again in a state where no bias voltage is applied to the upper electrode layer 251 and the piezoelectric layer 221, and at this time, the piezoelectric layer 221 does not generate stress (the piezoelectric layer 221 returns to its original state), so the magnetic moment direction of the flip enhancement layer 231 returns to the magnetic moment direction of the flip enhancement layer 231 in the initial state of the semiconductor structure, and at this time, the magnetic moment direction of the flip enhancement layer 231 is again parallel to the magnetic moment direction of the magnetic tunnel junction 300.

Because the semiconductor structure comprises the piezoelectric layer 221 positioned between the inversion enhancement layer 231 and the lower electrode layer 211, when data is written, the piezoelectric layer 221 can generate stress through an applied bias voltage, and the magnetic moment direction of the inversion enhancement layer 231 is inverted by 90 degrees through the stress, namely, the magnetic moment direction of the inversion enhancement layer 231 is perpendicular to the magnetic moment direction of the magnetic tunnel junction 300, so that the inversion enhancement layer 231 can provide an additional bias magnetic field for the magnetic tunnel junction 300 when data is written, and write power consumption is reduced; meanwhile, when data is not written, due to the fact that no bias voltage is applied, stress generated by the piezoelectric layer 221 disappears, the magnetic moment direction of the flip enhancement layer 231 is flipped by 90 degrees again, namely the magnetic moment direction of the flip enhancement layer 231 returns to a state parallel to the magnetic moment direction of the magnetic tunnel junction 300, and the flip enhancement layer 231 does not generate a bias magnetic field influencing the magnetic moment direction of the first magnetic film 301, so that influence of the flip enhancement layer 231 on the magnetic moment direction of the first magnetic film 301 can be reduced when data is not written, and reliability and stability of the magnetic random access memory are improved. In summary, the switching enhancement layer 231 and the piezoelectric layer 221 can improve the reliability and stability of the magnetic random access memory while reducing the writing power consumption of the magnetic random access memory.

It should be noted that, for the convenience of understanding, fig. 5 to 7 only schematically show a magnetic moment direction of the magnetization direction of the magnetic tunnel junction of the magnetization direction of the magnetic tunnel junction of the magnetization direction of the magnetic tunnel junction structure of the magnetization direction of the magnetic tunnel junction structure of the magnetic layer 231 of the magnetic tunnel junction structure of the magnetic tunnel junction 300 of the magnetic tunnel junction structure of fig. 5 and the.

Fig. 8 to 10 are schematic structural views of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 8, a substrate 400 is provided.

In this embodiment, the substrate 400 has a device layer (not shown) therein. The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

The material of the substrate 400 includes a semiconductor material.

In this embodiment, the material of the substrate 400 includes silicon.

Subsequently, a lower electrode layer is formed on the surface of the substrate 400; forming a magnetic tunnel junction on the surface of the lower electrode layer; forming a turnover enhancement layer on the surface of the magnetic tunnel junction; forming a piezoelectric layer on the surface of the overturning enhancement layer, wherein when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction; and forming an upper electrode layer on the surface of the piezoelectric layer. Please refer to fig. 9 to 10 for a process of forming the lower electrode layer, the piezoelectric layer, the inversion enhancing layer, the magnetic tunnel junction, and the upper electrode layer.

Referring to fig. 9, a bottom electrode material layer 410 is formed on the surface of the substrate 400; forming a magnetic tunnel junction material layer 420 on the surface of the lower electrode material layer 410; forming a switching enhancement material layer 430 on the surface of the magnetic tunnel junction material layer 420; forming a piezoelectric material layer 440 on the surface of the inversion enhancing material layer 430; forming an upper electrode material layer 450 on the surface of the piezoelectric material layer 440; a patterned layer 460 is formed on the surface of the upper electrode material layer 450.

The lower electrode material layer 410 provides material for forming a lower electrode layer.

In the present embodiment, the process of forming the lower electrode material layer 410 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The magnetic tunnel junction material layer 420 provides a material for forming a magnetic tunnel junction.

In this embodiment, the magnetic tunnel junction material layer 420 includes: a first magnetic material layer 421 on the surface of the lower electrode material layer 410, a tunneling material layer 422 on the surface of the first magnetic material layer 421, and a second magnetic material layer 423 on the surface of the tunneling material layer 422.

In this embodiment, the process of forming the first magnetic material layer 421, the tunneling material layer 422, and the second magnetic material layer 423 includes: a chemical vapor deposition process or an atomic layer deposition process.

The first magnetic material layer 421 provides a material for forming a first magnetic film, the second magnetic material layer 423 provides a material for forming a second magnetic film, and the tunneling material layer 422 provides a material for forming a tunneling layer.

The layer of turn-up enhancement material 430 provides material for forming the turn-up enhancement layer.

In the present embodiment, the process of forming the flip enhanced material layer 430 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The layer of piezoelectric material 440 provides material for forming a piezoelectric layer.

In the present embodiment, the process of forming the piezoelectric material layer 440 includes an electroplating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

The upper electrode material layer 450 provides material for forming an upper electrode layer.

In the present embodiment, the process of forming the upper electrode material layer 450 includes a plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, a seed layer material layer 490 is formed on the surface of the lower electrode material layer 410 before the magnetic tunnel junction material film 420 is formed.

The seed layer material layer 490 provides material for forming a seed layer. The seed layer can enable the crystal lattices between the magnetic tunnel junction and the lower electrode layer to be more matched, so that the performance of the magnetic random access memory is improved.

In this embodiment, a first insertion material layer 470 is formed on the surface of the mtj material film 420 before the inversion enhancement material layer 430 is formed.

The first interposer material layer 470 provides material for forming a first interposer layer.

In the present embodiment, the process of forming the first insertion material layer 470 includes a spin coating process, a plating process, or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, before the piezoelectric material layer 440 is formed, a second insertion material layer 480 is formed on the surface of the inversion enhancement material layer 430.

The second interposer material layer 480 provides material for forming a second interposer layer.

In the present embodiment, the process of forming the second insertion material layer 480 includes an electroplating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

Referring to fig. 10, the upper electrode material layer 450, the piezoelectric material layer 440, the inversion enhancing material layer 430, the magnetic tunnel junction material layer 420 and the lower electrode material layer 410 are etched by using the patterning layer 460 as a mask until the surface of the substrate 400 is exposed, so as to form an upper electrode layer 451, a magnetic tunnel junction 500, an inversion enhancing layer 431, a piezoelectric layer 441 and a lower electrode layer 411.

Specifically, in the present embodiment, the lower electrode material layer 410 is etched to form a lower electrode layer 411 on the surface of the substrate 400; etching the magnetic tunnel junction material layer 420 to form a magnetic tunnel junction 500 on the surface of the lower electrode layer 411; etching the switching enhancement material layer 430 to form a switching enhancement layer 431 on the surface of the magnetic tunnel junction 500; etching the piezoelectric material layer 440 to form a piezoelectric layer 441 on the surface of the inversion enhancement layer 431; the upper electrode material layer 450 is etched to form an upper electrode layer 451 on the surface of the piezoelectric layer 441.

The piezoelectric layer 441 is used to control the magnetic moment direction of the flip enhancement layer 431.

When no applied voltage is applied to the piezoelectric layer 441, the direction of the magnetic moment of the switching enhancement layer 431 is parallel to the direction of the magnetic moment of the magnetic tunnel junction 500.

In this embodiment, the process of etching the upper electrode material layer 450, the magnetic tunnel junction material layer 420, the switching enhancement material layer 430, the piezoelectric material layer 440, and the lower electrode material layer 410 includes a reactive ion etching process or an ion beam etching process.

In this embodiment, the material of the lower electrode layer 411 includes tantalum, aluminum, or copper.

In this embodiment, the material of the piezoelectric layer 441 includes: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

In the embodiment, the thickness of the piezoelectric layer 441 ranges from 1 nm to 2 nm, and when the thickness of the piezoelectric layer 441 ranges from 1 nm to 2 nm, the magnetic moment direction of the turning enhancement layer 431 can be better controlled.

In other embodiments, the thickness of the piezoelectric layer 441 is between 0 nm and 1 nm, or greater than 2 nm and less than 10 nm.

In this embodiment, the material of the piezoelectric layer 441 is a piezoelectric material.

In this embodiment, the flip enhancement layer 431 includes: 1 or more layers of inversion enhancement films (not shown) stacked in the substrate normal direction.

When the inversion enhancement layer 431 includes 2 or more layers of the inversion enhancement film, the inversion enhancement layer 231 further includes a non-magnetic layer (not shown) between adjacent inversion enhancement films.

In this embodiment, the material of the rollover reinforcement layer 431 includes one or more of cofe, cofeb, or nife in combination.

In this embodiment, the direction of the magnetic moment of the switching enhancing layer 431 is perpendicular or parallel to the normal direction of the surface of the substrate 400.

In the present embodiment, the magnetic tunnel junction 500 includes: a first magnetic film 501 on the surface of the lower electrode layer 411; a tunneling layer 502 on the surface of the first magnetic film 501; and a second magnetic film 503 on the surface of the tunneling layer 502.

In this embodiment, the second magnetic film 503 is a free layer, and the first magnetic film 501 is a fixed layer.

The material of the first magnetic film 501 includes one or a combination of several of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron, or nickel-iron.

The material of the second magnetic film 503 includes one or a combination of several of iron, cobalt, nickel, cobalt-iron-boron, cobalt-iron, or nickel-iron.

The material of the tunneling layer 502 includes magnesium oxide.

The magnetic tunnel junction 500 may be a perpendicular anisotropic magnetic tunnel junction, or an in-plane anisotropic magnetic tunnel junction.

In the present embodiment, the material of the upper electrode layer 451 includes tantalum, aluminum, or copper.

In this embodiment, the upper electrode material layer 450, the magnetic tunnel junction material layer 420, the inversion enhancement material layer 430, the piezoelectric material layer 440, and the lower electrode material layer 410 are etched using the patterning layer 460 as a mask, and simultaneously, the first insertion material layer 470, the second insertion material layer 480, and the seed layer material layer 490 are etched to form a first insertion layer 471, a second insertion layer 481, and a seed layer 491.

Specifically, in the present embodiment, a first insertion layer 471 is formed between the magnetic tunnel junction 500 and the switching enhancement layer 431, a second insertion layer 481 is formed between the switching enhancement layer 431 and the piezoelectric layer 441, and a seed layer 491 is formed between the magnetic tunnel junction 500 and the lower electrode layer 411.

In this embodiment, the material of the first insertion layer 471 includes a non-magnetic metal material or a non-magnetic medium material, and the non-magnetic metal material includes ruthenium or tantalum.

In other embodiments, the first insertion layer is not formed.

In the present embodiment, the material of the second insertion layer 481 includes a nonmagnetic metal material including ruthenium or tantalum.

In other embodiments, the second insertion layer is not formed.

In other embodiments, no seed layer is formed.

It should be noted that the patterning layer 460 is removed by being worn out during the etching process for forming the upper electrode layer 451, the magnetic tunnel junction 500, the inversion enhancement layer 431, the piezoelectric layer 441 and the lower electrode layer 411.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the method for forming a semiconductor structure, please refer to fig. 10, which includes: a substrate 400; a lower electrode layer 411 on the surface of the substrate 400; a magnetic tunnel junction 500 on the surface of the lower electrode layer 411; an upper electrode layer 451 on a surface of the magnetic tunnel junction 500; a switching enhancement layer 431 located between the magnetic tunnel junction 500 and the upper electrode layer 451; and a piezoelectric layer 441 positioned between the switching enhancement layer 431 and the upper electrode layer 451, wherein the piezoelectric layer 441 is used for controlling a magnetic moment direction of the switching enhancement layer 431, and the magnetic moment direction of the switching enhancement layer 431 is parallel to the magnetic moment direction of the magnetic tunnel junction 500 when no external voltage is applied to the piezoelectric layer 441.

The material of the substrate 400 includes a semiconductor material.

In this embodiment, the material of the substrate 400 includes silicon.

In this embodiment, the first magnetic film 501 is a fixed layer, and the second magnetic film 503 is a free layer.

The material of the tunneling layer 502 includes magnesium oxide.

In this embodiment, the semiconductor structure further includes: a first insertion layer 471 located between the magnetic tunnel junction 500 and the switching enhancement layer 431.

Since the magnetic tunnel junction 500 and the switching enhancement layer 431 have the first insertion layer 471 therebetween, the coupling between the switching enhancement layer 431 and the magnetic tunnel junction 500 can be reduced.

The material of the first insertion layer 471 includes a non-magnetic metal material or a non-magnetic medium material, and the non-magnetic metal material includes ruthenium or tantalum.

In this embodiment, the semiconductor structure further includes: a second insertion layer 481 positioned between the flip enhancement layer 431 and the piezoelectric layer 441.

Since the second insertion layer 481 is further arranged between the inversion enhancement layer 431 and the piezoelectric layer 441, on one hand, the inversion enhancement layer 431 made of a magnetic material can be isolated from the piezoelectric layer 441 made of a non-magnetic material through the second insertion layer 481, so that mutual influence of diffusion and the like between the material of the inversion enhancement layer 431 and the material of the piezoelectric layer 441 is reduced, and on the other hand, the inversion enhancement layer 431 can be better enabled to form a magnetic moment in a specific direction through the second insertion layer 481.

The material of the second insertion layer 481 includes a nonmagnetic metallic material including ruthenium or tantalum.

In this embodiment, the semiconductor structure further includes: a seed layer 491 located between the magnetic tunnel junction 500 and the lower electrode layer 411.

In other embodiments, the semiconductor structure does not include a seed layer.

It should be noted that fig. 11 to 13 schematically show the magnetic moment directions of the switching enhancement layer 431 and the magnetic tunnel junction 500 when the magnetic tunnel junction 500 is an in-plane anisotropic magnetic tunnel junction, and when the magnetic tunnel junction 500 is a perpendicular anisotropic magnetic tunnel junction, the working principle of the semiconductor structure is the same as that when the magnetic tunnel junction 500 is an in-plane anisotropic magnetic tunnel junction, and the description thereof is omitted here.

Referring to fig. 11, fig. 11 schematically shows an initial state of a semiconductor structure. When no data is written, i.e. no applied bias voltage is applied to the piezoelectric layer 441, the direction of the magnetic moment of the switching enhancement layer 431 is parallel to the direction of the magnetic moment of the magnetic tunnel junction 500.

Specifically, at this time, the magnetic moment directions of the flip enhancement layer 431 are parallel to the magnetic moment directions of the first magnetic film 501, the tunneling layer 502 and the second magnetic film 503, respectively.

Referring to fig. 12 and 13, fig. 12 schematically shows a state of the semiconductor structure during writing data, and fig. 13 schematically shows a state of the semiconductor structure after completion of writing data. When writing data, an applied bias voltage is applied to the upper electrode layer 451 and the piezoelectric layer 441. The piezoelectric layer 441 can be stressed by an applied bias voltage, and the magnetization direction of the switching enhancement layer 431 can be switched by 90 degrees by the stress, that is, the magnetization direction of the switching enhancement layer 431 is perpendicular to the magnetization direction of the magnetic tunnel junction 500, so that the switching enhancement layer 431 can provide an additional bias magnetic field for the magnetic tunnel junction 500 when writing data.

Specifically, on the one hand, a bias magnetic field is applied to the magnetic tunnel junction 500 by an applied bias voltage, and on the other hand, an additional bias magnetic field is applied to the magnetic tunnel junction 500 by the switching enhancement layer 431 whose magnetic moment direction has been switched by 90 degrees, so that the magnetic moment direction of the second magnetic film 503 as a free layer is switched by 180 degrees, and data writing is completed.

After the data writing is completed, the semiconductor structure is again in a state where no bias voltage is applied to the upper electrode layer 451 and the piezoelectric layer 441, at this time, the piezoelectric layer 441 no longer generates stress (the piezoelectric layer 441 returns to its original state), so the magnetic moment direction of the flip enhancement layer 431 returns to the magnetic moment direction of the flip enhancement layer 431 in the initial state of the semiconductor structure, and at this time, the magnetic moment direction of the flip enhancement layer 431 is again parallel to the magnetic moment direction of the magnetic tunnel junction 500.

Since the semiconductor structure includes the piezoelectric layer 441 located between the flip enhancement layer 431 and the upper electrode layer 451, when data is written, the piezoelectric layer 441 can be stressed by an applied bias voltage, and the magnetic moment direction of the flip enhancement layer 431 can be flipped by 90 degrees by the stress, that is, the magnetic moment direction of the flip enhancement layer 431 is perpendicular to the magnetic moment direction of the magnetic tunnel junction 500, so that the flip enhancement layer 431 can provide an additional bias magnetic field for the magnetic tunnel junction 500 when data is written, thereby reducing the write power consumption; meanwhile, when data is not written, due to the fact that no bias voltage is applied, stress generated by the piezoelectric layer 441 disappears, so that the magnetic moment direction of the flip enhancement layer 431 is flipped again by 90 degrees, namely the magnetic moment direction of the flip enhancement layer 431 returns to a state parallel to the magnetic moment direction of the magnetic tunnel junction 500, and the flip enhancement layer 431 does not generate a bias magnetic field influencing the magnetic moment direction of the second magnetic film 503, therefore, when data is not written, the influence of the flip enhancement layer 431 on the magnetic moment direction of the second magnetic film 503 can be reduced, and the reliability and the stability of the magnetic random access memory are improved. In summary, the switching enhancement layer 431 and the piezoelectric layer 441 can reduce the write power consumption of the magnetic random access memory and improve the reliability and stability of the magnetic random access memory.

It should be noted that fig. 11 to 13 only schematically show a magnetic moment direction of the tunneling enhancement layer 431 and the magnetic tunnel junction 500 for easy understanding, and the magnetic moment directions of the tunneling enhancement layer 431 and the magnetic tunnel junction 500 may be opposite to the magnetic moment directions in fig. 11 to 13.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate;

a lower electrode layer on the surface of the substrate;

a magnetic tunnel junction located on the surface of the lower electrode layer;

an upper electrode layer on a surface of the magnetic tunnel junction;

an inversion enhancement layer located between the magnetic tunnel junction and the upper electrode layer or between the magnetic tunnel junction and the lower electrode layer;

the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer, when the overturning enhancement layer is positioned between the magnetic tunnel junction and the upper electrode layer, the piezoelectric layer is positioned between the overturning enhancement layer and the upper electrode layer, when the overturning enhancement layer is positioned between the magnetic tunnel junction and the lower electrode layer, the piezoelectric layer is positioned between the overturning enhancement layer and the lower electrode layer, and when no external voltage is applied to the piezoelectric layer, the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction.

2. The semiconductor structure of claim 1, wherein the material of the piezoelectric layer is a piezoelectric material.

3. The semiconductor structure of claim 2, wherein a material of the piezoelectric layer comprises: cadmium sulfide, lead magnesium niobate-lead titanate, lead zirconate titanate or barium titanate.

4. The semiconductor structure of claim 1, wherein the thickness of the piezoelectric layer is greater than 0 nanometers and the thickness of the piezoelectric layer is less than 10 nanometers.

5. The semiconductor structure of claim 1, wherein the direction of the magnetic moment of the switching enhancement layer is perpendicular or parallel to a normal direction of the substrate surface.

6. The semiconductor structure of claim 1, further comprising: a first insertion layer between the switching enhancement layer and the magnetic tunnel junction.

7. The semiconductor structure of claim 1, further comprising: a second interposer layer between the flip enhancement layer and the piezoelectric layer.

8. The semiconductor structure of claim 1, wherein when a switching enhancement layer is located between a magnetic tunnel junction and an upper electrode layer, the semiconductor structure further comprises: a seed layer located between the lower electrode layer and the magnetic tunnel junction.

9. The semiconductor structure of claim 1, wherein when the switching enhancement layer is located between the magnetic tunnel junction and the lower electrode layer, the semiconductor structure further comprises: a buffer layer between the lower electrode layer and the piezoelectric layer.

10. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a lower electrode layer on the surface of the substrate;

forming a piezoelectric layer on the surface of the lower electrode layer;

forming an overturning enhancement layer on the surface of the piezoelectric layer, wherein the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer;

forming a magnetic tunnel junction on the surface of the overturning enhancement layer, wherein the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction when no external voltage is applied to the piezoelectric layer;

and forming an upper electrode layer on the surface of the magnetic tunnel junction.

11. The method of forming a semiconductor structure of claim 10, further comprising: a first insertion layer is formed between the magnetic tunnel junction and the switching enhancement layer.

12. The method of forming a semiconductor structure of claim 10, further comprising: a second interposer layer is formed between the flip enhancing layer and the piezoelectric layer.

13. The method of forming a semiconductor structure of claim 10, further comprising: a buffer layer is formed between the piezoelectric layer and the lower electrode layer.

14. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a lower electrode layer on the surface of the substrate;

forming a magnetic tunnel junction on the surface of the lower electrode layer;

forming a turnover enhancement layer on the surface of the magnetic tunnel junction;

forming a piezoelectric layer on the surface of the overturning enhancement layer, wherein the piezoelectric layer is used for controlling the magnetic moment direction of the overturning enhancement layer, and the magnetic moment direction of the overturning enhancement layer is parallel to the magnetic moment direction of the magnetic tunnel junction when no external voltage is applied to the piezoelectric layer;

and forming an upper electrode layer on the surface of the piezoelectric layer.

15. The method of forming a semiconductor structure of claim 14, further comprising: a first insertion layer is formed between the switching enhancement layer and the magnetic tunnel junction.

16. The method of forming a semiconductor structure of claim 14, further comprising: a second intervening layer is formed between the piezoelectric layer and the flip reinforcement layer.

17. The method of forming a semiconductor structure of claim 14, further comprising: a seed layer is formed between the magnetic tunnel junction and the lower electrode layer.