CN113838438B - Data processing method and system for screen splicing, electronic device and storage medium - Google Patents
Data processing method and system for screen splicing, electronic device and storage medium Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
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- G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
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Abstract
The embodiment of the invention discloses a screen-splicing data processing method, a screen-splicing data processing system, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring data to be displayed bit by bit; carrying out binarization processing on bitwise data of data to be displayed; storing one-bit data subjected to binarization processing of data to be displayed into a storage area, wherein the storage area is composed of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen; after all data to be displayed are obtained, each bit of data to be displayed is subjected to binarization processing and stored in a storage area, an output enabling clock signal of the field programmable gate array is obtained; and when the output enabling clock signal reaches a rising edge, outputting data once from each random access memory in the storage area until the output enabling clock signal reaches a first preset number of times, and completely outputting the data in each random access memory to completely display the data to be displayed.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a screen-splicing data processing method and system, an electronic device, and a storage medium.
Background
Along with the development of the electronic display industry, the application of display screen is also more and more extensive, and under some circumstances, need use a plurality of display module assembly to splice, makes up into a display screen and shows data.
When splicing a plurality of display module groups into a display screen, the data that every display module group shows are inequality, consequently make the display screen can show required data.
However, in the display screen formed by splicing a plurality of existing display modules, the signal synchronism among the plurality of display modules needs to be improved.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, a system, a computer device and a storage medium for processing data by screen splicing.
A method of data processing for screen-splicing, the method comprising:
acquiring data to be displayed bit by bit; carrying out binarization processing on the bitwise data of the data to be displayed; storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen; acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed, and storing the data into the storage area, and acquiring an output enabling clock signal of the field programmable gate array; and when the output enabling clock signal reaches a rising edge, outputting data once from each random access memory in the storage area until the output enabling clock signal reaches a first preset number of times, and completely outputting the data in each random access memory to completely display the data to be displayed.
The bit-by-bit acquisition of the data to be displayed comprises the following steps: acquiring an input enabling signal of a field programmable gate array; and when the input enabling signal reaches a rising edge, acquiring one-bit data of the data to be displayed from a data source until the output enabling clock signal reaches a second preset number of times, and acquiring the complete data to be displayed.
Wherein, the storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area comprises the following steps: judging a display module for correspondingly displaying the one-bit data subjected to the binarization processing of the data to be displayed; and storing the one-bit data subjected to the binarization processing of the data to be displayed into the corresponding random access memory according to the corresponding relation between the random access memory and the display module.
The display module for judging the corresponding display of the one-bit data subjected to the binarization processing of the data to be displayed comprises: acquiring one-bit data which needs to be stored and is subjected to binarization processing on data to be displayed currently, acquiring the horizontal resolution of a display module and the number of the display modules from the bit value of the data to be displayed; dividing said horizontal resolution by said bit value to obtain a quotient; and using the quotient value to complement the number of the display modules to obtain a split screen value, wherein the split screen value is the sequencing value of the display modules correspondingly displayed by the one-bit data subjected to the binarization processing of the data to be displayed.
Wherein outputting data from each of the random access memories of the memory area once when the output enable clock signal reaches a rising edge comprises: acquiring the storage sequence of the data to be displayed in the random access memory when the part subjected to the binarization processing of the data to be displayed is stored in a storage area; and outputting data once from each of the random access memories in the memory areas by using the storing sequence as an output sequence when the output enable clock signal reaches a rising edge.
When the data to be displayed is stored in the storage area, the storage mode is single-thread serial input; and when the data to be displayed is output from the storage area, the output mode is multithread serial output.
A tiled data processing system, comprising:
the data acquisition module is used for acquiring the data to be displayed bit by bit; the data processing module is used for carrying out binarization processing on the bitwise data of the data to be displayed; the data storage module is used for storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area, the storage area is composed of a preset number of random access memories, and the random access memories are in one-to-one correspondence with the display modules spliced into the display screen; the signal acquisition module is used for acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed and storing the data into the storage area, and then acquiring an output enabling clock signal of the field programmable gate array; and the data output module is used for outputting data once from each random access memory in the storage area when the output enabling clock signal reaches a rising edge until the data in each random access memory are all output after the output enabling clock signal reaches a first preset number of times, and completely displaying the data to be displayed.
An electronic device comprising a memory and a processor, the memory storing a program that, when executed by the processor, causes the processor to perform the steps of:
acquiring data to be displayed bit by bit; carrying out binarization processing on the bitwise data of the data to be displayed; storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen; acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed, and storing the data into the storage area, and acquiring an output enabling clock signal of the field programmable gate array; and when the output enabling clock signal reaches a rising edge, outputting data once from each random access memory in the storage area until the output enabling clock signal reaches a first preset number of times, and then completely outputting the data in each random access memory to completely display the data to be displayed.
A computer-readable storage medium storing a program which, when executed by a processor, causes the processor to perform the steps of:
acquiring data to be displayed bit by bit; carrying out binarization processing on the bitwise data of the data to be displayed; storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen; after all the data to be displayed are obtained, each bit of data of the data to be displayed is subjected to binarization processing and stored in the storage area, an output enabling clock signal of the field programmable gate array is obtained; and when the output enabling clock signal reaches a rising edge, outputting data once from each random access memory in the storage area until the output enabling clock signal reaches a first preset number of times, and completely outputting the data in each random access memory to completely display the data to be displayed.
The embodiment of the invention has the following beneficial effects:
when the data to be displayed are output from the storage area, the output enable clock signal serves as a trigger signal for outputting the data to be displayed every time when reaching a rising edge, the data output every time can have the same trigger time, and therefore signal synchronism among a plurality of display modules spliced into a display screen is good.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Wherein:
FIG. 1 is a schematic flow chart diagram of a data processing method for screen splicing in one embodiment;
FIG. 2 is a schematic flow chart illustrating bit-by-bit acquisition of data to be displayed in the data processing method for screen splicing in one embodiment;
FIG. 3 is a schematic diagram illustrating a process of storing a single bit of data subjected to binarization processing of data to be displayed into a storage area in an embodiment of a screen-splicing data processing method;
FIG. 4 is a schematic flow chart illustrating a process of determining a display module for displaying a corresponding one-bit data after binarization processing of data to be displayed in an embodiment of a screen-splicing data processing method;
FIG. 5 is a flowchart illustrating a data output from each RAM in a memory area once when an output enable clock signal reaches a rising edge in the data processing method for screen-splicing according to an embodiment;
FIG. 6 is a block diagram of a data processing system that tiles screens in one embodiment;
FIG. 7 is a block diagram of a computer device in one embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In one embodiment, as shown in FIG. 1, a method for data processing by screen-splicing is provided. The method can be applied to both the terminal and the server, and this embodiment is exemplified by being applied to the terminal. The method specifically comprises the following steps:
s101, acquiring data to be displayed bit by bit;
s102, carrying out binarization processing on bitwise data of data to be displayed;
s103, storing the binary processed one-bit data of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories correspond to the display modules spliced into the display screen one by one;
s104, after all the data to be displayed are acquired, each bit of the data to be displayed is subjected to binarization processing and stored in a storage area, an output enabling clock signal of the field programmable gate array is acquired;
and S105, outputting data once from each random access memory in the storage area when the output enabling clock signal reaches a rising edge until the output enabling clock signal reaches a first preset number of times, and completely outputting the data in each random access memory to completely display the data to be displayed.
In step S101, the data source of the data to be displayed may be a memory, such as a usb disk, a removable hard disk, a memory card, or a network device, such as a computer, a mobile phone, or the like; and the data to be displayed is taken out from the memory by bit-by-bit acquisition, wherein the size of each bit of data is 8 bits in general.
In step S102, each bit of the acquired data to be displayed is 8 bits, and the display module to be driven is controlled by 1bit of monochrome data, so that each bit of the data to be displayed needs to be binarized to obtain 1bit of data to be displayed; in this embodiment, in order to reduce the processing time of the data, immediately after one-bit data of the data to be displayed is acquired, step S102 is executed to perform binarization processing on the bitwise data.
In step S103, the second preset number of the random access memories in the storage area is the same as the number of the display modules spliced into the screen, the random access memories correspond to the display modules spliced into the screen one by one, and one random access memory stores data of one display module.
In step S104, each bit of data to be displayed is acquired, binarized, and stored in a storage area, so that the storage of the data to be displayed is completed, and at this time, an output enable clock signal is acquired and the output enable clock signal is a clock signal of the fpga itself, so that only the acquisition is needed.
In step S105, a rising edge of the output enable clock signal can be used as a trigger signal, and when the rising edge of the output enable clock signal is output, data is triggered and output once, and after the output enable clock signal reaches a first preset number of times, all data in the random access memory can be output, and the data to be displayed is completely displayed on each display module.
When the data to be displayed are output from the storage area, the output enable clock signal serves as a trigger signal for outputting the data to be displayed every time when reaching a rising edge, the data output every time can have the same trigger time, and therefore signal synchronism among a plurality of display modules spliced into a display screen is good.
As shown in fig. 2, in an embodiment, the step S101, obtaining the data to be displayed bit by bit includes:
s1011, acquiring an input enabling signal of the field programmable gate array;
and S1012, when the input enable signal reaches a rising edge, acquiring one-bit data of the data to be displayed from the data source until the output enable clock signal reaches a second preset number of times, and acquiring complete data to be displayed.
In this embodiment, when the data to be displayed is input into the storage area, the input enable signal is used as the trigger signal for inputting the data to be displayed each time when the input enable signal reaches a rising edge, so that the data input each time has the same trigger time, and the situation of storage confusion when the data to be displayed is stored is reduced.
As shown in fig. 3, in one embodiment, storing the one-bit data subjected to the binarization process of the data to be displayed into the storage area in step S103 includes:
s1031, judging a display module which correspondingly displays the binary processed one-bit data of the data to be displayed;
s1032, storing the one-bit data subjected to the binarization processing of the data to be displayed into the corresponding random access memory according to the corresponding relation between the random access memory and the display module.
In this embodiment, a 10-tiled display module (resolution 1000 × 1000) is taken as an example, because the encoding sequence of the picture pixels by the picture encoding software is in a zigzag manner, i.e. from left to right, from top to bottom, therefore, the data of the 1 st pixel point to the 100 th pixel point, the data of the 1001 st pixel point to the 1100 st pixel point … … and the data of the 999001 th pixel point to the 999100 th pixel point are written into the random access memory, and the data of the hundred thousand pixel points are stored into the first ram, and the data of the 101 th pixel point to the 200 th pixel point, the data of the 1101 th pixel point to the 1200 th pixel point … …, the data of the 999101 th pixel point to the 999200 th pixel point are stored into a second random access memory … …, and so on, so that the data of one random access memory corresponds to the display data of one vertical split screen.
In this embodiment, since the display modules correspond to the random access memory one to one, the display module that determines that the one-bit data subjected to the binarization processing of the data to be displayed corresponds to the display module that is to be displayed can obtain the random access memory into which the one-bit data needs to be stored, so that the data to be displayed is stored in the storage area in order, and the storage disorder is reduced.
As shown in fig. 4, in an embodiment, in step S1031, the display module determining that the one-bit data subjected to the binarization processing of the data to be displayed is correspondingly displayed includes:
s10311, acquiring one-bit data which needs to be stored currently and is subjected to binarization processing of the data to be displayed, acquiring the horizontal resolution of the display modules and the number of the display modules from the bit value of the data to be displayed;
s10312, subtracting one by using the bit value, and dividing by the horizontal resolution to obtain a quotient;
and S10313, using the quotient value to carry out complementation on the number of the display modules to obtain a split screen value, wherein the split screen value is the ranking value of the display modules correspondingly displayed by the one-bit data subjected to the binarization processing of the data to be displayed.
In this embodiment, the number of bits of the data to be displayed is much greater than that of the random access memory, so that one random access memory needs to store multiple bits of data to be displayed, and according to the calculation rules in steps S10311 to S10313, the corresponding relationship between the bit value of each bit of data to be displayed and the ordering value of the display module can be calculated.
As shown in fig. 5, in one embodiment, outputting data once from each random access memory of the memory area when the output enable clock signal reaches a rising edge in step S105 includes:
s1051, obtaining the storing sequence of the data to be displayed in the random access memory when the part to be displayed data binaryzation processed is stored in the storage area;
s1052, when the output enable clock signal reaches a rising edge, the storage sequence is used as an output sequence, and data is output once from each random access memory in the storage area.
In this embodiment, it is necessary to determine an output sequence according to a storage sequence of the data to be displayed, so as to ensure accuracy of outputting the data to be displayed.
In this embodiment, still taking a 10-tiled display module (resolution is 1000 × 1000) as an example, for a 10-tiled display module with a resolution of 1000 × 1000, when the first random access memory outputs data from bit 1 to bit 100, the tenth random access memory outputs data from bit 900 to bit 1000, and when ten random access memories output 100 data at the same time, 1000 data (i.e., data of one row) can be stored in the driver chip, and when ten random access memories output 10 ten thousand data at the same time, 100 ten thousand data (i.e., one frame) can be stored in the driver chip. Of course, this is the normal case, for the display screen of "Z" type stored data, such output sequence is not problematic, but some display screens have data storage protocol of "S" type, if the random access memory also outputs data in this way, the display pattern will show mirror image effect, so for this case, each random access memory also outputs data in "S" type data output sequence, that is, starting from 100 bits, decreasing to 1bit, starting from 200 bits, decreasing to 101 bits … …, starting from 100000 bits, and decreasing to 99901 bits.
In one embodiment, when step S103 is executed to store the data to be displayed in the storage area, the storage mode is single-threaded serial input; when the data to be displayed is output from the memory area in executing step S105, the output mode is multi-thread serial output.
In this embodiment, since step S101 and step S102 process one bit of data, when step S103 is executed, a single thread is used, and there is no need to open multiple threads, which reduces the resource occupation of the thread; in step S105, when the output enable clock signal reaches a rising edge, each of the random access memories outputs data once, and the multithreading is used, so that the output speed can be increased, and the signal synchronization among the plurality of display modules is better.
As shown in fig. 6, in one embodiment, there is further provided a screen-pieced data processing system, including: the device comprises a data acquisition module 1, a data processing module 2, a data storage module 3, a signal acquisition module 4 and a data output module 5; the data acquisition module is used for acquiring data to be displayed bit by bit; the data processing module is used for carrying out binarization processing on the bitwise data of the data to be displayed; the data storage module is used for storing one-bit data subjected to binarization processing of data to be displayed into a storage area, the storage area is composed of a preset number of random access memories, and the random access memories are in one-to-one correspondence with the display modules spliced into the display screen; the signal acquisition module is used for acquiring all data to be displayed, carrying out binarization processing on each bit of data to be displayed and storing the data into a storage area, and then acquiring an output enabling clock signal of the field programmable gate array; the data output module is used for outputting data once from each random access memory in the storage area when the output enabling clock signal reaches a rising edge until the output enabling clock signal reaches a first preset number of times, and then outputting all the data in each random access memory to completely display the data to be displayed.
In this embodiment, when the data to be displayed is output from the storage area, the output enable clock signal is used as a trigger signal for outputting the data to be displayed each time when reaching a rising edge, so that the data output each time has the same trigger time, and therefore, the signal synchronism among a plurality of display modules spliced into a display screen is good.
In one embodiment, the data acquisition module 1 comprises: an input enable signal acquisition unit and a bit-by-bit data acquisition unit; the input enabling signal acquisition unit is used for acquiring an input enabling signal of the field programmable gate array; the bit-by-bit data acquisition unit is used for acquiring one-bit data of the data to be displayed from the data source when the input enabling signal reaches a rising edge until the output enabling clock signal reaches a second preset number of times, and then obtaining complete data to be displayed.
In one embodiment, the data storage module 3 comprises: a judging unit and a storage unit; the storage of the one-bit data subjected to the binarization processing of the data to be displayed into the storage area comprises the following steps: the judging unit is used for judging a display module which correspondingly displays the one-bit data subjected to the binarization processing of the data to be displayed; the storage unit is used for storing the one-bit data subjected to the binarization processing of the data to be displayed into the corresponding random access memory according to the corresponding relation between the random access memory and the display module.
In one embodiment, the judging unit includes: acquiring a subunit, a percentage value calculating operator unit and a split screen value calculating operator unit; the acquisition subunit is used for acquiring one-bit data which needs to be stored and is subjected to binarization processing on the data to be displayed currently, acquiring the horizontal resolution of the display module and the number of the display modules according to the bit value of the data to be displayed; the percentage value operator unit is used for dividing the bit value by one, dividing the bit value by the horizontal resolution and then dividing the bit value by one hundred to obtain a percentage value; and the screen division value operator unit is used for multiplying the percentage value by the number of the display modules to obtain a screen division value, and the screen division value is the ranking value of the display modules correspondingly displayed by the one-bit data subjected to the binarization processing of the data to be displayed.
In one embodiment, the data output module 5 includes: a storage sequence acquisition unit and an output unit; the storage sequence acquisition unit is used for acquiring the storage sequence of the data to be displayed in the random access memory when the part subjected to the binarization processing of the data to be displayed is stored in the storage area; the output unit is configured to output the data once from each of the random access memories in the storage area with the storage sequence as an output sequence when the output enable clock signal reaches a rising edge.
FIG. 7 is a diagram illustrating an internal structure of a computer device in one embodiment. The computer device may specifically be a terminal, and may also be a server. As shown in fig. 7, the computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program that, when executed by the processor, causes the processor to implement the age identification method. The internal memory may also have a computer program stored thereon that, when executed by the processor, causes the processor to perform the age identification method. Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, an electronic device is presented, comprising a memory and a processor, the memory storing a program that, when executed by the processor, causes the processor to perform the steps of:
acquiring data to be displayed bit by bit; carrying out binarization processing on the bitwise data of the data to be displayed; storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen; acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed, and storing the data into the storage area, and acquiring an output enabling clock signal of the field programmable gate array; and when the output enabling clock signal reaches a rising edge, outputting data once from each random access memory in the storage area until the output enabling clock signal reaches a first preset number of times, and completely outputting the data in each random access memory to completely display the data to be displayed.
In one embodiment, a computer-readable storage medium is provided, storing a program that, when executed by a processor, causes the processor to perform the steps of:
acquiring data to be displayed bit by bit; carrying out binarization processing on the bitwise data of the data to be displayed; storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen; acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed, and storing the data into the storage area, and acquiring an output enabling clock signal of the field programmable gate array; and when the output enabling clock signal reaches a rising edge, outputting data once from each random access memory in the storage area until the output enabling clock signal reaches a first preset number of times, and completely outputting the data in each random access memory to completely display the data to be displayed.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the program is executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (8)
1. A data processing method for screen splicing is characterized by comprising the following steps:
acquiring data to be displayed bit by bit;
carrying out binarization processing on the bitwise data of the data to be displayed;
storing the binary processed one-bit data of the data to be displayed into a storage area, wherein the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with display modules spliced into a display screen;
acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed, and storing the data into the storage area, and acquiring an output enabling clock signal of the field programmable gate array;
when the output enabling clock signal reaches a rising edge, outputting data from each random access memory of the storage area once until the output enabling clock signal reaches a first preset number of times, and then outputting all the data in each random access memory to completely display the data to be displayed;
wherein, the storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area comprises the following steps:
judging a display module which correspondingly displays the one-bit data subjected to the binarization processing of the data to be displayed;
storing the binary data of the data to be displayed into the corresponding random access memory according to the corresponding relation between the random access memory and the display module;
the display module for judging the corresponding display of the one-bit data subjected to the binarization processing of the data to be displayed comprises:
acquiring one-bit data which needs to be stored and is subjected to binarization processing on data to be displayed currently, acquiring the horizontal resolution of a display module and the number of the display modules from the bit value of the data to be displayed;
dividing said horizontal resolution by said bit value to obtain a quotient;
and obtaining a split-screen value by using the quotient value to complement the number of the display modules, wherein the split-screen value is the ranking value of the display modules correspondingly displayed by the one-bit data to be subjected to the binarization processing of the data to be displayed.
2. The tiled data processing method of claim 1,
the bit-by-bit acquisition of the data to be displayed comprises the following steps:
acquiring an input enabling signal of a field programmable gate array;
and when the input enabling signal reaches a rising edge, acquiring one-bit data of the data to be displayed from a data source until the output enabling clock signal reaches a second preset number of times, and acquiring the complete data to be displayed.
3. The tiled data processing method of claim 1,
outputting data once from each of the random access memories of the memory area when the output enable clock signal reaches a rising edge, comprising:
acquiring the storage sequence of the data to be displayed in the random access memory when the part subjected to the binarization processing of the data to be displayed is stored in a storage area;
and outputting data once from each of the random access memories in the memory areas by using the storing sequence as an output sequence when the output enable clock signal reaches a rising edge.
4. The tiled data processing method of claim 1,
when the data to be displayed is stored in the storage area, the storage mode is single-thread serial input;
and when the data to be displayed is output from the storage area, the output mode is multithread serial output.
5. A tiled data processing system, comprising:
the data acquisition module is used for acquiring the data to be displayed bit by bit;
the data processing module is used for carrying out binarization processing on the bitwise data of the data to be displayed;
the data storage module is used for storing the binary-processed one-bit data of the data to be displayed into a storage area, the storage area consists of a preset number of random access memories, and the random access memories are in one-to-one correspondence with the display modules spliced into the display screen;
the signal acquisition module is used for acquiring all the data to be displayed, carrying out binarization processing on each bit of the data to be displayed and storing the data into the storage area, and then acquiring an output enabling clock signal of the field programmable gate array;
the data output module is used for outputting data once from each random access memory in the storage area when the output enabling clock signal reaches a rising edge until the data in each random access memory are all output after the output enabling clock signal reaches a first preset number of times, and completely displaying the data to be displayed;
the data storage module is specifically configured to:
the step of storing the one-bit data subjected to the binarization processing of the data to be displayed into a storage area comprises the following steps of:
judging a display module which correspondingly displays the one-bit data subjected to the binarization processing of the data to be displayed;
storing the one-bit data subjected to the binarization processing of the data to be displayed into the corresponding random access memory according to the corresponding relation between the random access memory and the display module;
the display module for judging the corresponding display of the one-bit data subjected to the binarization processing of the data to be displayed comprises:
acquiring one-bit data which needs to be stored and is subjected to binarization processing on data to be displayed currently, acquiring the horizontal resolution of a display module and the number of the display modules from the bit value of the data to be displayed;
dividing said horizontal resolution by said bit value to obtain a quotient;
and using the quotient value to complement the number of the display modules to obtain a split screen value, wherein the split screen value is the sequencing value of the display modules correspondingly displayed by the one-bit data subjected to the binarization processing of the data to be displayed.
6. A tiled data processing system according to claim 5,
the data acquisition module comprises:
the input enabling signal acquisition unit is used for acquiring an input enabling signal of the field programmable gate array;
and the bit-by-bit data acquisition unit is used for acquiring one bit of data to be displayed from a data source when the input enabling signal reaches a rising edge until the output enabling clock signal reaches a second preset number of times, and then obtaining the complete data to be displayed.
7. An electronic device comprising a memory and a processor, the memory storing a program which, when executed by the processor, causes the processor to perform the steps of the tiled data processing method of any of claims 1 to 4.
8. A computer-readable storage medium storing a program which, when executed by a processor, causes the processor to perform the steps of the screen-pieced data processing method according to any one of claims 1 to 4.
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