CN113810071A - Self-adaptive line sequence adjusting method, device, equipment, system and storage medium - Google Patents
Self-adaptive line sequence adjusting method, device, equipment, system and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of differential signal receiving and transmitting, and discloses a method, a device, equipment, a system and a storage medium for self-adaptive line sequence adjustment. The invention provides a scheme for realizing self-adaptive line sequence adjustment on a software level, namely, after serial signals which are transmitted in a differential signal form and come from a signal sending end are obtained, the purpose of judging whether differential line welding has errors or not from a software perspective can be realized, and the line sequence adjustment on the software level can be self-adaptively finished through the change of a signal reduction processing mode when the errors are judged, so that received data of a normal line sequence are obtained, further, reworking and re-welding are not needed, the production efficiency can be greatly improved, and the method is convenient for practical application and popularization.
Description
Technical Field
The invention belongs to the technical field of differential signal transceiving, and particularly relates to a method, a device, equipment, a system and a storage medium for self-adaptive line sequence adjustment.
Background
In the conventional communication technology, if differential signals are used between two components for data transmission (including wired transmission or wireless transmission), differential wires at the connecting ends of the two components are respectively soldered to corresponding circuits, then data to be transmitted are processed into differential signals by a signal transmitting end component, the differential signals are transmitted to a signal receiving end component through the differential wires, then the differential signals are restored and processed into received data by a signal receiving end component, whether a wire sequence is correct or not is judged by detecting the received data, if the wire sequence is correct, the subsequently received differential signals are normally restored and processed so as to obtain correct received data, and if the wire sequence is incorrect, the previous soldering needs to be removed, the wire sequence is adjusted, and then the soldering needs to be performed again. However, in actual conditions, the error probability of the differential line welding method is very high, which leads to frequent rework, and further causes extremely low production efficiency.
Disclosure of Invention
In order to solve the problems that frequent rework is needed and the production efficiency is extremely low due to high error probability of a differential wire welding mode in actual working conditions, the invention aims to provide a self-adaptive wire sequence adjusting method, a device, terminal equipment, a communication system and a computer readable storage medium.
In a first aspect, the present invention provides a method for adjusting a self-adaptive line sequence, which is applied to a controller at a signal receiving end, and includes:
acquiring a serial signal which is transmitted in a differential signal form from a signal transmitting end;
sequentially carrying out parallel conversion processing and decoding processing on the serial signals to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front synchronous information and the rear synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
extracting a line sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal sending end, wherein the line sequence judgment code to be checked is one multi-bit parallel data;
judging whether the line sequence judgment code to be checked is equal to a known line sequence judgment code of the signal sending end, wherein the running difference positive value RD + of the known line sequence judgment code is not equal to the running difference negative value RD-of the known line sequence judgment code after the bit is inverted;
and if not, performing the processing of firstly negating, then performing parallel conversion and decoding on the subsequently received serial signals so as to complete the line sequence adjustment and obtain the received data of the normal line sequence.
Based on the above invention, a scheme is provided for realizing adaptive line sequence adjustment on a software level, namely, after a serial signal which is transmitted in a differential signal form and is from a signal transmitting end is obtained, the serial signal is sequentially subjected to parallel conversion processing and decoding processing to obtain a plurality of multi-bit parallel data with continuous time sequence, then according to a synchronous information rule of the signal transmitting end, a line sequence judgment code to be checked which is positioned in synchronous information is extracted from the plurality of multi-bit parallel data, then the characteristic that the known line sequence judgment code has a positive running difference value RD + and is not equal to a negative running difference value RD-after the bit is inverted is utilized, the purpose of judging whether differential line welding is wrong from a software angle can be realized by comparing the line sequence judgment code to be checked with the known line sequence judgment code, and the change of a signal reduction processing mode can be realized when the error is judged, the method and the device can adaptively complete the line sequence adjustment on the software level to obtain the received data of the normal line sequence, and further do not need to rework and re-weld, thereby greatly improving the production efficiency and being convenient for practical application and popularization.
In one possible design, extracting a wire sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal sending end includes:
acquiring at least two multi-bit parallel data from the M multi-bit parallel data, wherein N + K-1 multi-bit parallel data are respectively arranged in the M multi-bit parallel data at intervals in the at least two multi-bit parallel data and all adjacent two multi-bit parallel data in time sequence, and the value of K is two;
judging whether each multi-bit parallel data in the at least two multi-bit parallel data is equal to a known synchronization judgment code of the signal sending end, wherein the running difference positive value RD + of the known synchronization judgment code is equal to the running difference negative value RD-of the known synchronization judgment code after the bit is inverted;
if yes, extracting one adjacent multi-bit parallel data behind any one multi-bit parallel data in the at least two multi-bit parallel data in time sequence from the M multi-bit parallel data so as to obtain a line sequence judgment code to be checked in the synchronous information.
Based on the possible design, the purposes of accurately identifying the first code of the synchronous information from a plurality of multi-bit parallel data and extracting the judgment code of the line sequence to be checked can be realized on the premise of having the least content of the synchronous information, so that the occupation ratio of the service information in the differential signal can be effectively improved, the transmission speed of the service data is improved, and the receiving synchronization effect is guaranteed.
In one possible design, when the multi-bit parallel data is eight-bit parallel data, the known line sequence judgment code is a D code in 8B/10B coding, and the known synchronization judgment code is a K code in 8B/10B coding.
In one possible design, the D code is a D16.2 code and the K code is a K28.7 code.
In a second aspect, the present invention provides a self-adaptive line sequence adjusting device, which is arranged in a controller of a signal receiving end, and comprises a serial signal obtaining unit, a conversion decoding processing unit, a line sequence judging code extracting unit, a judging unit and a line sequence adjusting executing unit;
the serial signal acquisition unit is used for acquiring a serial signal which is transmitted from a signal transmitting end in a differential signal form;
the conversion decoding processing unit is in communication connection with the serial signal acquisition unit and is used for sequentially performing parallel conversion processing and decoding processing on the serial signal to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front synchronous information and the rear synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
the line sequence judgment code extraction unit is in communication connection with the conversion decoding processing unit and is used for extracting a line sequence judgment code to be checked from the M multi-bit parallel data according to a synchronous information rule of the signal sending end, wherein the line sequence judgment code to be checked is one multi-bit parallel data;
the judging unit is communicatively connected to the line sequence judgment code extracting unit, and configured to judge whether the line sequence judgment code to be checked is equal to a known line sequence judgment code of the signal sending end, where a running difference positive value RD + of the known line sequence judgment code after bit inversion is not equal to a running difference negative value RD-;
the line sequence adjustment executing unit is respectively in communication connection with the conversion decoding processing unit and the judging unit, and is configured to instruct the conversion decoding processing unit to perform processing of inverting, then converting in parallel and decoding on the subsequently received serial signal when it is judged that the line sequence judgment code to be checked is not equal to the known line sequence judgment code of the signal sending end, so as to complete line sequence adjustment and obtain received data of a normal line sequence.
In one possible design, the line sequence judgment code extraction unit comprises a parallel data acquisition subunit, a judgment subunit and a parallel data extraction subunit which are sequentially in communication connection;
the parallel data acquiring subunit is configured to acquire at least two pieces of multi-bit parallel data from the M pieces of multi-bit parallel data, where N + K-1 pieces of multi-bit parallel data are respectively spaced in the M pieces of multi-bit parallel data by all adjacent two pieces of multi-bit parallel data in time sequence, and K takes a value of two;
the determining subunit is configured to determine whether each piece of multi-bit parallel data in the at least two pieces of multi-bit parallel data is equal to a known synchronization determination code of the signal transmitting end, where a running difference positive value RD + of the known synchronization determination code after bit inversion is equal to a running difference negative value RD —;
the parallel data extracting subunit is configured to, when it is determined that each multi-bit parallel data in the at least two multi-bit parallel data is equal to a known synchronization determination code of the signal sending end, extract, from the M multi-bit parallel data, an adjacent multi-bit parallel data that is chronologically behind any one multi-bit parallel data in the at least two multi-bit parallel data, so as to obtain a line-to-be-checked sequence determination code located in the synchronization information.
In a third aspect, the present invention provides a terminal device, including a memory and a controller, where the memory is used for storing a computer program, and the controller is used for reading the computer program and executing the adaptive line sequence adjusting method according to the first aspect or any possible design of the first aspect.
In a fourth aspect, the present invention provides a communication system, including a signal sending end component and a signal receiving end component, where the signal receiving end component includes a differential signal receiving circuit and a signal receiving controller that are communicatively connected, the differential signal receiving circuit is communicatively connected to the signal sending end component through a differential signal transmission link, and the signal receiving controller includes a conversion and decoding processing module and a data receiving module that are communicatively connected;
the signal transmitting end component is used for transmitting a differential signal to the differential signal receiving circuit through the differential signal transmission link;
the differential signal receiving circuit is used for carrying out circuit processing on the received differential signal to obtain a serial signal and inputting the serial signal into a conversion decoding processing module in the controller;
the conversion decoding processing module is used for sequentially carrying out parallel conversion processing and decoding processing on the serial signals to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front and back synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
the data receiving module is used for receiving all multi-bit parallel data from the conversion decoding processing module, and extracting a wire sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal sending end component, then when the judgment code of the wire sequence to be checked is judged not to be equal to the judgment code of the known wire sequence of the signal sending end component, instructing the conversion decoding processing module to perform the processes of first negation, then parallel conversion and decoding on the subsequently received serial signals so as to complete the line sequence adjustment and obtain the received data of the normal line sequence, the line sequence judgment code to be checked is the multi-bit parallel data, and the running difference positive value RD + of the known line sequence judgment code is not equal to the running difference negative value RD-of the known line sequence judgment code after the bit is inverted.
In one possible design, the signal sending end assembly comprises a signal sending controller and a differential signal sending circuit which are connected in communication, wherein the signal sending controller comprises a data sending module and a coding conversion processing module which are connected in communication, and the differential signal sending circuit is connected with the differential signal receiving circuit in communication through the differential signal transmission link;
the data sending module is configured to generate data to be sent that includes the synchronization information and the service information, and transmit the data to be sent to the code conversion processing module, where the synchronization information includes the known line sequence judgment code;
the coding conversion processing module is used for sequentially carrying out coding processing and serial conversion processing on the data to be transmitted to obtain serial signals to be transmitted and outputting the serial signals to be transmitted to the differential signal transmitting circuit;
the differential signal transmitting circuit is used for performing circuit processing on the serial signal to be transmitted to obtain a differential signal to be transmitted, and transmitting the differential signal to be transmitted to the differential signal receiving circuit through the differential signal transmission link.
In a fifth aspect, the present invention provides a computer-readable storage medium having stored thereon instructions which, when executed on a computer, perform the adaptive line sequence adjustment method according to the first aspect or any possible design of the first aspect.
In a sixth aspect, the present invention provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the adaptive line sequence adjustment method as described in the first aspect or any possible design of the first aspect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for adjusting a self-adaptive line sequence according to the present invention.
Fig. 2 is a diagram illustrating an exemplary timing sequence of multi-bit parallel data in the adaptive line sequence adjusting method according to the present invention.
Fig. 3 is a diagram illustrating an exemplary processing procedure of multi-bit parallel data before 10B/8B decoding, where fig. 3(a) shows the processing procedure when the previously encoded data exists more than the bit "0" than the bit "1", and fig. 3(B) shows the processing procedure when the previously encoded data exists more than the bit "1" than the bit "0".
Fig. 4 is a schematic structural diagram of an adaptive line sequence adjusting apparatus provided in the present invention.
Fig. 5 is a schematic structural diagram of a terminal device provided by the present invention.
Fig. 6 is a schematic structural diagram of a communication system provided in the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely representative of exemplary embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that, although the terms first, second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, a first object may be referred to as a second object, and similarly, a second object may be referred to as a first object, without departing from the scope of example embodiments of the present invention.
It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, B exists alone or A and B exist at the same time; for the term "/and" as may appear herein, which describes another associative object relationship, it means that two relationships may exist, e.g., a/and B, may mean: a exists singly or A and B exist simultaneously; in addition, for the character "/" that may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.
As shown in fig. 1, the adaptive line sequence adjusting method provided in the first aspect of this embodiment can be applied to a controller at a signal receiving end and executed by the controller with certain computing resources, for example, executed by a digital processing Unit such as a Micro Controller Unit (MCU), a microprocessor, a Field Programmable Gate Array (FPGA), and a Complex Programmable Logic Device (CPLD) in a terminal Device, so as to determine whether the differential line welding is faulty from a software perspective after acquiring serial signals transmitted in a differential signal form from a signal transmitting end, and adaptively complete line sequence adjustment at a software level through a change of a signal reduction processing manner when the fault is determined, obtain received data of a normal line sequence, and further, without rework and rewelding, greatly improve production efficiency, is convenient for practical application and popularization. As shown in fig. 1, the adaptive line sequence adjusting method may include, but is not limited to, the following steps S1 to S5.
S1, acquiring a serial signal which is transmitted from a signal transmitting end in a differential signal mode.
In step S1, the serial signal may be obtained by the differential signal receiving circuit of the signal receiving terminal after performing circuit processing on the differential signal from the signal transmitting terminal, and is input to the controller to achieve the purpose of obtaining the serial signal, where a specific circuit processing manner is an existing conventional differential signal receiving processing manner, such as performing comparison processing on two paths of differential signals based on a comparator and performing differential-to-single-ended processing, and the like. In addition, the transmission of the serial signal in the form of differential signals means that, in the signal transmission process, the serial signal circuit needs to be processed into two differential signals (specifically, the conventional differential signal transmission processing mode, for example, signal amplification processing and single-ended signal to differential processing are performed on the serial signal), then one differential signal is transmitted on two differential lines (which may be in a wired link mode or a wireless link mode), and finally, when the two differential signals are received, the serial signal is restored through circuit processing.
And S2, sequentially carrying out parallel conversion processing and decoding processing on the serial signals to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 × K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front synchronous information and the rear synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information.
In step S2, the parallel conversion processing is a restoration processing behavior corresponding to the serial conversion processing behavior at the time of the serial signal transmission, and is used to convert the 01 data represented by the level (for example, high level represents 1, low level represents 0) in the serial signal into the multiple parallel 01 data; the decoding processing is a restoration processing behavior corresponding to the encoding processing behavior at the time of the serial signal transmission, and is used for decoding and restoring the multi-path parallel 01 data into multi-bit parallel data (specifically, decoding and restoring multi-bit parallel data with a high bit number into multi-bit parallel data with a low bit number, for example, decoding and restoring ten-bit parallel data into eight-bit parallel data); the two restoration processing modes are both the existing conventional mapping relation processing mode. Taking the case that the multi-bit parallel data is eight-bit parallel data (i.e. one multi-bit parallel data represents data of one Byte), if an 8B/10B encoding method (an existing encoding method that encodes eight-bit data into ten-bit data) is used for data encoding and a 10B/8B decoding method (an existing decoding method that corresponds to the 8B/10B encoding method and decodes ten-bit data into eight-bit data) is used for data decoding, the M multi-bit parallel data with consecutive time sequences may be as shown in fig. 2, and the corresponding parallel conversion processing and decoding processing procedures may be as shown in fig. 3. In addition, the value of M is indefinite, and the subsequent step S3 is executed once each multi-bit parallel data is obtained after the minimum value condition (i.e. not less than N +2 × K) is satisfied until the line sequence determination code in the synchronization information is extracted; the synchronization information and the service information are conventional terms, the former includes data required for signal synchronization at a signal receiving end, and the latter includes service data actually required to be transmitted.
And S3, extracting a line sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to the synchronization information rule of the signal sending end, wherein the line sequence judgment code to be checked is one multi-bit parallel data.
In the step S3, the key for extracting the line-sequence-to-be-checked code is how to identify the synchronization information from the M multi-bit parallel data and the known position of the known line-sequence-to-be-checked code in the synchronization information (i.e. as one of the contents of the synchronization information rule), and the specific extraction process may be implemented by identifying the synchronization information from the M multi-bit parallel data based on an existing conventional identification manner, and then extracting the line-sequence-to-be-checked code according to the known position of the known line-sequence-to-be-checked code in the synchronization information.
S4, judging whether the line sequence judgment code to be checked is equal to a known line sequence judgment code of the signal sending end or not, wherein the running difference positive value RD + of the known line sequence judgment code is not equal to the running difference negative value RD-of the known line sequence judgment code after the bit is inverted.
In step S4, the known line sequence judgment code is added to a specified position in the synchronization information before the signal sending end encodes data to be sent, so as to extract the line sequence judgment code to be checked from the M multi-bit parallel data based on the synchronization information rule of the signal sending end. The running difference positive value RD + and the running difference negative value RD-are common terms of the existing encoding/decoding technology, wherein the running difference positive value RD + refers to an encoding result corresponding to a digital code when the accumulated state of the inconsistency (i.e. running inconsistency, abbreviated RD) of all the encoded data is more bits "1" than "0" when the digital code is encoded, and can also be represented by "+ 1" in a simplified manner; the running difference negative value RD-refers to the coding result corresponding to a digital code when the inconsistency accumulation states of all the coded data are more bits "0" than bits "1" when the digital code is coded, and can also be represented by "-1" in a simplified way. Taking the example that the multi-bit parallel data is eight-bit parallel data, if an 8B/10B coding mode is adopted for data coding and a 10B/8B decoding mode is adopted for data decoding, the known line sequence judgment code may adopt a D code which is in the 8B/10B coding and satisfies a running difference positive value RD + and is not equal to a running difference negative value RD-after bit inversion, such as a partial D code shown in table 1 below:
TABLE 1 run disparity positive RD + and run disparity negative RD + for partial D codes in 8B/10B coding
As shown in table 1 above, the D code may specifically but not limited to be a D16.2 code, that is, OX50 or "01010000" is used, and the running difference positive value RD + is "1001000101", and the running difference negative value RD-is "0110110101", which may satisfy the condition that the running difference positive value RD + is not equal to the running difference negative value RD "after bit inversion. Because the known line sequence judging code has the characteristic that the running difference positive value RD + is not equal to the running difference negative value RD-after the bit is inverted, if the line sequence error exists in the differential line, the line sequence judging code to be checked obtained after the circuit processing, the parallel conversion processing, the decoding processing and the data code extraction processing are sequentially carried out on the two paths of received differential signals is inevitably not equal to the known line sequence judging code, otherwise, the line sequence judging code to be checked is inevitably equal, and whether the line sequence judging code to be checked is equal to the known line sequence judging code or not can be used as a judging basis for judging whether the line sequence is normal or not so as to carry out line sequence adjustment when the line sequence is judged to be abnormal.
And S5, if not, performing the processing of firstly negating, then performing parallel conversion and decoding on the subsequently received serial signals so as to complete the line sequence adjustment and obtain the received data of the normal line sequence.
In the step S5, since the line sequence error/abnormality is determined, the serial signal received subsequently is inverted, so that the erroneous serial signal caused by the line sequence error/abnormality of the two differential lines can be corrected on the software level, and then the line sequence adjustment can be adaptively completed through the conversion and decoding processes, so as to obtain the received data of the normal line sequence. In addition, if the judgment code of the line sequence to be checked is equal to the judgment code of the known line sequence, the line sequence is determined to be normal, the currently received multi-bit parallel data is the received data of the normal line sequence, and the line sequence adjustment is not needed.
Thus, based on the adaptive line sequence adjusting method described in the foregoing steps S1-S5, a scheme is provided for implementing adaptive line sequence adjustment on a software level, that is, after a serial signal transmitted in a differential signal form from a signal transmitting end is obtained, the serial signal is sequentially subjected to parallel conversion processing and decoding processing to obtain a plurality of multi-bit parallel data with continuous time sequence, then according to a synchronization information rule of the signal transmitting end, a line sequence judgment code to be checked located in synchronization information is extracted from the plurality of multi-bit parallel data, then by utilizing a characteristic that a known line sequence judgment code has a running difference positive value RD + is not equal to a running difference negative value RD after a bit is inverted, the purpose of judging whether a line welding difference is wrong or not from a software perspective is achieved by comparing the line sequence judgment code to be checked with the known line sequence judgment code, when an error is determined, the line sequence adjustment on the software level can be completed in a self-adaptive manner through the change of the signal reduction processing mode, so that the received data of the normal line sequence can be obtained, and further, rework and re-welding are not needed, so that the production efficiency can be greatly improved, and the practical application and popularization are facilitated.
In this embodiment, on the basis of the technical solution of the first aspect, a first possible design for how to extract the wire-sequence-to-be-checked judgment code is further provided, that is, the wire-sequence-to-be-checked judgment code located in the synchronization information is extracted from the M multi-bit parallel data according to the synchronization information rule of the signal sending end, which includes, but is not limited to, the following steps S31 to S33.
S31, at least two multi-bit parallel data are obtained from the M multi-bit parallel data, wherein N + K-1 multi-bit parallel data are respectively arranged in the M multi-bit parallel data at intervals of all adjacent two multi-bit parallel data in the at least two multi-bit parallel data in a time sequence, and the value of K is two.
In step S31, for example, as shown in fig. 2, the right-most 1 st multi-bit parallel data, the N +3 th multi-bit parallel data, and the like may be used as the at least two multi-bit parallel data, the right-most 2 nd multi-bit parallel data, the N +4 th multi-bit parallel data, and the like may be used as the at least two multi-bit parallel data, the right-most 3 rd multi-bit parallel data, the N +5 th multi-bit parallel data, and the like may be used as the at least two multi-bit parallel data, and the like. In addition, the value K is two, which indicates that the synchronization information includes a multi-bit parallel data (i.e., a subsequent known synchronization decision code) for performing signal synchronization at the signal receiving end in addition to the known line sequence decision code.
And S32, judging whether each multi-bit parallel data in the at least two multi-bit parallel data is equal to a known synchronization judgment code of the signal sending end, wherein the running difference positive value RD + of the known synchronization judgment code is equal to the running difference negative value RD-of the known synchronization judgment code after the bit is inverted.
In step S32, since the known synchronization decision code has a positive operation difference value RD + equal to a negative operation difference value RD-after bit inversion, even if a line sequence error exists in a differential line, after the received two paths of differential signals are sequentially subjected to circuit processing, parallel conversion processing, decoding processing and data code extraction processing, the obtained corresponding multi-bit parallel data can still be equal to the known synchronization decision code, so that whether each multi-bit parallel data in the at least two multi-bit parallel data is equal to the known synchronization decision code can be used as a basis for determining whether each multi-bit parallel data is a first code in the synchronization information, so that when the known synchronization decision code is determined as the first code, based on a positional relationship between the known synchronization decision code and the known line sequence decision code in the synchronization information, and extracting the line sequence judgment code to be checked corresponding to the known line sequence judgment code from the M multi-bit parallel data. Similarly, taking the example that the multi-bit parallel data is eight-bit parallel data, if an 8B/10B coding method is adopted for data coding and a 10B/8B decoding method is adopted for data decoding, the known synchronization judgment code may adopt a K code which is in 8B/10B coding and satisfies a running difference positive value RD + and is equal to a running difference negative value RD-after bit inversion, as a partial K code shown in table 2 below:
TABLE 2 run disparity positive RD + and run disparity negative RD + for partial K codes in 8B/10B coding
As shown in the above table 2, the K code may specifically but not limited to be the K28.7 code, that is, the OXFC or "11111100" is used, and the running difference positive value RD + is "1100000111", and the running difference negative value RD-is "0011111000", which may satisfy the condition that the running difference positive value RD + is equal to the running difference negative value RD "after the bit is inverted. Furthermore, considering that there may be a discrete OXFC or "11111100" in the traffic information, the number of the at least two multi-bit parallel data should be as large as possible, so as to eliminate the situation that the synchronization information header is misjudged due to the presence of the discrete OXFC or "11111100".
And S33, if yes, extracting one adjacent multi-bit parallel data behind any one of the at least two multi-bit parallel data in time sequence from the M multi-bit parallel data so as to obtain a line-to-be-checked sequence judgment code in the synchronous information.
In the step S33, since the synchronization information includes two multi-bit parallel data and the first code is determined, the adjacent multi-bit parallel data after the first code in the M multi-bit parallel data is the line sequence determination code to be checked corresponding to the known line sequence determination code, as shown in fig. 2, the 2 nd and N +4 th multi-bit parallel data from the right can be independently used as the line sequence determination code to be checked, respectively. In addition, if it is determined that at least one of the at least two pieces of multi-bit parallel data is not equal to the known synchronization determination code of the signal sending end, any one piece of multi-bit parallel data in the at least two pieces of multi-bit parallel data cannot be used as the synchronization information head code, different pieces of multi-bit parallel data need to be obtained again, and then steps S32 to S33 are executed again until the to-be-checked line sequence determination code is extracted.
Therefore, based on the possible design one described in the foregoing steps S31 to S33, on the premise of having the least content of synchronization information, the purpose of accurately identifying the synchronization information first code from a plurality of multi-bit parallel data and extracting the line sequence judgment code to be checked can be achieved, so that the occupation ratio of the service information in the differential signal can be effectively improved, the service data transmission speed can be improved, and the receiving synchronization effect can be ensured.
As shown in fig. 4, a second aspect of this embodiment provides a virtual device for implementing the adaptive line sequence adjustment method according to any one of the first aspect or the first aspect, where the virtual device is disposed in a controller at a signal receiving end, and includes a serial signal obtaining unit, a conversion and decoding processing unit, a line sequence determination code extracting unit, a determining unit, and a line sequence adjustment executing unit;
the serial signal acquisition unit is used for acquiring a serial signal which is transmitted from a signal transmitting end in a differential signal form;
the conversion decoding processing unit is in communication connection with the serial signal acquisition unit and is used for sequentially performing parallel conversion processing and decoding processing on the serial signal to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front synchronous information and the rear synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
the line sequence judgment code extraction unit is in communication connection with the conversion decoding processing unit and is used for extracting a line sequence judgment code to be checked from the M multi-bit parallel data according to a synchronous information rule of the signal sending end, wherein the line sequence judgment code to be checked is one multi-bit parallel data;
the judging unit is communicatively connected to the line sequence judgment code extracting unit, and configured to judge whether the line sequence judgment code to be checked is equal to a known line sequence judgment code of the signal sending end, where a running difference positive value RD + of the known line sequence judgment code after bit inversion is not equal to a running difference negative value RD-;
the line sequence adjustment executing unit is respectively in communication connection with the conversion decoding processing unit and the judging unit, and is configured to instruct the conversion decoding processing unit to perform processing of inverting, then converting in parallel and decoding on the subsequently received serial signal when it is judged that the line sequence judgment code to be checked is not equal to the known line sequence judgment code of the signal sending end, so as to complete line sequence adjustment and obtain received data of a normal line sequence.
In one possible design, the line sequence judging code extracting unit comprises a parallel data acquiring subunit, a judging subunit and a parallel data extracting subunit which are sequentially in communication connection;
the parallel data acquiring subunit is configured to acquire at least two pieces of multi-bit parallel data from the M pieces of multi-bit parallel data, where N + K-1 pieces of multi-bit parallel data are respectively spaced in the M pieces of multi-bit parallel data by all adjacent two pieces of multi-bit parallel data in time sequence, and K takes a value of two;
the determining subunit is configured to determine whether each piece of multi-bit parallel data in the at least two pieces of multi-bit parallel data is equal to a known synchronization determination code of the signal transmitting end, where a running difference positive value RD + of the known synchronization determination code after bit inversion is equal to a running difference negative value RD —;
the parallel data extracting subunit is configured to, when it is determined that each multi-bit parallel data in the at least two multi-bit parallel data is equal to a known synchronization determination code of the signal sending end, extract, from the M multi-bit parallel data, an adjacent multi-bit parallel data that is chronologically behind any one multi-bit parallel data in the at least two multi-bit parallel data, so as to obtain a line-to-be-checked sequence determination code located in the synchronization information.
For the working process, working details, and technical effects of the foregoing apparatus provided in the second aspect of this embodiment, reference may be made to the adaptive line sequence adjustment method described in the first aspect or any one of the first aspects that may be designed, and details are not described herein.
As shown in fig. 5, a third aspect of this embodiment provides a terminal device for executing the adaptive line sequence adjusting method according to any one of the first aspect or the possible designs of the first aspect, where the terminal device includes a memory and a controller, the memory is used for storing a computer program, and the controller is used for reading the computer program and executing the adaptive line sequence adjusting method according to any one of the first aspect or the possible designs of the first aspect. For example, the Memory may include, but is not limited to, a Random-Access Memory (RAM), a Read-Only Memory (ROM), a Flash Memory (Flash Memory), a First-in First-out (FIFO), and/or a First-in Last-out (FILO), and the like; the controller may be, but is not limited to, a microcontroller of the model number STM32F105 family. In addition, the terminal equipment can also include, but is not limited to, a power supply module, a display screen and other necessary components.
For a working process, working details, and technical effects of the foregoing terminal device provided in the third aspect of this embodiment, reference may be made to the adaptive line sequence adjustment method described in the first aspect or any one of the first aspects that may be designed, which is not described herein again.
As shown in fig. 6, a fourth aspect of this embodiment provides a communication system that employs the adaptive line sequence adjustment method according to any one of the first aspect or the first aspect, including a signal sending end component and a signal receiving end component, where the signal receiving end component includes a differential signal receiving circuit and a signal receiving controller that are communicatively connected, the differential signal receiving circuit is communicatively connected to the signal sending end component through a differential signal transmission link, and the signal receiving controller includes a conversion and decoding processing module and a data receiving module that are communicatively connected;
the signal transmitting end component is used for transmitting a differential signal to the differential signal receiving circuit through the differential signal transmission link;
the differential signal receiving circuit is used for carrying out circuit processing on the received differential signal to obtain a serial signal and inputting the serial signal into a conversion decoding processing module in the controller;
the conversion decoding processing module is used for sequentially carrying out parallel conversion processing and decoding processing on the serial signals to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front and back synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
the data receiving module is used for receiving all multi-bit parallel data from the conversion decoding processing module, and extracting a wire sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal sending end component, then when the judgment code of the wire sequence to be checked is judged not to be equal to the judgment code of the known wire sequence of the signal sending end component, instructing the conversion decoding processing module to perform the processes of first negation, then parallel conversion and decoding on the subsequently received serial signals so as to complete the line sequence adjustment and obtain the received data of the normal line sequence, the line sequence judgment code to be checked is the multi-bit parallel data, and the running difference positive value RD + of the known line sequence judgment code is not equal to the running difference negative value RD-of the known line sequence judgment code after the bit is inverted.
In one possible design, the signal sending end component includes a signal sending controller and a differential signal sending circuit that are connected in communication, where the signal sending controller includes a data sending module and a coding conversion processing module that are connected in communication, and the differential signal sending circuit is connected in communication with the differential signal receiving circuit through the differential signal transmission link;
the data sending module is configured to generate data to be sent that includes the synchronization information and the service information, and transmit the data to be sent to the code conversion processing module, where the synchronization information includes the known line sequence judgment code;
the coding conversion processing module is used for sequentially carrying out coding processing and serial conversion processing on the data to be transmitted to obtain serial signals to be transmitted and outputting the serial signals to be transmitted to the differential signal transmitting circuit;
the differential signal transmitting circuit is used for performing circuit processing on the serial signal to be transmitted to obtain a differential signal to be transmitted, and transmitting the differential signal to be transmitted to the differential signal receiving circuit through the differential signal transmission link.
For a working process, working details, and technical effects of the foregoing communication system provided in the fourth aspect of this embodiment, reference may be made to the adaptive line sequence adjustment method described in the first aspect or any one of the first aspects that may be designed, and details are not described herein.
A fifth aspect of the present embodiment provides a computer-readable storage medium storing instructions including the instructions of any one of the first aspect or the first aspect in possible design, that is, the computer-readable storage medium stores instructions that, when executed on a computer, perform the adaptive line sequence adjustment method according to any one of the first aspect or the first aspect in possible design. The computer-readable storage medium refers to a carrier for storing data, and may include, but is not limited to, a computer-readable storage medium such as a floppy disk, an optical disk, a hard disk, a flash Memory, a flash disk and/or a Memory Stick (Memory Stick), and the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
For a working process, working details, and technical effects of the foregoing computer-readable storage medium provided in the fifth aspect of this embodiment, reference may be made to the adaptive line sequence adjustment method in any one of the first aspect or the first aspect, which is not described herein again.
A sixth aspect of the present embodiments provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the adaptive line sequence adjustment method according to the first aspect or any one of the possible designs of the first aspect. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable devices.
Finally, it should be noted that the present invention is not limited to the above alternative embodiments, and that various other forms of products can be obtained by anyone in light of the present invention. The above detailed description should not be taken as limiting the scope of the invention, which is defined in the claims, and which the description is intended to be interpreted accordingly.
Claims (10)
1. A method for adjusting an adaptive line sequence is applied to a controller of a signal receiving end, and comprises the following steps:
acquiring a serial signal which is transmitted in a differential signal form from a signal transmitting end;
sequentially carrying out parallel conversion processing and decoding processing on the serial signals to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front synchronous information and the rear synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
extracting a line sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal sending end, wherein the line sequence judgment code to be checked is one multi-bit parallel data;
judging whether the line sequence judgment code to be checked is equal to a known line sequence judgment code of the signal sending end, wherein the running difference positive value RD + of the known line sequence judgment code is not equal to the running difference negative value RD-of the known line sequence judgment code after the bit is inverted;
and if not, performing the processing of firstly negating, then performing parallel conversion and decoding on the subsequently received serial signals so as to complete the line sequence adjustment and obtain the received data of the normal line sequence.
2. The adaptive line sequence adjusting method according to claim 1, wherein extracting a line sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal transmitting end includes:
acquiring at least two multi-bit parallel data from the M multi-bit parallel data, wherein N + K-1 multi-bit parallel data are respectively arranged in the M multi-bit parallel data at intervals in the at least two multi-bit parallel data and all adjacent two multi-bit parallel data in time sequence, and the value of K is two;
judging whether each multi-bit parallel data in the at least two multi-bit parallel data is equal to a known synchronization judgment code of the signal sending end, wherein the running difference positive value RD + of the known synchronization judgment code is equal to the running difference negative value RD-of the known synchronization judgment code after the bit is inverted;
if yes, extracting one adjacent multi-bit parallel data behind any one multi-bit parallel data in the at least two multi-bit parallel data in time sequence from the M multi-bit parallel data so as to obtain a line sequence judgment code to be checked in the synchronous information.
3. The adaptive line sequence adjusting method of claim 2, wherein when the multi-bit parallel data is eight-bit parallel data, the known line sequence judgment code is a D code in an 8B/10B code, and the known synchronization judgment code is a K code in the 8B/10B code.
4. The adaptive line order adjusting method of claim 3, wherein the D code is a D16.2 code and the K code is a K28.7 code.
5. A self-adaptive line sequence adjusting device is characterized in that a controller arranged at a signal receiving end comprises a serial signal acquisition unit, a conversion decoding processing unit, a line sequence judgment code extraction unit, a judgment unit and a line sequence adjustment execution unit;
the serial signal acquisition unit is used for acquiring a serial signal which is transmitted from a signal transmitting end in a differential signal form;
the conversion decoding processing unit is in communication connection with the serial signal acquisition unit and is used for sequentially performing parallel conversion processing and decoding processing on the serial signal to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front synchronous information and the rear synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
the line sequence judgment code extraction unit is in communication connection with the conversion decoding processing unit and is used for extracting a line sequence judgment code to be checked from the M multi-bit parallel data according to a synchronous information rule of the signal sending end, wherein the line sequence judgment code to be checked is one multi-bit parallel data;
the judging unit is communicatively connected to the line sequence judgment code extracting unit, and configured to judge whether the line sequence judgment code to be checked is equal to a known line sequence judgment code of the signal sending end, where a running difference positive value RD + of the known line sequence judgment code after bit inversion is not equal to a running difference negative value RD-;
the line sequence adjustment executing unit is respectively in communication connection with the conversion decoding processing unit and the judging unit, and is configured to instruct the conversion decoding processing unit to perform processing of inverting, then converting in parallel and decoding on the subsequently received serial signal when it is judged that the line sequence judgment code to be checked is not equal to the known line sequence judgment code of the signal sending end, so as to complete line sequence adjustment and obtain received data of a normal line sequence.
6. The adaptive line sequence adjusting device of claim 5, wherein the line sequence judging code extracting unit comprises a parallel data acquiring subunit, a judging subunit and a parallel data extracting subunit which are sequentially connected in communication;
the parallel data acquiring subunit is configured to acquire at least two pieces of multi-bit parallel data from the M pieces of multi-bit parallel data, where N + K-1 pieces of multi-bit parallel data are respectively spaced in the M pieces of multi-bit parallel data by all adjacent two pieces of multi-bit parallel data in time sequence, and K takes a value of two;
the determining subunit is configured to determine whether each piece of multi-bit parallel data in the at least two pieces of multi-bit parallel data is equal to a known synchronization determination code of the signal transmitting end, where a running difference positive value RD + of the known synchronization determination code after bit inversion is equal to a running difference negative value RD —;
the parallel data extracting subunit is configured to, when it is determined that each multi-bit parallel data in the at least two multi-bit parallel data is equal to a known synchronization determination code of the signal sending end, extract, from the M multi-bit parallel data, an adjacent multi-bit parallel data that is chronologically behind any one multi-bit parallel data in the at least two multi-bit parallel data, so as to obtain a line-to-be-checked sequence determination code located in the synchronization information.
7. A terminal device, comprising a memory and a controller, wherein the memory is connected to the controller in a communication manner, the memory is used for storing a computer program, and the controller is used for reading the computer program and executing the adaptive line sequence adjusting method according to any one of claims 1 to 4.
8. A communication system is characterized by comprising a signal sending end component and a signal receiving end component, wherein the signal receiving end component comprises a differential signal receiving circuit and a signal receiving controller which are connected in a communication mode, the differential signal receiving circuit is connected with the signal sending end component in the communication mode through a differential signal transmission link, and the signal receiving controller comprises a conversion decoding processing module and a data receiving module which are connected in the communication mode;
the signal transmitting end component is used for transmitting a differential signal to the differential signal receiving circuit through the differential signal transmission link;
the differential signal receiving circuit is used for carrying out circuit processing on the received differential signal to obtain a serial signal and inputting the serial signal into a conversion decoding processing module in the controller;
the conversion decoding processing module is used for sequentially carrying out parallel conversion processing and decoding processing on the serial signals to obtain M multi-bit parallel data with continuous time sequence, wherein M is a positive integer not less than N +2 x K, N is a positive integer and represents the total number of the multi-bit parallel data of the service information between the front and back synchronous information in the time sequence, and K is a positive integer not less than two and represents the total number of the multi-bit parallel data of the synchronous information;
the data receiving module is used for receiving all multi-bit parallel data from the conversion decoding processing module, and extracting a wire sequence judgment code to be checked in the synchronization information from the M multi-bit parallel data according to a synchronization information rule of the signal sending end component, then when the judgment code of the wire sequence to be checked is judged not to be equal to the judgment code of the known wire sequence of the signal sending end component, instructing the conversion decoding processing module to perform the processes of first negation, then parallel conversion and decoding on the subsequently received serial signals so as to complete the line sequence adjustment and obtain the received data of the normal line sequence, the line sequence judgment code to be checked is the multi-bit parallel data, and the running difference positive value RD + of the known line sequence judgment code is not equal to the running difference negative value RD-of the known line sequence judgment code after the bit is inverted.
9. The communication system according to claim 8, wherein the signal transmitting end component comprises a signal transmitting controller and a differential signal transmitting circuit which are communicatively connected, wherein the signal transmitting controller comprises a data transmitting module and a coding conversion processing module which are communicatively connected, and the differential signal transmitting circuit is communicatively connected with the differential signal receiving circuit through the differential signal transmission link;
the data sending module is configured to generate data to be sent that includes the synchronization information and the service information, and transmit the data to be sent to the code conversion processing module, where the synchronization information includes the known line sequence judgment code;
the coding conversion processing module is used for sequentially carrying out coding processing and serial conversion processing on the data to be transmitted to obtain serial signals to be transmitted and outputting the serial signals to be transmitted to the differential signal transmitting circuit;
the differential signal transmitting circuit is used for performing circuit processing on the serial signal to be transmitted to obtain a differential signal to be transmitted, and transmitting the differential signal to be transmitted to the differential signal receiving circuit through the differential signal transmission link.
10. A computer-readable storage medium having stored thereon instructions for performing the adaptive line sequence adjustment method according to any one of claims 1 to 4 when the instructions are run on a computer.
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