CN113793570A

CN113793570A - Shift register, scanning drive circuit and display device

Info

Publication number: CN113793570A
Application number: CN202111134461.4A
Authority: CN
Inventors: 冯雪欢; 姚星; 许静波; 张大成
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Joint Technology Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-09-27
Filing date: 2021-09-27
Publication date: 2021-12-14

Abstract

The embodiment of the disclosure discloses a shift register, a scanning driving circuit and a display device, relates to the technical field of display, and is used for avoiding a flicker phenomenon of a display picture. The shift register includes: the circuit comprises a first input circuit, a second input circuit, a first control circuit, a first output circuit and a second output circuit. The first input circuit is electrically connected with the first signal end, the first clock signal end and the first node. The second input circuit is electrically connected with the second signal end, the third signal end, the second voltage signal end, the fourth signal end and the second node. The first output circuit is electrically connected with the first node, the first voltage signal end and the output signal end. The second output circuit is electrically connected with at least the second node, the second voltage signal end and the output signal end. The output signal terminal of the shift register is electrically connected to the gate of the control transistor of the pixel driving circuit to provide an enable signal. The shift register, the scanning driving circuit and the display device provided by the embodiment of the disclosure are used for image display.

Description

Shift register, scanning drive circuit and display device

Technical Field

The disclosure relates to the technical field of display, and in particular to a shift register, a scan driving circuit and a display device.

Background

Organic Light Emitting Diodes (OLEDs) have been widely used in the display field because of their advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, flexible display, etc.

Disclosure of Invention

An object of the present disclosure is to provide a shift register, a scan driving circuit and a display device, which are used to improve the response time of a dynamic image and reduce the smear of the dynamic image.

In order to achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

in one aspect, embodiments of the present disclosure provide a shift register. The shift register includes: the circuit comprises a first input circuit, a second input circuit, a first control circuit, a first output circuit and a second output circuit. The first input circuit is electrically connected with the first signal end, the first clock signal end and the first node. The first input circuit is configured to transmit a first signal received at the first signal terminal to the first node under control of a first clock signal transmitted by the first clock signal terminal. The second input circuit is electrically connected with the second signal end, the third signal end, the second voltage signal end, the fourth signal end and the second node. The second input circuit is configured to transmit a third signal received at the third signal terminal to the second node under control of a second signal transmitted by the second signal terminal, and to transmit a second voltage signal received at the second voltage signal terminal to the second node under control of the fourth signal terminal; the second signal terminal and the third signal terminal each include one of a first voltage signal terminal and the first clock signal terminal. The first control circuit is electrically connected to the first node, the second node, and the second voltage signal terminal. The first control circuit is configured to transmit the second voltage signal to the first node under control of a voltage of the second node. The first output circuit is electrically connected to the first node, the first voltage signal terminal, and the output signal terminal. The first output circuit is configured to transmit the first voltage signal to the output signal terminal under control of the voltage of the first node. The second output circuit is electrically connected to at least the second node, the second voltage signal terminal, and the output signal terminal. The second output circuit is configured to transmit the second voltage signal to the output signal terminal under control of the voltage of the second node.

Therefore, some embodiments of the present disclosure provide a shift register, by providing a first input circuit, a second input circuit, a first control circuit, a first output circuit, and a second output circuit, and electrically connecting each circuit with a corresponding signal terminal, the mutual cooperation between each circuit and each signal terminal can be utilized to lead the first output circuit and the second output circuit to be conducted in different time periods, so that the first voltage signal output by the first output circuit and the second voltage signal output by the second output circuit cooperate to form an output signal with alternating high and low levels, the waveform of the output signal is the same as the waveform of the enable signal required by the pixel driving circuit in the display device, thus, the plurality of shift registers can be used for providing the enabling signals for different pixel driving circuits in the display device, and the display driving corresponding to different sub-pixels is realized. The shift register is adopted to carry out display driving on the sub-pixels, the light-emitting stage and the black insertion stage can be alternately carried out in one frame display stage, and the light-emitting device can alternately emit light and stop emitting light in one frame display process, so that the light-emitting duration of the light-emitting device in the one frame display stage can be reduced, the response time of a dynamic picture is enhanced, the black insertion with short time interval and high frequency is realized, the black picture can be prevented from being captured by human eyes, and the flicker phenomenon of the display picture is avoided.

In some examples, the first input circuit includes: a first transistor; the gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

In some examples, the second input circuit includes: a second transistor and a third transistor; a gate of the second transistor is electrically connected to the second signal terminal, a first electrode of the second transistor is electrically connected to the third signal terminal, and a second electrode of the second transistor is electrically connected to the second node; a gate of the third transistor is electrically connected to the fourth signal terminal, a first electrode of the third transistor is electrically connected to the second voltage signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

In some examples, the second input circuit further comprises: a fourth transistor and a fifth transistor; a gate of the fourth transistor is electrically connected to the third node, a first electrode of the fourth transistor is electrically connected to the third signal terminal, and a second electrode of the fourth transistor is electrically connected to the second node; the second pole of the second transistor is also electrically connected with the third node and is electrically connected with the second node through the fourth transistor; the grid electrode of the fifth transistor is electrically connected with the fourth signal end, the first electrode of the fifth transistor is electrically connected with the second voltage signal end, and the second electrode of the fifth transistor is electrically connected with the third node.

In some examples, the first signal terminal is a first voltage signal terminal, and the fourth signal terminal is a first cascade signal terminal. Or, the first signal terminal is the first cascade signal terminal, and the fourth signal terminal is the first node.

In some examples, the shift register further comprises a second control circuit; the second control circuit is electrically connected with the first cascade signal end, the third voltage signal end, the fourth voltage signal end, the second cascade signal end and the fourth node. The second control circuit is configured to transmit a first cascade signal transmitted by the first cascade signal terminal to the fourth node under control of a third voltage signal transmitted by the third voltage signal terminal, or transmit a second cascade signal transmitted by the second cascade signal terminal to the fourth node under control of a fourth voltage signal transmitted by the fourth voltage signal terminal. Wherein the third voltage signal and the fourth voltage signal are inverse signals. Under the condition that the first signal end is a first cascade signal end and the fourth signal end is the first node, the first input circuit is also electrically connected with the fourth node and is electrically connected with the first cascade signal end through the second control circuit. And under the condition that the first signal end is the first voltage signal end and the fourth signal end is the first cascade signal end, the second input circuit is also electrically connected with the fourth node and is electrically connected with the first cascade signal end through the second control circuit.

In some examples, the second control circuit includes: a sixth transistor and a seventh transistor. The grid electrode of the sixth transistor is electrically connected with a third voltage signal end, the first electrode of the sixth transistor is electrically connected with the first cascade signal end, and the second electrode of the sixth transistor is electrically connected with the fourth node. A gate of the seventh transistor is electrically connected to a fourth voltage signal terminal, a first electrode of the seventh transistor is electrically connected to the second cascade signal terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node. Under the condition that the first signal end is a first cascade signal end, the fourth signal end is the first node, and the first input circuit comprises a first transistor, the first electrode of the first transistor is electrically connected with the fourth node and electrically connected with the first cascade signal end through the sixth transistor. When the first signal terminal is a first voltage signal terminal, the fourth signal terminal is the first cascade signal terminal, and the second input circuit includes a third transistor, a gate of the third transistor is further electrically connected to the fourth node and electrically connected to the first cascade signal terminal through the sixth transistor.

In some examples, the first control circuit includes: and an eighth transistor. A gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node. The first output circuit includes: a ninth transistor and a first capacitor; a gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the ninth transistor is electrically connected to the output signal terminal. A first pole of the first capacitor is electrically connected to the first node, and a second pole of the first capacitor is electrically connected to the output signal terminal. The second output circuit includes: a tenth transistor and a second capacitor. A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the tenth transistor is electrically connected to the first output signal terminal. A first pole of the second capacitor is electrically connected to the second node, and a second pole of the second capacitor is electrically connected to the second voltage signal terminal. In a case where the second output circuit is further electrically connected to a second clock signal terminal, the second pole of the second capacitor is electrically connected to the second voltage signal terminal or the second clock signal terminal.

In some examples, in a case where the first signal terminal is a first voltage signal terminal and the fourth signal terminal is a first cascade signal terminal, the shift register further includes: and a third control circuit. The third control circuit is electrically connected with a fifth node, a second clock signal end and the first node; the second control circuit is configured to transmit the second clock signal to the first node under control of the voltage of the fifth node and the second clock signal transmitted by the second clock signal terminal. Wherein the first input circuit is further electrically connected to the fifth node and to the first node through the third control circuit; the first input circuit is configured to transmit the first signal to the fifth node under control of the first clock signal.

In some examples, the second control circuit includes: an eleventh transistor, a twelfth transistor, and a third capacitor. A gate of the eleventh transistor is electrically connected to the fifth node, a first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the sixth node. A gate of the twelfth transistor is electrically connected to the second clock signal terminal, a first electrode of the twelfth transistor is electrically connected to the sixth node, and a second electrode of the twelfth transistor is electrically connected to the first node. A first pole of the third capacitor is electrically connected to the fifth node and a second pole of the third capacitor is electrically connected to the sixth node. In the case where the first input circuit includes a first transistor, a second pole of the first transistor is electrically connected to the fifth node, and is electrically connected to the first node through the eleventh transistor and the twelfth transistor in this order.

In some examples, the shift register further comprises: and a fourth control circuit. The fourth control circuit is electrically connected to the fifth node, the second voltage signal terminal, the second clock signal terminal, and the second node. The fourth control circuit is configured to transmit the second voltage signal to the second node under control of the voltage of the fifth node and the second clock signal.

In some examples, the fourth control circuit includes: a thirteenth transistor and a fourteenth transistor. A gate of the thirteenth transistor is electrically connected to the fifth node, a first electrode of the thirteenth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor. A gate of the fourteenth transistor is electrically connected to the second clock signal terminal, and a second pole of the fourteenth transistor is electrically connected to the second node.

In some examples, the shift register further comprises: and a fifth control circuit. The fifth control circuit is electrically connected to the second node, the fifth node, and one of the second voltage signal terminal and the first clock signal terminal. The fifth control circuit is configured to transmit the second voltage signal or the first clock signal to the fifth node under control of the voltage of the second node.

In some examples, the fifth control circuit includes: a fifteenth transistor. A gate of the fifteenth transistor is electrically connected to the second node, a first pole of the fifteenth transistor is electrically connected to one of the second voltage signal terminal and the first clock signal terminal, and a second pole of the fifteenth transistor is electrically connected to the fifth node.

In some examples, the shift register further comprises: a first switching circuit. The first switch circuit is electrically connected to the second node, the seventh node, and the first clock signal terminal. The first switching circuit is configured to transmit a signal from the seventh node to the second node under control of the first clock signal. The second input circuit is also electrically connected to the seventh node and to the second node through the first switch circuit.

In some examples, the first switching circuit includes: and a sixteenth transistor. A gate of the sixteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the sixteenth transistor is electrically connected to the seventh node, and a second electrode of the sixteenth transistor is electrically connected to the second node. In a case where the second input circuit includes the second transistor and the third transistor, a second pole of the second transistor is electrically connected to the seventh node and to the second node through the sixteenth transistor, and a second pole of the third transistor is electrically connected to the seventh node and to the second node through the sixteenth transistor.

In some examples, the shift register further comprises: a third input circuit and a sixth control circuit. The third input circuit is electrically connected to the third signal terminal, the second voltage signal terminal, the fifth voltage signal terminal, the fourth signal terminal, and the eighth node. The third input circuit is configured to transmit the third signal to the eighth node under control of a fifth voltage signal transmitted by the fifth voltage signal terminal or transmit the second voltage signal to the eighth node under control of the second signal. The third signal terminal includes one of the first voltage signal terminal, the first clock signal terminal, and the fifth voltage signal terminal. The sixth control circuit is electrically connected to the eighth node, the first node, and the second voltage signal terminal. The sixth control circuit is configured to transmit the second voltage signal to the first node under control of the voltage of the eighth node. The second output circuit is also electrically connected to the eighth node. The second output circuit is further configured to transmit the second voltage signal to the output signal terminal under control of the voltage of the eighth node. Wherein the second signal terminal further comprises a sixth voltage signal terminal. In a case where the second signal terminal is the sixth voltage signal terminal, the second input circuit is further configured to transmit the third signal to the eighth node under control of a sixth voltage signal transmitted by the sixth voltage signal terminal. The fifth voltage signal and the sixth voltage signal are inverse signals.

In some examples, the third input circuit includes: a seventeenth transistor and an eighteenth transistor. A gate of the seventeenth transistor is electrically connected to the fifth voltage signal terminal, a first electrode of the seventeenth transistor is electrically connected to the third signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the eighth node. The grid electrode of the eighteenth transistor is electrically connected with the fourth signal end, the first electrode of the eighteenth transistor is electrically connected with the second voltage signal end, and the second electrode of the eighteenth transistor is electrically connected with the eighth node. The sixth control circuit includes: a nineteenth transistor. A gate of the nineteenth transistor is electrically connected to the eighth node, a first electrode of the nineteenth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the nineteenth transistor is electrically connected to the first node. The second output circuit further includes: a twentieth transistor. The gate of the twentieth transistor is electrically connected to the eighth node, the first electrode of the twentieth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the twentieth transistor is electrically connected to the output signal terminal.

In some examples, the third input circuit further comprises: a twenty-first transistor and a twenty-second transistor. The grid electrode of the twenty-first transistor is electrically connected with a ninth node, the first electrode of the twenty-first transistor is electrically connected with the third signal end, and the second electrode of the twenty-first transistor is electrically connected with the eighth node. The grid electrode of the twenty-second transistor is electrically connected with a fourth signal end, the first electrode of the twenty-second transistor is electrically connected with the second voltage signal end, and the second electrode of the twenty-second transistor is electrically connected with the ninth node. Wherein a second pole of the seventeenth transistor is further electrically connected to the ninth node and to the eighth node through the twenty-first transistor.

In some examples, the shift register further includes at least one of a seventh control circuit, an eighth control circuit, and a second switch circuit. The seventh control circuit is electrically connected to the fifth node, the second voltage signal terminal, the second clock signal terminal, and the eighth node. The seventh control circuit is configured to transmit the second voltage signal to the eighth node under control of the voltage of the fifth node and a second clock signal transmitted by the second clock signal terminal. The eighth control circuit is electrically connected to the eighth node, the fourth node, and the second voltage signal terminal. The eighth control circuit is configured to transmit the second voltage signal to the fifth node under control of the voltage of the eighth node. The second switch circuit is electrically connected with the first clock signal end, the tenth node and the eighth node; the second switching circuit is configured to transmit a signal of the tenth node to the eighth node under the control of the first clock signal. The third input circuit is also electrically connected to the tenth node and to the eighth node through the second switch circuit.

In some examples, the seventh control circuit includes: a twenty-third transistor and a twenty-fourth transistor. A gate of the twenty-third transistor is electrically connected to the fifth node, a first electrode of the twenty-third transistor is electrically connected to the second voltage signal terminal, and a second electrode of the twenty-third transistor is electrically connected to the first electrode of the twenty-fourth transistor. A gate of the twenty-fourth transistor is electrically connected to the second clock signal terminal, and a second pole of the twenty-fourth transistor is electrically connected to the eighth node. The eighth control circuit includes: a twenty-fifth transistor. The gate of the twenty-fifth transistor is electrically connected to the eighth node, the first electrode of the twenty-fifth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the twenty-fifth transistor is electrically connected to the fifth node. The second switching circuit includes: a twenty-seventh transistor. A gate of the twenty-seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the twenty-seventh transistor is electrically connected to the tenth node, and a second electrode of the twenty-seventh transistor is electrically connected to the eighth node. In a case where the third input circuit includes the seventeenth transistor and the eighteenth transistor, a second pole of the seventeenth transistor is electrically connected to the tenth node and is electrically connected to the eighth node through the twenty seventh transistor, and a second pole of the eighteenth transistor is electrically connected to the tenth node and is electrically connected to the eighth node through the twenty seventh transistor.

In some examples, the shift register further comprises: a first anti-creeping circuit. The first leakage prevention circuit is electrically connected to one of the first node and the output signal terminal, the first voltage signal terminal, and a first leakage prevention node. The first leakage prevention circuit is configured to transmit the first voltage signal to the first leakage prevention node under control of a voltage of the first node or an output signal transmitted by the output signal terminal. Wherein the first control circuit is further electrically connected to the first anti-leakage node. The second output circuit is also electrically connected with the first anti-leakage node. In a case where the shift register further includes the sixth control circuit, the sixth control circuit is further electrically connected to the first leakage-preventing node.

In some examples, the first leakage prevention circuit includes: a twenty-sixth transistor. A gate of the twenty-sixth transistor is electrically connected to one of the first node and the output signal terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the first anti-leakage node. The eighth transistor includes: a first sub-transistor and a second sub-transistor. The grid electrode of the first sub transistor is electrically connected with the second node, the first electrode of the first sub transistor is electrically connected with the second voltage signal end, and the second electrode of the first sub transistor is electrically connected with the first anti-leakage node. The grid electrode of the second sub transistor is electrically connected with the second node, the first pole of the second sub transistor is electrically connected with the first anti-leakage node, and the second pole of the second sub transistor is electrically connected with the first node. The tenth transistor includes: a third sub-transistor and a fourth sub-transistor. The grid electrode of the third sub-transistor is electrically connected with the second node, the first electrode of the third sub-transistor is electrically connected with the second voltage signal end, and the second electrode of the third sub-transistor is electrically connected with the first anti-leakage node. The grid electrode of the fourth sub-transistor is electrically connected with the second node, the first electrode of the fourth sub-transistor is electrically connected with the first anti-leakage node, and the second electrode of the fourth sub-transistor is electrically connected with the output signal end. In a case where the sixth control circuit includes the nineteenth transistor, the nineteenth transistor includes: a fifth sub-transistor and a sixth sub-transistor. The gate of the fifth sub-transistor is electrically connected to the eighth node, the first electrode of the fifth sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the fifth sub-transistor is electrically connected to the first anti-leakage node. The gate of the sixth sub-transistor is electrically connected to the eighth node, the first pole of the sixth sub-transistor is electrically connected to the first anti-leakage node, and the second pole of the sixth sub-transistor is electrically connected to the first node. In a case where the second output circuit further includes a twentieth transistor, the twentieth transistor includes: a seventh sub-transistor and an eighth sub-transistor. A gate of the seventh sub-transistor is electrically connected to the eighth node, a first electrode of the seventh sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the seventh sub-transistor is electrically connected to the first anti-leakage node. The gate of the eighth sub-transistor is electrically connected to the eighth node, the first electrode of the eighth sub-transistor is electrically connected to the first anti-leakage node, and the second electrode of the eighth sub-transistor is electrically connected to the output signal terminal.

In some examples, in a case where the shift register further includes the third control circuit, the third control circuit is further electrically connected to the first leakage prevention node.

In some examples, in a case where the third control circuit includes an eleventh transistor and a twelfth transistor, the eleventh transistor includes: a ninth sub-transistor and a tenth sub-transistor. And/or, the twelfth transistor includes: an eleventh sub-transistor and a twelfth sub-transistor. The gate of the ninth sub-transistor is electrically connected to the fourth node, the first pole of the ninth sub-transistor is electrically connected to the fifth node, and the second pole of the ninth sub-transistor is electrically connected to the first anti-leakage node. A gate of the tenth sub-transistor is electrically connected to the fourth node, a first electrode of the tenth sub-transistor is electrically connected to the first anti-leakage node, and a second electrode of the tenth sub-transistor is electrically connected to the second clock signal terminal. A gate of the eleventh sub-transistor is electrically connected to the second clock signal terminal, a first electrode of the eleventh sub-transistor is electrically connected to the fifth node, and a second electrode of the eleventh sub-transistor is electrically connected to the first anti-leakage node. The grid electrode of the twelfth sub-transistor is electrically connected with the second clock signal end, the first electrode of the twelfth sub-transistor is electrically connected with the first anti-leakage node, and the second electrode of the twelfth sub-transistor is electrically connected with the first node.

In some examples, in a case where the shift register further includes the fifth control circuit, the fifth control circuit is further electrically connected to the first leakage prevention node. In a case where the shift register further includes the eighth control circuit, the eighth control circuit is further electrically connected to the first leakage-preventing node. Or, the shift register further includes: and a second anticreeping circuit. The second anti-leakage circuit is electrically connected with the fifth node, the first voltage signal end and the second anti-leakage node. The second leakage prevention circuit is configured to transmit the first voltage signal to the second leakage prevention node under control of the voltage of the fifth node. The fifth control circuit is also electrically connected with the second anti-creeping node. The eighth control circuit is further electrically connected to the second anti-leakage node.

In some examples, in a case where the fifth control circuit is further electrically connected to the first leakage prevention node, the fifteenth transistor includes: a thirteenth sub-transistor and a fourteenth sub-transistor. In a case where the eighth control circuit is further electrically connected to the first leakage-preventing node, the twenty-fifth transistor includes: a fifteenth sub-transistor and a sixteenth sub-transistor. The gate of the thirteenth sub-transistor is electrically connected to the second node, the first electrode of the thirteenth sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the thirteenth sub-transistor is electrically connected to the first anti-leakage node. A gate of the fourteenth sub-transistor is electrically connected to the second node, a first pole of the fourteenth sub-transistor is electrically connected to the first anti-leakage node, and a second pole of the fourteenth sub-transistor is electrically connected to the fifth node. A gate of the fifteenth sub-transistor is electrically connected to the eighth node, a first electrode of the fifteenth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the fifteenth sub-transistor is electrically connected to the first anti-leakage node. A gate of the sixteenth sub-transistor is electrically connected to the eighth node, a first pole of the sixteenth sub-transistor is electrically connected to the first anti-leakage node, and a second pole of the sixteenth sub-transistor is electrically connected to the fifth node. In a case where the fifth control circuit is further electrically connected to the second leakage-preventing node, the fifteenth transistor includes: a seventeenth sub-transistor and an eighteenth sub-transistor. In a case where the eighth control circuit is further electrically connected to the second leakage-preventing node, the twenty-fifth transistor includes: a nineteenth sub-transistor and a twentieth sub-transistor. The gate of the seventeenth sub-transistor is electrically connected to the second node, the first electrode of the seventeenth sub-transistor is electrically connected to the second voltage signal terminal, and the second electrode of the seventeenth sub-transistor is electrically connected to the second anti-leakage node. The grid electrode of the eighteenth sub-transistor is electrically connected with the second node, the first pole of the eighteenth sub-transistor is electrically connected with the second anti-leakage node, and the second pole of the eighteenth sub-transistor is electrically connected with the fifth node. A gate of the nineteenth sub-transistor is electrically connected to the eighth node, a first electrode of the nineteenth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the nineteenth sub-transistor is electrically connected to the second anti-leakage node. The gate of the twentieth sub-transistor is electrically connected to the eighth node, the first pole of the twentieth sub-transistor is electrically connected to the second anti-leakage node, and the second pole of the twentieth sub-transistor is electrically connected to the fifth node.

In another aspect, a scan driving circuit is provided, which includes a plurality of shift registers as described in some embodiments above.

The shift register included in the scan driving circuit has the same structure and beneficial technical effects as those of the shift register provided in some embodiments, and is not described herein again.

In yet another aspect, a display device is provided, which comprises the scan driving circuit and the pixel driving circuits described in some embodiments above. Wherein the pixel driving circuit includes: a switching transistor, a sensing transistor, a driving transistor, a control transistor, and a storage capacitor. And the shift register in the scanning driving circuit is electrically connected with the grid electrode of the control transistor so as to provide an enabling signal.

The scan driving circuit included in the display device has the same structure and beneficial technical effects as the scan driving circuit provided in some embodiments, and is not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic and are not intended to limit the actual size of products to which embodiments of the disclosure relate.

FIG. 1 is a block diagram of a display device according to some embodiments of the present disclosure;

FIG. 2 is a block diagram of another display device in accordance with some embodiments of the present disclosure;

FIG. 3 is a block diagram of a subpixel in some embodiments according to the present disclosure;

FIG. 4 is a timing diagram illustrating operation of a sub-pixel corresponding to the sub-pixel shown in FIG. 3 according to some embodiments of the present disclosure;

FIG. 5 is a block diagram of a shift register in accordance with some embodiments of the present disclosure;

FIG. 6 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

FIG. 7 is a circuit diagram of another shift register in some embodiments according to the present disclosure;

FIG. 8 is a block diagram of another shift register in some embodiments according to the present disclosure;

FIG. 9 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 10 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 11 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 12 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 13 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 14 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 15 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 16 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 17 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 18 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 19 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 20 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 21 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 22 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 23 is a block diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 24 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 25 is a circuit diagram of yet another shift register in some embodiments according to the present disclosure;

FIG. 26 is a block diagram of a scan driver circuit in accordance with some embodiments of the present disclosure;

FIG. 27 is a timing diagram illustrating operation of a scan driver circuit corresponding to the circuit shown in FIG. 26 according to some embodiments of the present disclosure;

FIG. 28 is a block diagram of another scan driver circuit in accordance with some embodiments of the present disclosure;

fig. 29 is a timing diagram illustrating an operation of a scan driving circuit corresponding to the scan driving circuit shown in fig. 28 according to some embodiments of the present disclosure.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "an example" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

The transistors used in the circuit provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the thin film transistors are all taken as examples in the embodiments of the present disclosure for description.

In some embodiments, the first pole of each transistor employed by the shift register is one of a source and a drain of the transistor, and the second pole is the other of the source and the drain of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain thereof may not be different in structure, that is, the first and the second poles of the transistor in the embodiment of the present disclosure may not be different in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit provided by the embodiment of the present disclosure, "nodes" do not represent actually existing components, but represent junctions of relevant electrical connections in the circuit diagram, that is, the nodes are nodes equivalent to the junctions of relevant electrical connections in the circuit diagram.

In the circuit provided in the embodiment of the present disclosure, the transistors are all N-type transistors as an example.

At present, in the display field, for example, in OLED display, an image smear phenomenon may occur during a dynamic picture switching process, and although some pixel driving circuits in the related art may improve the phenomenon by black insertion, because black insertion with a short time interval and a high frequency is difficult to be implemented in the pixel driving circuits in the related art, an improvement effect on the image smear phenomenon is limited, and a human eye may catch a black inserted picture easily, thereby causing a flicker of a display picture.

Based on this, some embodiments of the present disclosure provide a display device 1000, as shown in fig. 1, the display device 1000 may be any device that displays whether in motion (e.g., video) or stationary (e.g., still image) and whether text or images. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Digital Assistants (PDAs), hand-held or portable computers, Global Positioning System (GPS) receivers/navigators, cameras, motion Picture Experts Group (MP 4) video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, computer monitors, automobile displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear view cameras in vehicles), electronic photographs, electronic billboards or signs, video game consoles, and the like, Projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images for a piece of jewelry), and the like.

In some examples, as shown in fig. 2, the display apparatus 1000 may include: a substrate 200, and a plurality of sub-pixels P, a plurality of gate lines GL and a plurality of data lines DL disposed at one side of the substrate 200.

The types of the substrate 200 include various types, and the arrangement can be selected according to actual needs.

Illustratively, the substrate 200 may be a rigid substrate. The rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

Illustratively, the substrate 200 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like.

In some examples, as shown in fig. 2, the display apparatus 1000 has a display area a, and a bezel area B disposed beside the display area a. Here, the "side" refers to one side, two sides, three sides, or a peripheral side of the display area a, that is, the frame area B may be located on one side, two sides, or three sides of the display area a, or the frame area B may be disposed around the display area a.

In some examples, as shown in fig. 2, the plurality of sub-pixels P, the plurality of gate lines GL and the plurality of data lines DL may be located in the display area a, and the plurality of gate lines GL may extend along the first direction X and the plurality of data lines DL may extend along the second direction Y.

Here, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be set according to actual needs. Illustratively, the included angle between the first direction X and the second direction Y may be 85 °, 88 °, 90 °, 92 °, 95 °, or the like.

In some examples, as shown in fig. 3, each of the plurality of sub-pixels P may include a pixel driving circuit 300 and a light emitting device L electrically connected to the pixel driving circuit 300.

For example, the plurality of sub-pixels P may be arranged in an array, that is, the plurality of sub-pixels P may be arranged in a plurality of rows along the first direction X and arranged in a plurality of rows along the second direction Y. Here, the sub-pixels P arranged in a row along the first direction X may be referred to as the same row of sub-pixels P, and the sub-pixels P arranged in a row along the second direction Y may be referred to as the same column of sub-pixels P. The plurality of pixel driving circuits 300 in the same row of the subpixels P may be electrically connected to at least one gate line GL, and the plurality of pixel driving circuits 300 in the same column of the subpixels P may be electrically connected to one data line DL. The number of the gate lines GL electrically connected to the plurality of pixel driving circuits 300 in the same row of the sub-pixels P may be set according to the structure of the pixel driving circuits 300. The present disclosure will be described by taking an example in which a plurality of pixel driving circuits 300 in the same row of sub-pixels P are electrically connected to one gate line GL.

Of course, as shown in fig. 2, the display device 1000 may further include: a plurality of enable signal lines EL disposed at one side of the substrate 200 and extending in the first direction X.

Illustratively, one enable signal line EL may be electrically connected to a plurality of pixel driving circuits 300 in the same row of subpixels P.

During the display process of the display apparatus 1000, the sub-pixels P can receive the scan signal from the corresponding gate lines GL, the data signal from the corresponding data lines DL and the enable signal from the corresponding enable signal lines EL to form a driving voltage to drive the light emitting devices L in the sub-pixels P to emit light. The sub-pixels P cooperate with each other to enable the display device 1000 to display an image.

In some examples, as shown in fig. 3, the pixel driving circuit 300 includes: a switching transistor M1, a driving transistor M2, a sensing transistor M3, a control transistor M4, and a storage capacitor C.

For example, as shown in fig. 3, the gate of the switching transistor M1 is electrically connected to the first scan signal terminal G1, the first pole of the switching transistor M1 is electrically connected to the DATA signal terminal DATA, and the second pole of the switching transistor M1 is electrically connected to the DATA node G. Wherein the switching transistor M1 is configured to transmit the DATA signal received at the DATA signal terminal DATA to the DATA node G under the control of the first scan signal transmitted by the first scan signal terminal G1.

For example, as shown in fig. 3, the gate of the control transistor M4 is electrically connected to the enable signal terminal EM, the first pole of the control transistor M4 is electrically connected to the seventh voltage signal terminal ELVDD, and the second pole of the control transistor M4 is electrically connected to the first pole of the driving transistor M2. Wherein the control transistor M4 is configured to transmit the seventh voltage signal received at the seventh voltage signal terminal ELVDD to the first pole of the driving transistor M2 under the control of the enable signal transmitted by the enable signal terminal EM.

For example, as shown in fig. 3, the gate of the driving transistor M2 is electrically connected to the data node G, the first pole of the driving transistor M2 is electrically connected to the second pole of the control transistor M4, and the second pole of the driving transistor M2 is electrically connected to the sensing node S. The driving transistor M2 is configured to be turned on under the control of the voltage of the data node G, and receive and transmit a seventh voltage signal to the sensing node S.

For example, as shown in fig. 3, a first pole of the storage capacitor C is electrically connected to the data node G, and a second pole of the storage capacitor C is electrically connected to the sensing node S. The switching transistor M1 charges the storage capacitor C during the process of charging the data node G.

For example, as shown in fig. 3, the gate of the sensing transistor M3 is electrically connected to the second scan signal terminal G2, the first pole of the sensing transistor M3 is electrically connected to the sensing signal terminal SENSE, and the second pole of the sensing transistor M3 is electrically connected to the sensing node S. The sensing transistor M3 is configured to detect the electrical characteristics of the sensing node S under the control of the second scan signal transmitted from the second scan signal terminal G2 to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and/or the carrier mobility of the driving transistor M2.

Here, the SENSE signal terminal SENSE may provide a reset signal for resetting the sensing node S or a sensing signal for acquiring, for example, a threshold voltage of the driving transistor M2.

Illustratively, the light emitting device L may be an OLED light emitting device.

For example, as shown in fig. 3, the anode of the light emitting device L is electrically connected to the sensing node S, and the cathode of the light emitting device L is electrically connected to the eighth voltage signal terminal ELVSS. The light emitting device L is configured to emit light under the cooperation of the seventh voltage signal from the sensing node S and the eighth voltage signal transmitted from the eighth voltage signal terminal ELVSS.

In the display period of one frame, the operation process of the pixel driving circuit 300 may include, for example, a blanking period and a driving period, and the blanking period may be used to obtain the threshold voltage of the driving transistor M2, and the detailed operation process of the blanking period is not described herein too much. As shown in fig. 4, the driving phase may include, for example: a reset and data writing phase t1, and a light-emitting phase t2 and a black insertion phase t3 which are alternately repeated.

As shown in fig. 4, the reset and data write phase t1 can be divided into a reset phase (i) and a data write phase (ii).

In the reset phase, the first scan signal is at a high level, the enable signal is at a high level, the second scan signal is at a high level, and the data signal is at a low level.

At this time, the switching transistor M1 is turned on under the control of the first scan signal, transmits the data signal to the data node G, and resets the data node G.

In the second data writing stage, the first scan signal is at a high level, the enable signal is at a high level, the second scan signal is at a high level, and the data signal is at a high level.

At this time, the switching transistor M1 is turned on under the control of the first scan signal, transmits the data signal to the data node G, makes the data node G at a high level, and charges the storage capacitor C. The control transistor M4 is turned on under the control of the enable signal, and transmits the seventh voltage signal to the first pole of the driving transistor M2.

In the light emission period t2, the first scan signal is at a low level, the enable signal is at a high level, and the second scan signal is at a low level.

At this time, the switching transistor M1 turns off when the first scan signal is at a high level, and the storage capacitor C starts discharging, so that the potential of the data node G is maintained at a high potential. The control transistor M4 is turned on under the control of the enable signal, and transmits the seventh voltage signal to the first pole of the driving transistor M2. The driving transistor M2 is turned on under the control of the data node G, transmits the seventh voltage signal to the sensing node S, and raises the potential of the sensing node S, so that the potential of the data node G is further raised due to the bootstrap effect of the storage capacitor C and maintains a high level for a period of time. In this way, the light emitting device L is driven to emit light according to the seventh voltage signal from the sensing node S and the eighth voltage signal transmitted from the eighth voltage signal terminal ELVSS.

In the black insertion period t3, the first scan signal is at a low level, the enable signal is at a low level, and the second scan signal is at a low level.

At this time, the control transistor M4 is turned off under the control of the enable signal, so that the seventh voltage signal cannot be transmitted to the first electrode of the driving transistor M2 and further cannot be transmitted to the anode of the light emitting device L, thereby stopping the light emitting device L from emitting light.

By alternately performing the light-emitting period t2 and the black insertion period t3 in one frame display period, the light-emitting device L can alternately emit light and stop emitting light in one frame display period, so that the light-emitting duration of the light-emitting device L in one frame display period can be reduced, the response time of a dynamic picture can be increased, black insertion with short time interval and high frequency can be realized, a black picture can be prevented from being captured by human eyes, and a flicker phenomenon of the displayed picture can be avoided.

In some examples, the display device 1000 further comprises: the scan driving circuit 400. The scan driving circuit 400 may be located on the same side of the substrate 200 as the plurality of sub-pixels P, the gate lines GL, the data lines DL, and the enable signal lines EL.

In some examples, as shown in fig. 26 and 28, the scan driving circuit 400 includes a plurality of shift registers 100. The shift register 100 is electrically connected to the gate of the control transistor M4 of the pixel driving circuit 300 to provide an enable signal.

The structure of the shift register 100 will be described with reference to fig. 5 and 6.

In some examples, as shown in fig. 5 and 6, the shift register 100 includes: a first input circuit 10, a second input circuit 20, a first control circuit 30, a first output circuit 40, and a second output circuit 50.

Illustratively, as shown in fig. 5 and 6, the first input circuit 10 is electrically connected to the first signal terminal S1, the first clock signal terminal CKA, and the first node N1. The first input circuit 10 is configured to transmit the first signal received at the first signal terminal S1 to the first node N1 under control of the first clock signal transmitted by the first clock signal terminal CKA.

For example, in the case where the first clock signal is at a high level, the first input circuit 10 may receive and transmit the first signal to the first node N1 under the control of the first clock signal.

Illustratively, as shown in fig. 5 and 6, the second input circuit 20 is electrically connected to the second signal terminal S2, the third signal terminal S3, the second voltage signal terminal VGL, the fourth signal terminal S4 and the second node N2. The second input circuit 20 is configured to transmit the third signal received at the third signal terminal S3 to the second node N2 under the control of the second signal transmitted at the second signal terminal S2, and transmit the second voltage signal received at the second voltage signal terminal VGL to the second node N2 under the control of the fourth signal terminal S4. The second and third signal terminals S2 and S3 each include one of the first voltage signal terminal VGH and the first clock signal terminal CKA.

Here, the second signal terminal S2 and the third signal terminal S3 may be the same signal terminal, for example, the second signal terminal S2 and the third signal terminal S3 may both be the first voltage signal terminal VGH, or the second signal terminal S2 and the third signal terminal S3 may both be the first clock signal terminal CKA. The second signal terminal S2 and the third signal terminal S3 may be different signal terminals, for example, the second signal terminal S2 is the first voltage signal terminal VGH, and the third signal terminal S3 is the first clock signal terminal CKA, or the second signal terminal S2 is the first clock signal terminal CKA, and the third signal terminal S3 is the first voltage signal terminal VGH.

For example, in a case where the second signal is at a high level, the second input circuit 20 may receive and transmit the third signal to the second node N2 under the control of the second signal, and in a case where the fourth signal is at a high level, the second input circuit 20 may receive and transmit the second voltage signal to the second node N2 under the control of the fourth signal.

When the second signal is at a high level and the fourth signal is at a high level, the voltage of the second node N2 is controlled by the second voltage signal.

For example, as shown in fig. 5 and 6, the first control circuit 30 is electrically connected to the first node N1, the second node N2, and the second voltage signal terminal VGL. The first control circuit 30 is configured to transmit a second voltage signal to the first node N1 under the control of the voltage of the second node N2.

For example, in a case where the voltage of the second node N2 is at a high level, the first control circuit 30 may receive and transmit the second voltage signal to the first node N1 under the control of the voltage of the second node N2.

This makes it possible to turn on the first control circuit 30, transmit the second voltage signal to the first node N1, and make the level of the first node N1 low when the second input circuit 20 is turned on and transmits a high level to the second node N2, thereby preventing the first output circuit 40 from being turned on.

Illustratively, as shown in fig. 5 and 6, the first output circuit 40 is electrically connected to the first node N1, the first voltage signal terminal VGH, and the output signal terminal OUT < N >. The first output circuit 40 is configured to transmit a first voltage signal to the output signal terminal OUT < N > under control of the voltage of the first node N1.

For example, in a case where the voltage of the first node N1 is at a high level, the first output circuit 40 may receive and transmit a first voltage signal to the output signal terminal OUT < N > under the control of the voltage of the first node N1.

Illustratively, as shown in fig. 5 and 6, the second output circuit 50 is electrically connected to at least the second node N2, the second voltage signal terminal VGL, and the output signal terminal OUT < N >. The second output circuit 50 is configured to transmit a second voltage signal to the output signal terminal OUT < N > under control of the voltage of the second node N2.

For example, in a case where the voltage of the second node N2 is at a high level, the second output circuit 50 may receive and transmit the second voltage signal to the output signal terminal OUT < N > under the control of the voltage of the second node N2.

It should be noted that the first voltage signal terminal VGH may be, for example, a dc high voltage signal terminal, and in this case, the first voltage signal may be a dc high level signal. The second voltage signal terminal VGL may be, for example, a dc low voltage signal terminal, and in this case, the second voltage signal may be a dc low level signal.

It should be noted that the "high level" and the "low level" mentioned herein are relative only, and do not define the magnitude relationship between the voltage value of the high level signal and 0V, nor the magnitude relationship between the voltage value of the low level signal and 0V.

Illustratively, the output signal terminal OUT < N > of the shift register 100 is electrically connected to the gate of the control transistor M4 to provide an enable signal.

Some of the operation of the shift register 100 is schematically described below.

For example, in a case where the first input circuit 10 is turned on and the signal transmitted to the first node N1 is at a high level, the first output circuit 40 may be turned on under the control of the first node N1 to transmit the first voltage signal (high level signal) to the output signal terminal OUT < N >.

For another example, in a case where the second input circuit 20 is turned on and the signal transmitted to the second node N2 is at a high level, the second output circuit 50 may be turned on under the control of the second node N2 to transmit the second voltage signal (low level signal) to the output signal terminal OUT < N >; at the same time, the first control circuit 30 is also turned on under the control of the second node N2, and transmits the second voltage signal to the first node N1, so that the signal at the first node N1 is in a low state, thereby ensuring that the first output circuit 40 is not turned on under the control of the first node N1 and is in a turned-off state.

Therefore, the shift register 100 in the present application may output the first voltage signal (high level signal) alone or the second voltage signal (low level signal) alone, so that the first output circuit 40 and the second output circuit 50 in the shift register 100 may be controlled to be turned on in different time periods by cooperating with the respective signal terminals, respectively, to obtain a desired waveform, for example, the waveform may be a continuous high level, a continuous low level, a low level of a period of time followed by a high level of a period of time, or a low level of a period of time followed by a high level of a period of time.

Thus, the shift register 100 provided by some embodiments of the present disclosure may provide, by providing the first input circuit 10, the second input circuit 20, the first control circuit 30, the first output circuit 40, and the second output circuit 50, and electrically connecting each circuit to a corresponding signal terminal, by using the mutual cooperation between each circuit and each signal terminal, the first output circuit 40 and the second output circuit 50 are turned on in different time periods, so that the first voltage signal output by the first output circuit 40 and the second voltage signal output by the second output circuit 50 cooperate to form an output signal with alternating high and low levels, the waveform of the output signal is the same as the waveform of the enable signal EM required by the pixel driving circuit 300 in the display apparatus 1000, so that the enable signal EM may be provided to different pixel driving circuits 300 in the display apparatus 1000 by using a plurality of shift registers 100, display driving corresponding to different sub-pixels P is realized. By adopting the shift register 100 to display and drive the sub-pixel P, the light-emitting stage t2 and the black insertion stage t3 can be alternately performed in one frame display stage, and the light-emitting device L can alternately emit light and stop emitting light in one frame display process, so that the light-emitting duration of the light-emitting device L in one frame display stage can be reduced, the dynamic picture response time can be enhanced, and the black insertion with short time interval and high frequency can be realized, so that the black picture can be prevented from being captured by human eyes, and the display picture can be prevented from flickering.

Next, referring to fig. 6 and 7, the structure of the first input circuit 10, the second input circuit 20, the first control circuit 30, the first output circuit 40, and the second output circuit 50 included in the shift register 100 will be schematically described.

In some examples, as shown in fig. 6, the first input circuit 10 includes: the first transistor T1. The gate of the first transistor T1 is electrically connected to the first clock signal terminal CKA, the first pole of the first transistor T1 is electrically connected to the first signal terminal S1, and the second pole of the first transistor T1 is electrically connected to the first node N1.

For example, in a case where the level of the first clock signal is a high level, the first transistor T1 may be turned on under the control of the first clock signal, receive and transmit the first signal to the first node N1, and charge the first node N1.

In some examples, as shown in fig. 6, the second input circuit 20 includes: a second transistor T2 and a third transistor T3.

The gate of the second transistor T2 is electrically connected to the second signal terminal S2, the first pole of the second transistor T2 is electrically connected to the third signal terminal S3, and the second pole of the second transistor T2 is electrically connected to the second node N2.

For example, in a case where the level of the second signal is a high level, the second transistor T2 may be turned on under the control of the second signal, receive and transmit the third signal to the second node N2, and charge the second node N2.

A gate of the third transistor T3 is electrically connected to the fourth signal terminal S4, a first pole of the third transistor T3 is electrically connected to the second voltage signal terminal VGL, and a second pole of the third transistor T3 is electrically connected to the second node N2.

For example, in a case where the level of the fourth signal is a high level, the third transistor T3 may be turned on under the control of the fourth signal, and receive and transmit the second voltage signal to the second node N2.

Note that the width-to-length ratio of the third transistor T3 is larger than that of the second transistor T2. Thus, in the case where the third transistor T3 is turned on, it is ensured that the voltage of the second node N2 is controlled by the second voltage signal transmitted by the third transistor T3. That is, when the third transistor T3 is turned on, whether the second transistor T2 is turned on or not, the voltage of the second node N2 is at a low level, which is beneficial to preventing the voltage of the second node N2 from being affected by the third signal transmitted by the second transistor T2 and ensuring the stability of the voltage of the second node N2.

In some examples, as shown in fig. 7, the second input circuit 20 further includes: a fourth transistor T4 and a fifth transistor T5.

A gate of the fourth transistor T4 is electrically connected to the third node N3, a first pole of the fourth transistor T4 is electrically connected to the third signal terminal S3, and a second pole of the fourth transistor T4 is electrically connected to the second node N2. The second pole of the second transistor T2 is also electrically connected to the third node N3, and to the second node N2 through the fourth transistor T4.

For example, at this time, in case that the level of the second signal is a high level, the second transistor T2 may be turned on under the control of the second signal, and receive and transmit the third signal to the third node N3. In case that the voltage of the third node N3 is at a high level, the fourth transistor T4 may be turned on under the control of the voltage of the third node, receive and transmit the third signal to the second node N2.

A gate of the fifth transistor T5 is electrically connected to the fourth signal terminal S4, a first pole of the fifth transistor T5 is electrically connected to the second voltage signal terminal VGL, and a second pole of the fifth transistor T5 is electrically connected to the third node N3.

For example, in a case where the level of the fourth signal is a high level, the fifth transistor T5 may be turned on under the control of the fourth signal, and receive and transmit the second voltage signal to the third node N3.

The present disclosure has various options for the arrangement of the first signal terminal S1 and the fourth signal terminal S4, and the arrangement can be selected according to actual needs.

In some examples, the first signal terminal S1 is the first voltage signal terminal VGH and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, or the first signal terminal S1 is the first cascade signal terminal OUT < N-1> and the fourth signal terminal S4 is the first node N1.

In some examples, as shown in fig. 8 to 11, the shift register 100 further includes a second control circuit 60. The second control circuit 60 is electrically connected to the first cascade signal terminal OUT < N-1>, the third voltage signal terminal V3, the fourth voltage signal terminal V4, the second cascade signal terminal OUT < N +1>, and the fourth node N4. The second control circuit 60 is configured to transmit the first cascade signal transmitted by the first cascade signal terminal OUT < N-1> to the fourth node N4 under the control of the third voltage signal transmitted by the third voltage signal terminal V3, or transmit the second cascade signal transmitted by the second cascade signal terminal OUT < N +1> to the fourth node N4 under the control of the fourth voltage signal transmitted by the fourth voltage signal terminal V4.

For example, in the case that the third voltage signal is at a high level, the second control circuit 60 may receive and transmit the first cascade signal to the fourth node N4 under the control of the third voltage signal. Alternatively, in the case where the fourth voltage signal is at a high level, the second control circuit 60 may receive and transmit the second cascade signal to the fourth node N4 under the control of the fourth voltage signal.

In the shift registers 100 of the scan driving circuit 400, the output signal terminal of the nth shift register is denoted as OUT < N >, the output signal terminal of the N-1 th shift register is denoted as the first cascade signal terminal OUT < N-1>, and the output signal terminal of the N +1 th shift register is denoted as the second cascade signal terminal OUT < N +1 >.

The third voltage signal and the fourth voltage signal are inverse signals.

That is, in the case where the level of the third voltage signal is a high level, the level of the fourth voltage signal is a low level; when the level of the third voltage signal is at a low level, the level of the fourth voltage signal is at a high level. This ensures that the second control circuit 60 can only transmit one of the first cascade signal terminal OUT < N-1> and the second cascade signal terminal OUT < N +1> to the fourth node N4.

It should be noted that, in practical applications, a user may adjust a viewing state of the display apparatus 1000, for example, a landscape viewing state or a portrait viewing state, in which the display apparatus 1000 also needs to adjust a scanning sequence of the scanning driving circuit 400 to adapt to the landscape viewing state or the portrait viewing state when displaying a dynamic picture, and by setting the second control circuit, the first cascade signal or the second cascade signal may be transmitted to the fourth node N4, so that the scanning sequence of the scanning driving circuit 400 may be adjusted according to different viewing states of the user, and further, it is ensured that the display apparatus 1000 may normally display the picture.

In the present disclosure, the specific arrangement position of the second control circuit 60 may be selected variously, for example, in relation to the specific arrangement manner of the first signal terminal S1 and the fourth signal terminal S4.

As shown in FIGS. 8 and 9, in the case where the first signal terminal S1 is the first cascade signal terminal OUT < N-1>, and the fourth signal terminal S4 is the first node N1, the first input circuit 10 is further electrically connected to the fourth node N4, and is electrically connected to the first cascade signal terminal OUT < N-1> via the second control circuit 60.

As shown in fig. 10 and 11, in the case where the first signal terminal S1 is the first voltage signal terminal VGH and the fourth signal terminal is the first cascade signal terminal OUT < N-1>, the second input circuit 20 is also electrically connected to the fourth node N4 and to the first cascade signal terminal OUT < N-1> through the second control circuit 60.

In some examples, as shown in fig. 9 and 11, the second control circuit 60 includes: a sixth transistor T6 and a seventh transistor T7.

The gate of the sixth transistor T6 is electrically connected to the third voltage signal terminal V3, the first pole of the sixth transistor T6 is electrically connected to the first cascade signal terminal OUT < N-1>, and the second pole of the sixth transistor T6 is electrically connected to the fourth node N4.

For example, in case that the level of the third voltage signal is a high level, the sixth transistor T6 may be turned on under the control of the third voltage signal, and receive and transmit the first cascade signal to the fourth node N4.

A gate of the seventh transistor T7 is electrically connected to the fourth voltage signal terminal V4, a first pole of the seventh transistor T7 is electrically connected to the second cascade signal terminal OUT < N +1>, and a second pole of the seventh transistor T7 is electrically connected to the fourth node N4.

For example, in case that the level of the fourth voltage signal is a high level, the seventh transistor T7 may be turned on under the control of the fourth voltage signal, and receive and transmit the second cascade signal to the fourth node N4.

As shown in fig. 8 and 9, in case that the first signal terminal S1 is the first cascade signal terminal OUT < N-1>, the fourth signal terminal S4 is the first node N1, and the first input circuit 10 includes the first transistor T1, the first pole of the first transistor T1 is also electrically connected to the fourth node N4 and to the first cascade signal terminal OUT < N-1> through the sixth transistor T6.

As shown in fig. 10 and 11, in case that the first signal terminal S1 is the first voltage signal terminal VGH, the fourth signal terminal is the first cascade signal terminal OUT < N-1>, and the second input circuit 20 includes the third transistor T3, the gate of the third transistor T3 is also electrically connected to the fourth node N4 and to the first cascade signal terminal OUT < N-1> through the sixth transistor T6.

In some examples, as shown in fig. 8, the first control circuit 30 includes: and an eighth transistor T8. A gate of the eighth transistor T8 is electrically connected to the second node N2, a first pole of the eighth transistor T8 is electrically connected to the second voltage signal terminal VGL, and a second pole of the eighth transistor is electrically connected to the first node N1.

For example, in case that the level of the second node N2 is a high level, the eighth transistor T8 may be turned on under the control of the voltage of the second node N2, and receive and transmit the second voltage signal to the first node N1.

In some examples, as shown in fig. 8, the first output circuit 40 includes: a ninth transistor T9 and a first capacitor C1.

A gate of the ninth transistor T9 is electrically connected to the first node N1, a first pole of the ninth transistor T9 is electrically connected to the first voltage signal terminal VGH, and a second pole of the ninth transistor T9 is electrically connected to the output signal terminal OUT < N >. A first pole of the first capacitor C1 is electrically connected to the first node N1, and a second pole of the first capacitor C1 is electrically connected to the output signal terminal OUT < N >.

For example, in case that the level of the first node N1 is a high level, the ninth transistor T9 may be turned on under the control of the voltage of the first node N1, and receive and transmit the first voltage signal to the output signal terminal OUT < N >.

It is understood that the first capacitor C1 is also charged during the transmission of the first signal to the first node N1 by the first transistor T1 in the first input circuit 10. With the first transistor T1 turned off, the first capacitor C1 may be discharged, maintaining the voltage of the first node N1 at the voltage value of the first signal, so that the ninth transistor T9 maintains a turn-on state.

In some examples, as shown in fig. 6, the second output circuit 50 includes: a tenth transistor T10, and a second capacitor C2.

A gate of the tenth transistor T10 is electrically connected to the second node N2, a first pole of the tenth transistor T10 is electrically connected to the second voltage signal terminal VGL, and a second pole of the tenth transistor T10 is electrically connected to the output signal terminal OUT < N >. A first pole of the second capacitor C2 is electrically connected to the second node N2, and a second pole of the second capacitor C2 is electrically connected to the second voltage signal terminal VGL.

For example, in case that the level of the second node N2 is a high level, the tenth transistor T10 may be turned on under the control of the voltage of the second node N2, and receive and transmit the second voltage signal to the output signal terminal OUT < N >.

It is understood that the second capacitor C2 is also charged during the transmission of the first voltage signal to the second node N2 by the second transistor T2 in the second input circuit 20. With the second transistor T2 turned off, the second capacitor C2 may be discharged, maintaining the voltage of the second node N2 at the voltage value of the first voltage signal, so that the tenth transistor T10 maintains a turn-on state.

In some examples, as shown in fig. 12 and 13, in the case where the second output circuit 50 is also electrically connected to the second clock signal terminal CKB, the second pole of the second capacitor C2 is electrically connected to the second voltage signal terminal VGL or the second clock signal terminal CKB.

As can be seen from the timing diagram shown in fig. 26, the waveform of the second clock signal terminal CKB is a high level and a low level alternately, when the second pole of the second capacitor C2 is electrically connected to the second clock signal terminal CKB, and when the level of the second clock signal terminal CKB changes from the low level to the high level, the potential of the second pole of the second capacitor C2 is raised, due to the coupling and bootstrapping effects of the capacitors, so that the potential of the first pole of the second capacitor C2 is correspondingly raised, and the first pole of the second capacitor C2 is electrically connected to the second node N2, so that the potential of the second node N2 can be raised, the tenth transistor T10 is turned on more fully, and the second voltage signal can be transmitted to the output signal terminal OUT < N >.

In some examples, as shown in fig. 14 and 15, in the case where the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, the shift register 100 further includes: a third control circuit 70.

The third control circuit 70 is electrically connected to the fifth node N5, the second clock signal terminal CKB, and the first node N1. The second control circuit 70 is configured to transmit the second clock signal to the first node N1 under the control of the voltage at the fifth node N5 and the second clock signal transmitted by the second clock signal terminal CKB. At this time, the first input circuit 10 is also electrically connected to the fifth node N5, and is electrically connected to the first node N1 through the third control circuit 70.

For example, the first input circuit 10 may transmit the first voltage signal to the fifth node N5 such that the voltage of the fifth node is at a high level. At this time, in case that the levels of the second clock signal are both high levels, the third control circuit 70 may receive and transmit the second clock signal to the first node N1 under the control of the voltage of the fifth node N5 and the second clock signal.

In some examples, as shown in fig. 15, the third control circuit includes: an eleventh transistor T11, a twelfth transistor T12, and a third capacitor C3.

A gate of the eleventh transistor T11 is electrically connected to the fifth node N5, a first pole of the eleventh transistor T11 is electrically connected to the second clock signal terminal CKB, and a second pole of the eleventh transistor T11 is electrically connected to the sixth node N6. A first pole of the third capacitor C3 is electrically connected to the fifth node N5, and a second pole of the third capacitor C3 is electrically connected to the sixth node N6.

At this time, in the case where the first input circuit 10 includes the first transistor T1, the second pole of the first transistor T1 is electrically connected to the fifth node N5, and is electrically connected to the first node through the eleventh transistor T11 and the twelfth transistor T12 in order. It is to be understood that, in case the first transistor T1 is turned on, the first transistor T1 first transmits the first voltage signal to the fifth node N5 to charge the fifth node N5.

For example, in case that the level of the fifth node N5 is a high level, the eleventh transistor T11 may be turned on under the control of the voltage of the fifth node N5, and receive and transmit the second clock signal to the sixth node N6.

It is understood that the third capacitor C3 is also charged during the transmission of the first voltage signal to the fifth node N5 by the first transistor T1 in the first input circuit 10. With the first transistor T1 turned off, the third capacitor C3 may be discharged, maintaining the voltage of the first node N1 at the voltage value of the first voltage signal, so that the eleventh transistor T11 maintains a turn-on state.

A gate of the twelfth transistor T12 is electrically connected to the second clock signal terminal CKB, a first pole of the twelfth transistor T12 is electrically connected to the sixth node N6, and a second pole of the twelfth transistor T12 is electrically connected to the first node N1.

For example, in case that the level of the second clock signal is a high level, the twelfth transistor T12 may be turned on under the control of the second clock signal, and receive and transmit the signal at the sixth node N6 to the first node N1.

In some examples, as shown in fig. 14 and 15, in the case where the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, the shift register 100 further includes: a fourth control circuit 80.

The fourth control circuit 80 is electrically connected to the fifth node N5, the second voltage signal terminal VGL, the second clock signal terminal CKB, and the second node N2. The fourth control circuit 80 is configured to transmit the second voltage signal to the second node N2 under the control of the voltage of the fifth node N5 and the second clock signal.

For example, in a case where both the level of the fifth node N5 and the level of the second clock signal are high level, the fourth control circuit 80 may receive and transmit the second voltage signal to the second node N2 under the control of the voltage of the fifth node N5 and the second clock signal.

Thus, when the first input circuit 10 is turned on and inputs a high level signal and the level of the second clock signal is high, the fourth control circuit 80 is turned on to transmit the second voltage signal to the second node N2, so that the level of the second node N2 is ensured to be low, and the second output circuit 50 is prevented from being turned on.

In some examples, as shown in fig. 15, the fourth control circuit 80 includes: a thirteenth transistor T13 and a fourteenth transistor T14.

A gate of the thirteenth transistor T13 is electrically connected to the fifth node N5, a first pole of the thirteenth transistor T13 is electrically connected to the second voltage signal terminal VGL, and a second pole of the thirteenth transistor T13 is electrically connected to the first pole of the fourteenth transistor T14. A gate of the fourteenth transistor T14 is electrically connected to the second clock signal terminal CKB, and a second pole of the fourteenth transistor T14 is electrically connected to the second node N2.

For example, in case that the level of the fifth node N5 is a high level, the thirteenth transistor T13 may be turned on under the control of the voltage of the fifth node N5, receive and transmit the second voltage signal to the first pole of the fourteenth transistor T14; in case that the level of the second clock signal is a high level, the fourteenth transistor T14 may be turned on under the control of the second clock signal, and receive and transmit the second voltage signal received at the first electrode of the fourteenth transistor T14 to the second node N2.

In some examples, as shown in fig. 14 and 15, in the case where the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, the shift register 100 further includes: a fifth control circuit 90.

The fifth control circuit 90 is electrically connected to one of the second voltage signal terminal VGL and the first clock signal terminal CKA, the second node N2, and the fifth node N5. The fifth control circuit 90 is configured to transmit the second voltage signal or the first clock signal to the fifth node N5 under the control of the voltage of the second node N2.

For example, in the case where the level of the second node N2 is a high level, the fifth control circuit 90 may receive and transmit the second voltage signal or the first clock signal to the fifth node N5 under the control of the voltage of the second node N2.

Thus, when the second input circuit 20 is turned on and a high level is input to the second node N2, the fifth control circuit 90 is turned on to transmit the second voltage signal or the first clock signal in a low level state to the fifth node N5, so as to ensure that the level of the fifth node N5 is low, the third control circuit 70 is not turned on, and the first output circuit 40 is prevented from being turned on.

In some examples, as shown in fig. 15, the fifth control circuit 90 includes: and a fifteenth transistor T15. A gate of the fifteenth transistor T15 is electrically connected to the second node N2, a first pole of the fifteenth transistor T15 is electrically connected to one of the second voltage signal terminal VGL and the first clock signal terminal CKA, and a second pole of the fifteenth transistor T15 is electrically connected to the fifth node N5.

For example, in case that the level of the second node N2 is a high level, the fifteenth transistor T15 may be turned on under the control of the voltage of the second node N2, and receive and transmit the second voltage signal or the first clock signal to the fifth node N5.

In some examples, as shown in fig. 14 and 15, in the case where the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, the shift register 100 further includes: a first switching circuit 21.

The first switch circuit 21 is electrically connected to the second node N2, the seventh node N7 and the first clock signal terminal CKA; the first switch circuit 21 is configured to transmit a signal from the seventh node N7 to the second node N2 under the control of the first clock signal. At this time, the second input circuit 20 is also electrically connected to the seventh node N7, and is electrically connected to the second node N2 through the first switch circuit 21.

For example, in a case where the level of the first clock signal is a high level, the first switch circuit 21 may receive and transmit a signal of the seventh node N7 (which may be, for example, a third signal or a second voltage signal) to the second node N2 under the control of the voltage of the first clock signal.

In some examples, as shown in fig. 15, the first switching circuit 21 includes: and a sixteenth transistor T16. A gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal CKA, a first pole of the sixteenth transistor T16 is electrically connected to the seventh node N7, and a second pole of the sixteenth transistor T16 is electrically connected to the second node N2.

For example, in case that the level of the first clock signal is a high level, the sixteenth transistor T16 may be turned on under the control of the first clock signal, and receive and transmit the signal of the seventh node N7 to the second node N2.

At this time, in the case where the second input circuit 20 includes the second transistor T2 and the third transistor T3, the second pole of the second transistor T2 is electrically connected to the seventh node N7 and to the second node N2 through the sixteenth transistor T16, and the second pole of the third transistor T3 is electrically connected to the seventh node N7 and to the second node N2 through the sixteenth transistor T16.

In some examples, as shown in fig. 16 to 18, the shift register 100 further includes: a third input circuit 20 'and a sixth control circuit 30'.

The third input circuit 20' is electrically connected to the third signal terminal S3, the fifth voltage signal terminal V5, the fourth signal terminal S4 and the eighth node N8. The third input circuit 20' is configured to transmit the third signal to the eighth node N8 under the control of the fifth voltage signal transmitted from the fifth voltage signal terminal V5, or to transmit the second voltage signal to the eighth node N8 under the control of the second signal. The third signal terminal S3 includes one of the first voltage signal terminal VGH, the first clock signal terminal CKA, and the fifth voltage signal terminal V5.

For example, in a case where the level of the fifth voltage signal is a high level, the third input circuit 20' may receive and transmit the third signal to the eighth node N8 under the control of the fifth voltage signal; alternatively, in the case where the level of the second signal is a high level, the third input circuit 20' may receive and transmit the second voltage signal to the eighth node N8 under the control of the second signal.

The sixth control circuit 30' is electrically connected to the eighth node N8, the first node N1, and the second voltage signal terminal VGL. The sixth control circuit 30' is configured to transmit the second voltage signal to the first node N1 under the control of the voltage of the eighth node N8.

At this time, the second output circuit 50 is also electrically connected to the eighth node N8, and the second output circuit 50 is further configured to transmit the second voltage signal to the output signal terminal OUT < N > under the control of the voltage of the eighth node N8.

For example, in case that the level of the eighth node N8 is a high level, the second output circuit 50 may receive and transmit the second voltage signal to the output signal terminal OUT < N > under the control of the voltage of the eighth node N8.

This makes it possible to turn on the sixth control circuit 30 'to transmit the second voltage signal to the first node N1 and make the level of the first node N1 low when the third input circuit 20' is turned on and transmits a high level to the eighth node N8, thereby preventing the first output circuit 40 from being turned on.

Illustratively, the second signal terminal S2 further includes a sixth voltage signal terminal V6. In case the second signal terminal is the sixth voltage signal terminal V6, the second input circuit 20 is further configured to transmit the third signal to the second node N2 under the control of the sixth voltage signal transmitted by the sixth voltage signal terminal V6.

For example, in a case where the level of the sixth voltage signal is a high level, the second input circuit 20 may receive and transmit the third signal to the second node N2 under the control of the sixth voltage signal.

At this time, the fifth voltage signal and the sixth voltage signal are inverse signals. This ensures that only one of the second input circuit 20 and the third input circuit 20 'can be turned on and transmit the third signal at the same time, that is, the second input circuit 20 and the third input circuit 20' can be operated alternately in time, thereby alleviating the load on the circuit caused by continuous operation.

In some examples, as shown in fig. 17, the third input circuit 20' includes: a seventeenth transistor T17 and an eighteenth transistor T18.

A gate of the seventeenth transistor T17 is electrically connected to the fifth voltage signal terminal V5, a first pole of the seventeenth transistor T17 is electrically connected to the third signal terminal S3, and a second pole of the seventeenth transistor T17 is electrically connected to the eighth node N8.

For example, in a case where the level of the fifth voltage signal is a high level, the seventeenth transistor T17 may be turned on under the control of the fifth voltage signal, receive and transmit the third signal to the eighth node N8, and charge the eighth node N8.

A gate of the eighteenth transistor T18 is electrically connected to the second signal terminal S2, a first pole of the eighteenth transistor T18 is electrically connected to the second voltage signal terminal VGL, and a second pole of the eighteenth transistor T18 is electrically connected to the eighth node N8.

For example, in case that the level of the second signal is a high level, the eighteenth transistor T18 may be turned on under the control of the second signal, receive and transmit the second voltage signal to the eighth node N8, and charge the eighth node N8.

Note that the width-to-length ratio of the eighteenth transistor T18 is larger than that of the seventeenth transistor T17. Thus, in case that the eighteenth transistor T18 is turned on, it is ensured that the voltage of the eighth node N8 is controlled by the second voltage signal transmitted by the eighteenth transistor T18. That is, when the eighteenth transistor T18 is turned on, whether the seventeenth transistor T17 is turned on or not, the voltage at the eighth node N8 is at a low level, which is beneficial to prevent the voltage at the eighth node N8 from being affected by the third signal transmitted by the seventeenth transistor T17, and to ensure the stability of the voltage at the second node N2.

Illustratively, as shown in fig. 18, the third input circuit 20' further includes: a twenty-first transistor T21 and a twenty-second transistor T22.

A gate of the twenty-first transistor T21 is electrically connected to the ninth node N9, a first pole of the twenty-first transistor T21 is electrically connected to the third signal terminal S3, and a second pole of the twenty-first transistor T21 is electrically connected to the eighth node N8.

For example, in case that the level of the ninth node N9 is a high level, the twenty-first transistor T21 may be turned on under the control of the ninth node N9, and receive and transmit the third signal to the eighth node N8.

A gate of the twentieth transistor T22 is electrically connected to the fourth signal terminal S4, a first pole of the twentieth transistor T22 is electrically connected to the second voltage signal terminal VGL, and a second pole of the twentieth transistor T22 is electrically connected to the eighth node N8.

For example, in case that the level of the fourth signal is a high level, the twentieth transistor T22 may be turned on under the control of the fourth signal, and receive and transmit the second voltage signal to the eighth node N8.

At this time, the second pole of the seventeenth transistor T17 is also electrically connected to the ninth node N9, and to the eighth node N8 through the twenty-first transistor T21.

In some examples, as shown in fig. 17 and 18, the sixth control circuit 30' includes: a nineteenth transistor T19.

A gate of the nineteenth transistor T19 is electrically connected to the eighth node N8, a first pole of the nineteenth transistor T19 is electrically connected to the second voltage signal terminal VGL, and a second pole of the nineteenth transistor T19 is electrically connected to the first node N1.

For example, in a case where the level of the eighth node N8 is a high level, the nineteenth transistor T19 may be turned on under the control of the eighth node N8, and receive and transmit the second voltage signal to the first node N1.

In some examples, as shown in fig. 17 and 18, the second output circuit 50 further includes: a twentieth transistor T20.

A gate of the twentieth transistor T20 is electrically connected to the eighth node N8, a first pole of the twentieth transistor T20 is electrically connected to the second voltage signal terminal VGL, and a second pole of the twentieth transistor T20 is electrically connected to the output signal terminal OUT < N >.

For example, in case that the level of the eighth node N8 is a high level, the twentieth transistor T20 may be turned on under the control of the eighth node N8, and receive and transmit the second voltage signal to the output signal terminal OUT < N >.

In some examples, as shown in fig. 19 and 20, in the case where the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, the shift register 100 further includes: a seventh control circuit 80 ', an eighth control circuit 90 ' and a second switching circuit 21 '.

The seventh control circuit 80' is electrically connected to the fifth node N5, the second voltage signal terminal VGL, the second clock signal terminal CKB, and the eighth node N8. The seventh control circuit 80' is configured to transmit the second voltage signal to the eighth node N8 under the control of the voltage of the fifth node N5 and the second clock signal transmitted by the second clock signal terminal CKB.

For example, in the case where the levels of the fifth node N5 and the second clock signal are both high, the seventh control circuit 80' receives and transmits the second voltage signal to the eighth node N8 under the control of the fifth node N5 and the second clock signal.

Thus, when the first input circuit 10 is turned on and a high level signal is input, the seventh control circuit 80 'is turned on to transmit the second voltage signal to the eighth node N8, so that the level of the eighth node N8 is ensured to be a low level, and the third output circuit 20' is prevented from being turned on.

The eighth control circuit 90' is electrically connected to the eighth node N8, the fifth node N5 and the second voltage signal terminal VGL. The eighth control circuit 90' is configured to transmit the second voltage signal to the fifth node N5 under the control of the voltage of the eighth node N8.

For example, in a case where the levels of the eighth node N8 are all high, the eighth control circuit 90' receives and transmits the second voltage signal to the fifth node N5 under the control of the eighth node N8.

Thus, when the third input circuit 20 'is turned on and a high level is input to the eighth node N8, the eighth control circuit 90' is turned on to transmit the second voltage signal to the fifth node N5, so that the level of the fifth node N5 is low, the third control circuit 70 is not turned on, and the first output circuit 40 is prevented from being turned on.

The second switch circuit 21' is electrically connected to the first clock signal terminal CKA, the tenth node N10, and the eighth node N8. The second switch circuit 21' is configured to transmit the signal of the tenth node N10 to the eighth node N8 under the control of the first clock signal transmitted by the first clock signal terminal CKA.

For example, in the case where the first clock signal is at a high level, the second switching circuit 21 'receives and transmits the signal transmitted from the third input circuit 30' to the eighth node N8 under the control of the first clock signal.

At this time, the third input circuit 20 'is also electrically connected to the tenth node N10, and is electrically connected to the eighth node N8 through the second switching circuit 21'.

In some examples, as shown in fig. 20, the seventh control circuit 80' includes: a twenty-third transistor T23 and a twenty-fourth transistor T24.

A gate of the twenty-third transistor T23 is electrically connected to the fifth node N5, a first pole of the twenty-third transistor T23 is electrically connected to the second voltage signal terminal VGL, and a second pole of the twenty-third transistor T23 is electrically connected to the first pole of the twenty-fourth transistor T24.

For example, in case that the level of the fifth node N5 is a high level, the twenty-third transistor T23 is turned on under the control of the fifth node N5, and receives and transmits the second voltage signal to the first pole of the twenty-fourth transistor T24.

A gate of the twenty-fourth transistor T24 is electrically connected to the second clock signal terminal CKB, and a second pole of the twenty-fourth transistor T24 is electrically connected to the eighth node N8.

For example, in case that the level of the second clock signal is a high level, the twenty-fourth transistor T24 is turned on under the control of the second clock signal, and receives and transmits the second voltage signal received at the first pole of the twenty-fourth transistor T24 to the eighth node electrode N8.

In some examples, as shown in fig. 20, the eighth control circuit 90' includes: a twenty-fifth transistor T25.

A gate of the twenty-fifth transistor T25 is electrically connected to the eighth node N8, a first pole of the twenty-fifth transistor T25 is electrically connected to the second voltage signal terminal VGL, and a second pole of the twenty-fifth transistor T25 is electrically connected to the fifth node N5.

For example, in case that the level of the eighth node N8 is a high level, the twenty-fifth transistor T25 is turned on under the control of the eighth node N8, and receives and transmits the second voltage signal to the fifth node N5.

In some examples, as shown in fig. 20, the second switching circuit 21' includes: a twenty-seventh transistor T27.

A gate of the twenty-seventh transistor T27 is electrically connected to the first clock signal terminal CKA, a first pole of the twenty-seventh transistor T27 is electrically connected to the tenth node N10, and a second pole of the twenty-seventh transistor T27 is electrically connected to the eighth node N8.

For example, in the case where the level of the first clock signal is a high level, the twenty-seventh transistor T27 is turned on under the control of the first clock signal, and receives and transmits the signal at the tenth node N10 to the eighth node N8.

At this time, in the case where the third input circuit 20' includes the seventeenth transistor T17 and the eighteenth transistor T18, the second pole of the seventeenth transistor T17 is electrically connected to the tenth node N10 and to the eighth node N8 through the twenty seventh transistor T27, and the second pole of the eighteenth transistor T18 is electrically connected to the tenth node N10 and to the eighth node N8 through the twenty seventh transistor T27.

In some examples, as shown in fig. 21, the shift register 100 further includes: the first anticreeping circuit 110.

The first leakage prevention circuit 110 is electrically connected to the first node N1, one of the output signal terminals OUT < N >, the first voltage signal terminal VGH, and the first leakage prevention node OFF 1. The first leakage prevention circuit 110 is configured to transmit a first voltage signal to the first leakage prevention node OFF1 under the control of the voltage of the first node N1 or an output signal transmitted from the output signal terminal OUT < N >.

For example, in the case where the level of the first node N1 or the output signal is high, the first anticreeping circuit 110 receives and transmits the first voltage signal to the first anticreeping node OFF1 under the control of the first node N1 or the output signal.

Based on this, as shown in fig. 21, the first control circuit 30 is also electrically connected to the first leakage prevention node OFF 1. Thus, in the case where the voltage of the first node N1 or the output signal is at a high level, the first leakage prevention circuit 110 may transmit the first voltage signal to the first leakage prevention node OFF1, so that the voltage of the first leakage prevention node OFF1 increases, the voltage difference between the first leakage prevention node OFF1 and the first node N1 is reduced, and the first node N1 is prevented from being leaked through the first control circuit 30.

As shown in fig. 21, the second output circuit 50 is also electrically connected to the first leakage prevention node OFF 1. Thus, in the case where the voltage of the first node N1 or the output signal is at a high level, the first leakage prevention circuit 110 can transmit the first voltage signal to the first leakage prevention node OFF1, so that the voltage of the first leakage prevention node OFF1 rises, the voltage difference between the first leakage prevention node OFF1 and the output signal terminal OUT < N > is reduced, and the output signal terminal OUT < N > is prevented from leaking through the second output circuit 50.

As shown in fig. 23, in the case where the shift register 100 further includes the sixth control circuit 30 ', the sixth control circuit 30' is also electrically connected to the first leakage-preventing node. Thus, in the case where the voltage of the first node N1 or the output signal is at a high level, the first leakage prevention circuit 110 can transmit the first voltage signal to the first leakage prevention node OFF1, so that the voltage of the first leakage prevention node OFF1 rises, the voltage difference between the first leakage prevention node OFF1 and the first node N1 is reduced, and the output signal terminal OUT < N > is prevented from leaking through the sixth control circuit 30'.

In some examples, as shown in fig. 22, the first leakage prevention circuit 110 includes: a twenty-sixth transistor T26.

A gate of the twenty-sixth transistor T26 is electrically connected to the first node N1 or the first output signal terminal OUT < N >, a first pole of the twenty-sixth transistor T26 is electrically connected to the first voltage signal terminal VGH, and a second pole of the twenty-sixth transistor T26 is electrically connected to the first leakage-preventing node OFF 1.

For example, in case that the level of the first node N1 or the output signal is a high level, the twenty-sixth transistor T26 is turned on under the control of the first node N1 or the output signal, and receives and transmits the first voltage signal to the first leakage preventing node OFF 1.

In some examples, as shown in fig. 22, in a case where the first control circuit 30 is also electrically connected to the first leakage prevention node OFF1, the eighth transistor T8 includes: a first sub-transistor T8a and a second sub-transistor T8 b.

The gate of the first sub-transistor T8a is electrically connected to the second node N2, the first pole of the first sub-transistor T8a is electrically connected to the second voltage signal terminal VGL, and the second pole of the first sub-transistor T8a is electrically connected to the first anti-leakage node OFF 1. The gate of the second sub-transistor T8b is electrically connected to the second node N2, the first pole of the second sub-transistor T8b is electrically connected to the first anti-leakage node OFF1, and the second pole of the second sub-transistor T8b is electrically connected to the first node N1.

For example, in a case where the level of the second node N2 is a high level, the first sub transistor T8a and the second sub transistor T8b may be turned on at the same time under the control of the second node N2, the first sub transistor T8a may receive and transmit the second voltage signal to the first leakage prevention node OFF1, and the second sub transistor T8b may transmit the second voltage signal from the first leakage prevention node OFF1 to the first node N1, and pull down the voltage of the first node N1 to a low level.

Here, in the case where the voltage of the first node N1 is at a high level and the first control circuit 30 is in an active state, the first leakage prevention circuit 110 may transmit a first voltage signal to the first leakage prevention node OFF1, reduce the voltage difference between the first leakage prevention node OFF1 and the first node N1, and make the voltage difference between the gate and the second pole of the first sub-transistor T8a less than zero, ensuring that the first sub-transistor T8a is completely or more completely turned OFF. This prevents the first node N1 from leaking through the first control circuit 30, so that the first node N1 can be maintained at a higher and more stable voltage.

In some examples, as shown in fig. 22, in a case where the second output circuit 50 is also electrically connected to the first leakage prevention node OFF1, the tenth transistor T10 includes: a third sub-transistor T10a and a fourth sub-transistor T10 b.

The gate of the third sub-transistor T10a is electrically connected to the second node N2, the first pole of the third sub-transistor T10a is electrically connected to the second voltage signal terminal VGL, and the second pole of the third sub-transistor T10a is electrically connected to the first leakage-preventing node OFF 1. The gate of the fourth sub-transistor T10b is electrically connected to the second node N2, the first pole of the fourth sub-transistor T10b is electrically connected to the first anti-leakage node OFF1, and the second pole of the fourth sub-transistor T10b is electrically connected to the output signal terminal OUT < N >.

For example, in a case where the level of the second node N2 is a high level, the third sub-transistor T10a and the fourth sub-transistor T10b may be simultaneously turned on under the control of the second node N2, the third sub-transistor T10a may receive and transmit the second voltage signal to the first leakage-preventing node OFF1, and the fourth sub-transistor T10b may transmit the second voltage signal from the first leakage-preventing node OFF1 to the output signal terminal OUT < N >, and pull down the voltage of the output signal terminal OUT < N > to a low level.

Here, in the case where the voltage of the first node N1 is at a high level and the second output circuit 50 is in a state of being operated, the first leakage prevention circuit 110 may transmit the first voltage signal to the first leakage prevention node OFF1, reduce the voltage difference between the first leakage prevention node OFF1 and the output signal terminal OUT < N >, and make the voltage difference between the gate and the second pole of the third sub-transistor T10a less than zero, ensuring that the third sub-transistor T10a is completely or more completely turned OFF. This prevents the output signal terminal OUT < N > from leaking through the second output circuit 50, so that the output signal terminal OUT < N > can be maintained at a higher and more stable voltage.

In some examples, as shown in fig. 24, in the case where the sixth control circuit 30' includes the nineteenth transistor T19, the nineteenth transistor T19 includes: a fifth sub-transistor T19a and a sixth sub-transistor T19 b.

A gate of the fifth sub-transistor T19a is electrically connected to the eighth node N8, a first pole of the fifth sub-transistor T19a is electrically connected to the second voltage signal terminal VGL, and a second pole of the fifth sub-transistor T19a is electrically connected to the first leakage-preventing node OFF 1; the gate of the sixth sub-transistor T19b is electrically connected to the eighth node N8, the first pole of the sixth sub-transistor T19b is electrically connected to the first anti-leakage node OFF1, and the second pole of the sixth sub-transistor T19b is electrically connected to the first node N1.

For example, in a case where the level of the eighth node N8 is a high level, the fifth sub transistor T19a and the sixth sub transistor T19b may be simultaneously turned on under the control of the eighth node N8, the fifth sub transistor T19a may receive and transmit the second voltage signal to the first leakage prevention node OFF1, and the sixth sub transistor T19b may transmit the second voltage signal from the first leakage prevention node OFF1 to the first node N1, and pull down the voltage of the first node N1 to a low level.

Here, in the case where the voltage of the first node N1 is at a high level and the sixth control circuit 30' is in a state of being operated, the first leakage prevention circuit 110 may transmit the first voltage signal to the first leakage prevention node OFF1, reduce the voltage difference between the first leakage prevention node OFF1 and the first node N1, and make the voltage difference between the gate and the second pole of the fifth sub-transistor T19a less than zero, ensuring that the fifth sub-transistor T19a is completely or more completely turned OFF. This prevents the first node N1 from leaking through the sixth control circuit 30', so that the first node N1 can be maintained at a higher, more stable voltage.

In some examples, as shown in fig. 23, in the case where the second output circuit 50 further includes a twentieth transistor T20, the twentieth transistor T20 includes: a seventh sub-transistor T20a and an eighth sub-transistor T20 b.

The gate of the seventh sub-transistor T20a is electrically connected to the eighth node N8, the first pole of the seventh sub-transistor T20a is electrically connected to the second voltage signal terminal VGL, and the second pole of the seventh sub-transistor T20a is electrically connected to the first leakage-preventing node OFF 1. The gate of the eighth sub-transistor T20b is electrically connected to the eighth node N8, the first pole of the eighth sub-transistor T20b is electrically connected to the first anti-leakage node OFF1, and the second pole of the eighth sub-transistor T20b is electrically connected to the output signal terminal OUT < N >.

For example, in case that the level of the eighth node N8 is a high level, the seventh sub-transistor T20a and the eighth sub-transistor T20b may be simultaneously turned on under the control of the eighth node N8, the seventh sub-transistor T20a may receive and transmit the second voltage signal to the first leakage-preventing node OFF1, and the eighth sub-transistor T20b may transmit the second voltage signal from the first leakage-preventing node OFF1 to the output signal terminal OUT < N >, and pull down the voltage of the output signal terminal OUT < N > to a low level.

Here, in the case where the voltage of the first node N1 is at a high level and the second output circuit 50 is in a state of being operated, the first leakage prevention circuit 110 may transmit the first voltage signal to the first leakage prevention node OFF1, reduce the voltage difference between the first leakage prevention node OFF1 and the output signal terminal OUT < N >, and make the voltage difference between the gate and the second pole of the seventh sub-transistor T20a less than zero, ensuring that the seventh sub-transistor T20a is completely or more completely turned OFF. This prevents the output signal terminal OUT < N > from leaking through the second output circuit 50, so that the output signal terminal OUT < N > can be maintained at a higher and more stable voltage.

In some examples, as shown in fig. 24, in the case where the shift register 100 further includes the third control circuit 70, the third control circuit 70 is also electrically connected to the first leakage prevention node OFF 1.

For example, in the case where the third control circuit 70 includes the eleventh transistor T11 and the twelfth transistor T12, the eleventh transistor T11 includes: a ninth sub-transistor T11a and a tenth sub-transistor T11 b; and/or, the twelfth transistor T12 includes: an eleventh sub-transistor T12a and a twelfth sub-transistor T12 b.

Illustratively, the gate of the ninth sub-transistor T11a is electrically connected to the fifth node N5, the first pole of the ninth sub-transistor T11a is electrically connected to the second clock signal terminal CKB, and the second pole of the ninth sub-transistor T11a is electrically connected to the first leakage-preventing node OFF 1. A gate of the tenth sub-transistor T11b is electrically connected to the fifth node N5, a first pole of the tenth sub-transistor T11b is electrically connected to the first anti-leakage node OFF1, and a second pole of the tenth sub-transistor T11b is electrically connected to the sixth node N6.

For example, in case that the level of the fifth node N5 is a high level, the ninth sub transistor T11a and the tenth sub transistor T11b may be simultaneously turned on under the control of the fifth node N5, the ninth sub transistor T11a may receive and transmit the second clock signal to the first leakage prevention node OFF1, and the tenth sub transistor T11b may transmit the second clock signal from the first leakage prevention node OFF1 to the sixth node N6.

The beneficial effects of the first anti-leakage node OFF1 are the same as those of the first anti-leakage node OFF1 in some embodiments, and are not further described herein.

Illustratively, the gate of the eleventh sub-transistor T12a is electrically connected to the second clock signal terminal CKB, the first pole of the eleventh sub-transistor T12a is electrically connected to the sixth node N6, and the second pole of the eleventh sub-transistor T12a is electrically connected to the first leakage-preventing node OFF 1. The gate of the twelfth sub-transistor T12b is electrically connected to the second clock signal terminal CKB, the first pole of the twelfth sub-transistor T12b is electrically connected to the first anti-leakage node OFF1, and the second pole of the twelfth sub-transistor T12b is electrically connected to the first node N1.

For example, in case that the level of the second clock signal is a high level, the eleventh sub-transistor T12a and the twelfth sub-transistor T12b may be simultaneously turned on under the control of the second clock signal, the eleventh sub-transistor T12a may receive and transmit the second clock signal at the sixth node N6 to the first leakage prevention node OFF1, and the twelfth sub-transistor T12b may transmit the second clock signal from the first leakage prevention node OFF1 to the first node N1.

The present disclosure has various setting modes for preventing the leakage of the fifth control circuit 90, and the setting can be selected according to actual needs.

In one example, as shown in fig. 24, in the case where the shift register 100 further includes the fifth control circuit 90, the fifth control circuit 90 is also electrically connected to the first leakage preventing node OFF 1. In the case where the shift register 100 further includes the eighth control circuit 90 ', the eighth control circuit 90' is further electrically connected to the first leakage preventing node OFF 1;

in another example, as shown in fig. 25, the shift register 100 further includes: and a second leakage preventing circuit 120. The second leakage preventing circuit 120 is electrically connected to the fifth node N5, the first voltage signal terminal VGH, and the second leakage preventing node OFF 2; the second leakage preventing circuit 120 is configured to transmit the first voltage signal to the second leakage preventing node OFF2 under the control of the voltage of the fifth node N5.

For example, in a case where the voltage of the fifth node N5 is at a high level, the second leakage preventing circuit 120 may receive and transmit the first voltage signal to the second leakage preventing node OFF2 under the control of the fifth node N5.

Illustratively, in the case where the shift register 100 further includes the fifth control circuit 90, the fifth control circuit 90 is further electrically connected to the second leakage preventing node OFF 2. In the case where the shift register 100 further includes the eighth control circuit 90 ', the eighth control circuit 90' is also electrically connected to the second leakage preventing node OFF 2.

In some examples, as shown in fig. 24, in a case where the fifth control circuit 90 is also electrically connected to the first leakage prevention node OFF1, the fifteenth transistor T15 includes: a thirteenth sub-transistor T15a and a fourteenth sub-transistor T15 b.

The gate of the thirteenth sub-transistor T15a is electrically connected to the second node N2, the first pole of the thirteenth sub-transistor T15a is electrically connected to the second voltage signal terminal VGL, and the second pole of the thirteenth sub-transistor T15a is electrically connected to the first leakage-preventing node OFF 1. A gate of the fourteenth sub transistor T15b is electrically connected to the second node N2, a first pole of the fourteenth sub transistor T15b is electrically connected to the first anti-leakage node OFF1, and a second pole of the fourteenth sub transistor T15b is electrically connected to the fifth node N5.

For example, in a case where the level of the second node N2 is a high level, the thirteenth sub transistor T15a and the fourteenth sub transistor T15b may be simultaneously turned on under the control of the second node N2, the thirteenth sub transistor T15a may receive and transmit the second voltage signal to the first leakage prevention node OFF1, and the fourteenth sub transistor T15b may transmit the second voltage signal from the first leakage prevention node OFF1 to the fifth node N5.

In some examples, as shown in fig. 24, in a case where the eighth control circuit 90' is also electrically connected to the first leakage prevention node OFF1, the twenty-fifth transistor T25 includes: a fifteenth sub-transistor T25a and a sixteenth sub-transistor T25 b.

The gate of the fifteenth sub-transistor T25a is electrically connected to the eighth node N8, the first pole of the fifteenth sub-transistor T25a is electrically connected to the second voltage signal terminal VGL, and the second pole of the fifteenth sub-transistor T25a is electrically connected to the first anti-leakage node OFF 1. A gate of the sixteenth sub-transistor T25b is electrically connected to the eighth node N8, a first pole of the sixteenth sub-transistor T25b is electrically connected to the first anti-leakage node OFF1, and a second pole of the sixteenth sub-transistor T25b is electrically connected to the fifth node N5.

For example, in a case where the level of the eighth node N8 is a high level, the fifteenth sub transistor T25a and the sixteenth sub transistor T25b may be simultaneously turned on under the control of the eighth node N8, the fifteenth sub transistor T25a may receive and transmit the second voltage signal to the first leakage-preventing node OFF1, and the sixteenth sub transistor T25b may transmit the second voltage signal from the first leakage-preventing node OFF1 to the fifth node N5.

In some examples, as shown in fig. 25, in a case where the fifth control circuit 90 is also electrically connected to the second leakage preventing node OFF2, the fifteenth transistor T15 includes: a seventeenth sub-transistor T15c and an eighteenth sub-transistor T15 d.

The gate of the seventeenth sub-transistor T15c is electrically connected to the second node N2, the first pole of the seventeenth sub-transistor T15c is electrically connected to the second voltage signal terminal VGL, and the second pole of the seventeenth sub-transistor T15c is electrically connected to the second anti-leakage node OFF 2. The gate of the eighteenth sub-transistor T15d is electrically connected to the second node N2, the first pole of the eighteenth sub-transistor T15d is electrically connected to the second anti-leakage node OFF2, and the second pole of the eighteenth sub-transistor T15d is electrically connected to the fifth node N5.

For example, in case that the level of the second node N2 is a high level, the seventeenth sub-transistor T15c and the eighteenth sub-transistor T15d may be simultaneously turned on under the control of the second node N2, the seventeenth sub-transistor T15c may receive and transmit the second voltage signal to the second leakage-preventing node OFF2, and the eighteenth sub-transistor T15d may transmit the second voltage signal from the second leakage-preventing node OFF2 to the fifth node N5.

The advantages of the second anti-leakage node OFF2 are the same as those of the first anti-leakage node OFF1 in some embodiments, and are not further described herein.

In some examples, as shown in fig. 25, in a case where the eighth control circuit 90' is also electrically connected to the second leakage-preventing node OFF2, the twenty-fifth transistor T25 includes: a nineteenth sub-transistor T25c and a twentieth sub-transistor T25 d.

The gate of the nineteenth sub-transistor T25c is electrically connected to the eighth node N8, the first pole of the nineteenth sub-transistor T25c is electrically connected to the second voltage signal terminal VGL, and the second pole of the nineteenth sub-transistor T25c is electrically connected to the second leakage-preventing node OFF 2. The gate of the twentieth sub-transistor T25d is electrically connected to the eighth node N8, the first pole of the twentieth sub-transistor T25d is electrically connected to the second leakage-preventing node OFF2, and the second pole of the twentieth sub-transistor T25d is electrically connected to the fifth node N5.

For example, in a case where the level of the eighth node N8 is a high level, the nineteenth sub-transistor T25c and the twentieth sub-transistor T25d may be simultaneously turned on under the control of the eighth node N8, the nineteenth sub-transistor T25c may receive and transmit the second voltage signal to the second leakage prevention node OFF2, and the twentieth sub-transistor T25d may transmit the second voltage signal from the second leakage prevention node OFF2 to the fifth node N5.

Some embodiments of the present disclosure provide a scan driving circuit 400 including a plurality of shift registers 100. The cascade relationship of the plurality of shift registers 100 includes a plurality of types, and the arrangement can be selected according to actual needs.

As shown in fig. 26 and 28, among the plurality of shift registers 100, except for the last shift register 100, the output signal terminal OUT < N > of the nth shift register 100 is electrically connected to the (N + 1) th shift register 100. Wherein N is a positive integer. That is, the output signal output from the nth shift register 100 can be used as the input signal of the (N + 1) th shift register 100.

In fig. 26 and 28, OUT <1>, OUT <2>, OUT <3>, OUT <4>, OUT < N-1>, and OUT < N > respectively represent an output signal terminal of the first shift register 100, an output signal terminal of the second shift register 100, an output signal terminal of the third shift register 100, an output signal terminal of the fourth shift register 100, an output signal terminal of the N-1 th shift register 100, and an output signal terminal of the N-th shift register 100 in the scan driving circuit 400.

Illustratively, as shown in fig. 26 and 28, the scan driving circuit 400 includes a first clock signal line CLA and a second clock signal line CLB.

The present disclosure may have various setting modes for the connection relationship between the shift register 100 and the two clock signal lines, and the setting may be selected according to the structure of the shift register 100.

In some examples, in the case where the first signal terminal S1 is the first cascade signal terminal OUT < N-1> and the fourth signal terminal S4 is the first node N1, as shown in fig. 26, the first clock signal line CLA may be electrically connected to the first clock signal terminal CKA of the 2N-1 th shift register 100, and the second clock signal line CLB may be electrically connected to the first clock signal terminal CKA of the 2N shift register 100.

In other examples, in the case that the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1>, as shown in fig. 28, each shift register 100 is electrically connected to both a first clock signal line CLA and a second clock signal line CLB, wherein the first clock signal line CLA is electrically connected to the first clock signal terminal CKA of the 2N-1 th shift register 100, the first clock signal line CLA is electrically connected to the second clock signal terminal CKB of the 2N shift register 100, the second clock signal line CLB is electrically connected to the second clock signal terminal CKB of the 2N-1 th shift register 100, and the second clock signal line CLB is electrically connected to the first clock signal terminal CKA of the 2N shift register 100.

Illustratively, as shown in fig. 26 and 28, the scan driving circuit 400 may further include: the start signal line STL.

For example, the first shift register in the scan driving circuit 400 is electrically connected to the start signal line STL to take the start signal transmitted by the start signal line STL as an input signal.

The shift register 100 included in the scan driving circuit 400 has the same structure and beneficial technical effects as the shift register 100 provided in some embodiments, and is not described herein again.

The operation of the shift register 100 will be described in more detail below according to different structures of the shift register 100.

In some examples, the first signal terminal S1 is the first cascade signal terminal OUT < N-1>, and the fourth signal terminal S4 is the first node N1. The operation of the shift register 100 will be schematically described with reference to the structure shown in fig. 6 and the timing diagram shown in fig. 27, and taking the second signal terminal S2 as the first clock signal terminal CKA and the third signal terminal S3 as the first voltage signal terminal VGH as an example.

In fig. 27, OUT < N-1> represents a signal output from the output signal terminal of the N-1 th shift register 100, OUT < N > represents a signal output from the output signal terminal of the N-th shift register 100, and OUT < N +1> represents a signal output from the output signal terminal of the N +1 th shift register 100.

As shown in fig. 27, the operation of the shift register 100 includes: a first stage C, a second stage D, a third stage E and a fourth stage F.

In the first phase C, the level of the first clock signal transmitted by the first clock signal line CLA is divided into two phases, i.e., a high level phase and a low level phase.

When the first clock signal is in the high level phase, the first cascade signal is in the low level phase, and at this time, in response to the first clock signal, the first transistor T1 is turned on, transmits the first cascade signal of the low level to the first node N1, and charges the first capacitor C1. At this time, the ninth transistor T9 is turned off under the control of the voltage of the first node N1.

In response to the first clock signal, the second transistor T2 is turned on, transmits the first voltage signal received at the first voltage signal terminal VGH to the second node N2, and charges the second capacitor C2. The tenth transistor T10 is turned on under the control of the voltage of the second node N2, transmitting the second voltage signal received at the second voltage signal terminal VGL to the output signal terminal OUT < N >.

When the first clock signal is in a low level stage, both the first transistor T1 and the second transistor T2 are turned off in response to the first clock signal, the first capacitor C1 starts discharging, so that the voltage of the first node N1 is maintained at a low level, and thus the third transistor T3 is turned off under the control of the first node N1. At this time, the second capacitor C2 starts to discharge, so that the voltage of the second node N2 is maintained at a high level, the tenth transistor T10 maintains a turn-on state under the control of the voltage of the second node N2, and transmits the second voltage signal to the output signal terminal OUT < N >.

Therefore, in the first phase C, the voltage of the first node N1 is always maintained in a low state, so that the ninth transistor T9 is always in an off state; the voltage at the second node N2 is always maintained at a high level, so that the tenth transistor T10 is always turned on, and the output signal terminal OUT < N > continuously outputs the low level second voltage signal.

It should be noted that, since the voltage at the second node N2 is kept at the high level state in the first stage C, the eighth transistor T8 is always kept at the conducting state in response to the high level signal at the second node N2, and transmits the second voltage signal to the first node N1, so as to further ensure that the voltage at the first node N1 is at the low level state.

In the second phase D, the level of the first clock signal is divided into two phases, i.e., a high level phase and a low level phase. The level of the first cascade signal is high.

When the first clock signal is in a high level stage, the first transistor T1 is turned on in response to the first clock signal, transmits the first cascade signal to the first node N1, and charges the first capacitor C1; under the control of the voltage of the first node N1, the ninth transistor T9 is turned on, transmitting the first voltage signal to the output signal terminal OUT < N >.

In response to the first clock signal, the second transistor T2 is turned on, and at the same time, the third transistor T3 is turned on under the control of the voltage of the first node N1. Since the width-to-length ratio of the second transistor T2 is smaller than that of the third transistor T3, the voltage of the second node N2 is controlled by the second voltage signal transmitted by the third transistor T3, so that the voltage of the second node N2 is at a low level, and the tenth transistor T10 is turned off under the control of the voltage of the second node N2.

When the first clock signal is in a low level stage, both the first transistor T1 and the second transistor T2 are turned off in response to the first clock signal, and at this time, the first capacitor C1 starts to discharge, maintaining the first node N1 in a high level state. On the one hand, the third transistor T3 is kept in a turned-on state under the control of the voltage of the first node N1, and the second voltage signal is continuously transmitted to the second node N2, so that the second node N2 is continuously in a low level state, thereby ensuring that the tenth transistor T10 is continuously in a turned-off state; on the other hand, the ninth transistor T9 maintains a turn-on state under the control of the voltage of the first node N1, and continues to transmit the first voltage signal to the output signal terminal OUT < N >.

Therefore, in the second stage D, the level of the first node N1 is always maintained in a high state, so that the ninth transistor T9 is always in a conducting state, the level of the second node N2 is always maintained in a low state, so that the tenth transistor is always in a closing state, and the output signal terminal OUT < N > outputs the first voltage signal of high level.

In the third stage E, the level of the first clock signal is divided into a plurality of alternating low-level stages and high-level stages.

When the level of the first clock signal is in any high level stage, the level of the first cascade signal is high level. Accordingly, in any high stage of the level of the first clock signal, the operation of each transistor in the shift register 100 may refer to the corresponding operation in the second stage D, and in any low stage of the level of the first clock signal, the operation of each transistor in the shift register 100 may refer to the corresponding operation in the second stage D.

Therefore, in the third phase E, the first node N1 is always in the high state, so that the ninth transistor T9 is always in the on state, the level of the second node N2 is always maintained in the low state, so that the tenth transistor is always in the off state, and the output signal terminal OUT < N > continuously outputs the high-level first voltage signal.

In the fourth phase F, the level of the first cascade signal is a low level, and the level of the first clock signal is divided into two phases, namely a high level phase and a low level phase.

When the level of the first clock signal is high, both the first transistor T1 and the second transistor T2 are turned on in response to the first clock signal, the first transistor T1 transmits the first cascade signal of low level to the first node N1, charges the first capacitor C1, and turns off the ninth transistor T9. The second transistor T2 transmits the first voltage signal to the second node N2 and charges the second capacitor C2. The tenth transistor T10 is turned on under the control of the voltage of the second node N2, transmitting the second voltage signal to the output signal terminal OUT < N >.

When the level of the first clock signal is a low level, both the first transistor T1 and the second transistor T2 are turned off in response to the first clock signal, the first capacitor C1 starts to discharge, the level of the first node N1 is maintained in a low level state, and the ninth transistor T9 is still turned off under the control of the voltage of the first node N1. At this time, the second capacitor C2 starts to discharge, maintaining the second node N2 in a high state, so that the tenth transistor T10 is turned on under the control of the voltage of the second node N2, transmitting the second voltage signal to the output signal terminal OUT < N >.

Therefore, in the fourth phase F, the voltage of the first node N1 is always maintained in the low state, so that the ninth transistor T9 is always in the off state; the voltage at the second node N2 is always maintained at a high level, so that the tenth transistor T10 is always turned on, and the output signal terminal OUT < N > outputs a low level second voltage signal.

Therefore, based on the driving method of the shift register 100 in the present example, the waveform output by the shift register 100 is a waveform in which the high level and the low level are sequentially alternated, that is, the same as the waveform of the enable signal EM required by the pixel driving circuit 300 in the display device 1000 shown in fig. 4. That is, with the shift register 100, the enable signal EM required for the pixel driving circuit 300 in the display device 1000 can be obtained.

In another example, the first signal terminal S1 is the first voltage signal terminal VGH, and the fourth signal terminal S4 is the first cascade signal terminal OUT < N-1 >. With reference to the structure shown in fig. 15 and the timing diagram shown in fig. 29, the operation process of the shift register 100 will be schematically described by taking the second signal terminal S2 as the first clock signal terminal CKA and the third signal terminal S3 as the first voltage signal terminal VGH.

For example, in the structure shown in fig. 15, the first clock signal terminal CKA is electrically connected to the first clock signal line CLA, the second clock signal terminal CKB is electrically connected to the second clock signal line CLB, and the first electrode of the fifteenth transistor T15 is electrically connected to the second voltage signal terminal VGL.

As shown in fig. 29, the operation of the shift register 100 includes: a first stage H, a second stage I, a third stage J and a fourth stage K.

In the first phase H, the level of the first clock signal transmitted by the first clock signal line CLA is divided into two phases, i.e., a high level phase and a low level phase. The level of the first cascade signal is high. The level of the second clock signal transmitted by the second clock signal line CLB is low level.

When the first clock signal is in a high level stage, the first transistor T1 is turned on in response to the first clock signal, transmits the first voltage signal to the fifth node N5, and charges the third capacitor C3. Under the control of the voltage of the fifth node N5, the eleventh transistor T11 is turned on, transmitting the second clock signal to the sixth node N6. Since the twelfth transistor T12 is turned off under the control of the second clock signal, the signal of the sixth node N6 cannot be transmitted to the first node N1. The voltage at the first node N1 is maintained at the voltage of the previous stage, i.e., low level.

In response to the first clock signal, the second transistor T2 is turned on, and at the same time, the third transistor T3 is turned on under the control of the first cascade signal of high level. Since the width-to-length ratio of the second transistor T2 is smaller than that of the third transistor T3, the voltage of the seventh node N7 is controlled by the second voltage signal transmitted by the third transistor T3, so that the voltage of the seventh node N7 is at a low level. The sixteenth transistor T16 is turned on under the control of the first clock signal to transmit the second voltage signal at the seventh node N7 to the second node N2, so that the voltage at the second node N2 is at a low level.

When the first clock signal is at the low level, the second clock signal is still at the low level, so the signal at the sixth node N6 still cannot be transmitted to the first node N1, and the voltage at the first node N1 is maintained at the voltage at the previous stage, i.e., at the low level. The sixteenth transistor T16 is turned off under the control of the first clock signal, and thus the signal at the seventh node N7 cannot be transmitted to the second node N2, and the voltage at the second node N2 is maintained at the voltage of the previous stage, i.e., at the low level.

Therefore, in the first phase H, the voltage of the first node N1 is always maintained in a low state, so that the ninth transistor T9 is always in an off state; the voltage at the second node N2 is always maintained at a low level, so that the tenth transistor T10 is always turned off, and the voltage at the output signal terminal OUT < N > is maintained at the voltage of the previous stage, i.e., at a low level.

In the second phase I, the level of the first clock signal transmitted by the first clock signal line CLA is low. The level of the first cascade signal is high. The level of the second clock signal transmitted by the second clock signal line CLB is divided into two stages, which are a high level stage and a low level stage, respectively.

When the level of the second clock signal is in the high stage, the first transistor T1 is turned off under the control of the first clock signal, and the third capacitor C3 is still in a discharged state, so that the voltage of the fifth node N5 is maintained at a high level. The eleventh transistor T11 is turned on under the control of the voltage of the fifth node N5, transmitting the second clock signal to the sixth node N6. The twelfth transistor T12 is turned on under the control of the second clock signal, transmits the second clock signal at the sixth node N6 to the first node N1, makes the voltage of the first node N1 high, and charges the first capacitor C1.

It should be noted that, when the second clock signal is transmitted to the sixth node N6, the potential of the sixth node N6 is raised, and due to the bootstrap effect of the third capacitor C3, the potential of the fifth node N5 is further raised, so that the eleventh transistor T11 can be turned on more fully.

The sixteenth transistor T16 is turned off by the first clock signal of low level, and thus cannot transmit the signal at the seventh node N7 to the second node N2, while the thirteenth transistor T13 is turned on by the voltage at the fifth node N5, and the fourteenth transistor T14 is turned on by the second clock signal, transmits the second voltage signal of low level to the second node N2, and maintains the voltage at the second node N2 at low level.

When the level of the second clock signal is in the low level stage, the twelfth transistor T12 is turned off under the control of the second clock signal, and the first capacitor C1 starts discharging, so that the voltage of the first node N1 is maintained at a high level.

Since the sixteenth transistor T16 is still turned off by the first clock signal, the voltage at the second node N2 is maintained at the previous stage, i.e., at a low level.

Therefore, in the second phase I, the first node N1 is always in the high state, so that the ninth transistor T9 is always in the on state, the level of the second node N2 is always maintained in the low state, so that the tenth transistor is always in the off state, and the output signal terminal OUT < N > outputs the first voltage signal with the high level.

In the third phase J, the level of the first clock signal is divided into a plurality of alternating high-level phases and low-level phases. The level of the second clock signal is divided into a plurality of alternating low-level phases and high-level phases.

When the level of the second clock signal is in any high level stage, the level of the first clock signal is low level. Accordingly, in any high stage of the level of the second clock signal, the operation of each transistor in the shift register 100 may refer to the corresponding operation in the second stage I, and in any low stage of the level of the second clock signal, the operation of each transistor in the shift register 100 may refer to the corresponding operation in the second stage I.

Therefore, in the third phase J, the first node N1 is always in the high state, so that the ninth transistor T9 is always in the on state, the level of the second node N2 is always maintained in the low state, so that the tenth transistor is always in the off state, and the output signal terminal OUT < N > continuously outputs the high-level first voltage signal.

In the fourth phase K, the level of the first cascade signal is low. The level of the first clock signal is divided into a plurality of alternating high and low phases. The level of the second clock signal is divided into a plurality of alternating low-level phases and high-level phases.

It should be noted that, since the level clock of the first cascade signal maintains the low level state, the third transistor T3 is always kept in the off state under the control of the first cascade signal.

When the level of the first clock signal is in the first high stage, the second transistor T2 and the sixteenth transistor T16 are both turned on under the control of the first clock signal, transmit the first voltage signal of the high level to the second node N2, make the voltage of the second node N2 be the high level, and charge the second capacitor C2. At this time, the fifteenth transistor T15 is turned on under the control of the voltage of the second node N2, transmits a second voltage signal to the fifth node N5 such that the voltage of the fifth node N5 is pulled down to a low level, and the eighteenth transistor T18 is turned on under the control of the voltage of the second node N2, transmits a second voltage signal to the first node N1 such that the voltage of the first node N1 is pulled down to a low level.

When the level of the first clock signal is in the first low stage, the sixteenth transistor T16 is turned off under the control of the first clock signal, the second capacitor C2 starts to discharge, so that the voltage of the second node N2 is still maintained at the high level, and thus the fifteenth transistor T15 is kept in a turned-on state under the control of the voltage of the second node N2, and keeps pulling down the voltage of the fifth node N5 to the low level, and the eighteenth transistor T18 is kept in a turned-on state under the control of the voltage of the second node N2, and keeps pulling down the voltage of the first node N1 to the low level.

Therefore, in the fourth phase K, the voltage of the second node N2 is always maintained at the high level regardless of whether the level of the first clock signal is in the high level phase or the low level phase, so that the voltage of the fifth node N5 and the voltage of the first node N1 are continuously pulled down to the low level.

Therefore, in the fourth phase K, the voltage of the first node N1 is always maintained in a low state, so that the ninth transistor T9 is always in an off state; the voltage at the second node N2 is always maintained at a high level, so that the tenth transistor T10 is always turned on, and the output signal terminal OUT < N > outputs a low level second voltage signal.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A shift register, comprising:

the first input circuit is electrically connected with the first signal end, the first clock signal end and the first node; the first input circuit is configured to transmit a first signal received at the first signal terminal to the first node under control of a first clock signal transmitted by the first clock signal terminal;

the second input circuit is electrically connected with the second signal end, the third signal end, the second voltage signal end, the fourth signal end and the second node; the second input circuit is configured to transmit a third signal received at the third signal terminal to the second node under control of a second signal transmitted by the second signal terminal, and to transmit a second voltage signal received at the second voltage signal terminal to the second node under control of the fourth signal terminal; the second signal terminal and the third signal terminal each include one of a first voltage signal terminal and the first clock signal terminal;

a first control circuit electrically connected to the first node, the second node, and the second voltage signal terminal; the first control circuit is configured to transmit the second voltage signal to the first node under control of a voltage of the second node;

a first output circuit electrically connected to the first node, the first voltage signal terminal, and an output signal terminal; the first output circuit is configured to transmit the first voltage signal to the output signal terminal under control of the voltage of the first node; and the number of the first and second groups,

a second output circuit electrically connected to at least the second node, the second voltage signal terminal, and the output signal terminal; the second output circuit is configured to transmit the second voltage signal to the output signal terminal under control of the voltage of the second node.

2. The shift register according to claim 1, wherein the first input circuit comprises: a first transistor;

the gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the first signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

3. The shift register according to claim 1, wherein the second input circuit comprises: a second transistor and a third transistor;

a gate of the second transistor is electrically connected to the second signal terminal, a first electrode of the second transistor is electrically connected to the third signal terminal, and a second electrode of the second transistor is electrically connected to the second node;

a gate of the third transistor is electrically connected to the fourth signal terminal, a first electrode of the third transistor is electrically connected to the second voltage signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

4. The shift register of claim 3, wherein the second input circuit further comprises: a fourth transistor and a fifth transistor;

a gate of the fourth transistor is electrically connected to the third node, a first electrode of the fourth transistor is electrically connected to the third signal terminal, and a second electrode of the fourth transistor is electrically connected to the second node;

the second pole of the second transistor is also electrically connected with the third node and is electrically connected with the second node through the fourth transistor;

the grid electrode of the fifth transistor is electrically connected with the fourth signal end, the first electrode of the fifth transistor is electrically connected with the second voltage signal end, and the second electrode of the fifth transistor is electrically connected with the third node.

5. The shift register according to any one of claims 1 to 4, wherein the first signal terminal is a first voltage signal terminal, and the fourth signal terminal is a first cascade signal terminal;

or the like, or, alternatively,

the first signal terminal is the first cascade signal terminal, and the fourth signal terminal is the first node.

6. The shift register of claim 5, further comprising a second control circuit;

the second control circuit is electrically connected with the first cascade signal end, the third voltage signal end, the fourth voltage signal end, the second cascade signal end and the fourth node; the second control circuit is configured to transmit a first cascade signal transmitted by the first cascade signal terminal to the fourth node under control of a third voltage signal transmitted by the third voltage signal terminal, or transmit a second cascade signal transmitted by the second cascade signal terminal to the fourth node under control of a fourth voltage signal transmitted by the fourth voltage signal terminal;

wherein the third voltage signal and the fourth voltage signal are inverse signals;

under the condition that the first signal end is a first cascade signal end and the fourth signal end is the first node, the first input circuit is also electrically connected with the fourth node and is electrically connected with the first cascade signal end through the second control circuit;

and under the condition that the first signal end is the first voltage signal end and the fourth signal end is the first cascade signal end, the second input circuit is also electrically connected with the fourth node and is electrically connected with the first cascade signal end through the second control circuit.

7. The shift register according to claim 6, wherein the second control circuit comprises: a sixth transistor and a seventh transistor;

a grid electrode of the sixth transistor is electrically connected with a third voltage signal end, a first electrode of the sixth transistor is electrically connected with the first cascade signal end, and a second electrode of the sixth transistor is electrically connected with the fourth node;

a gate of the seventh transistor is electrically connected to a fourth voltage signal terminal, a first electrode of the seventh transistor is electrically connected to the second cascade signal terminal, and a second electrode of the seventh transistor is electrically connected to the fourth node;

in the case where the first signal terminal is a first cascade signal terminal, the fourth signal terminal is the first node, and the first input circuit includes a first transistor,

the first electrode of the first transistor is also electrically connected with the fourth node and is electrically connected with the first cascade signal end through the sixth transistor;

in a case where the first signal terminal is a first voltage signal terminal, the fourth signal terminal is the first cascade signal terminal, and the second input circuit includes a third transistor,

the gate of the third transistor is also electrically connected to the fourth node and to the first cascade signal terminal via the sixth transistor.

8. The shift register according to claim 1, wherein the first control circuit comprises: an eighth transistor;

a gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the eighth transistor is electrically connected to the first node;

the first output circuit includes: a ninth transistor and a first capacitor;

a gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the ninth transistor is electrically connected to the output signal terminal;

a first pole of the first capacitor is electrically connected to the first node, and a second pole of the first capacitor is electrically connected to the output signal terminal;

the second output circuit includes: a tenth transistor and a second capacitor;

a gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the tenth transistor is electrically connected to the output signal terminal;

a first pole of the second capacitor is electrically connected to the second node, and a second pole of the second capacitor is electrically connected to the second voltage signal terminal;

in a case where the second output circuit is further electrically connected to a second clock signal terminal, the second pole of the second capacitor is electrically connected to the second voltage signal terminal or the second clock signal terminal.

9. The shift register according to claim 5, wherein in a case where the first signal terminal is a first voltage signal terminal and the fourth signal terminal is a first cascade signal terminal, the shift register further comprises: a third control circuit;

the third control circuit is electrically connected with a fifth node, a second clock signal end and the first node; the third control circuit is configured to transmit the second clock signal to the first node under control of a voltage of the fifth node and the second clock signal transmitted by the second clock signal terminal;

wherein the first input circuit is further electrically connected to the fifth node and to the first node through the third control circuit; the first input circuit is configured to transmit the first signal to the fifth node under control of the first clock signal.

10. The shift register according to claim 9, wherein the third control circuit comprises: an eleventh transistor, a twelfth transistor, and a third capacitor;

a gate of the eleventh transistor is electrically connected to the fifth node, a first electrode of the eleventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the eleventh transistor is electrically connected to the sixth node;

a gate of the twelfth transistor is electrically connected to the second clock signal terminal, a first electrode of the twelfth transistor is electrically connected to the sixth node, and a second electrode of the twelfth transistor is electrically connected to the first node;

a first pole of the third capacitor is electrically connected to the fifth node and a second pole of the third capacitor is electrically connected to the sixth node;

in the case where the first input circuit includes a first transistor, a second pole of the first transistor is electrically connected to the fifth node, and is electrically connected to the first node through the eleventh transistor and the twelfth transistor in this order.

11. The shift register of claim 9, further comprising: a fourth control circuit;

the fourth control circuit is electrically connected with the fifth node, the second voltage signal end, the second clock signal end and the second node; the fourth control circuit is configured to transmit the second voltage signal to the second node under control of the voltage of the fifth node and the second clock signal.

12. The shift register according to claim 11, wherein the fourth control circuit comprises: a thirteenth transistor and a fourteenth transistor;

a gate of the thirteenth transistor is electrically connected to the fifth node, a first electrode of the thirteenth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the first electrode of the fourteenth transistor;

a gate of the fourteenth transistor is electrically connected to the second clock signal terminal, and a second pole of the fourteenth transistor is electrically connected to the second node.

13. The shift register of claim 9, further comprising: a fifth control circuit;

the fifth control circuit is electrically connected to the second node, the fifth node, and one of the second voltage signal terminal and the first clock signal terminal; the fifth control circuit is configured to transmit the second voltage signal or the first clock signal to the fifth node under control of the voltage of the second node.

14. The shift register according to claim 13, wherein the fifth control circuit comprises: a fifteenth transistor;

a gate of the fifteenth transistor is electrically connected to the second node, a first pole of the fifteenth transistor is electrically connected to one of the second voltage signal terminal and the first clock signal terminal, and a second pole of the fifteenth transistor is electrically connected to the fifth node.

15. The shift register of claim 9, further comprising: a first switching circuit;

the first switch circuit is electrically connected with the second node, the seventh node and the first clock signal end; the first switching circuit is configured to transmit a signal from the seventh node to the second node under control of the first clock signal;

the second input circuit is also electrically connected to the seventh node and to the second node through the first switch circuit.

16. The shift register according to claim 15, wherein the first switch circuit comprises: a sixteenth transistor;

a gate of the sixteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the sixteenth transistor is electrically connected to the seventh node, and a second electrode of the sixteenth transistor is electrically connected to the second node;

in a case where the second input circuit includes the second transistor and the third transistor, a second pole of the second transistor is electrically connected to the seventh node and to the second node through the sixteenth transistor, and a second pole of the third transistor is electrically connected to the seventh node and to the second node through the sixteenth transistor.

17. The shift register of claim 1, further comprising: a third input circuit and a sixth control circuit;

the third input circuit is electrically connected with the third signal end, the second voltage signal end, the fifth voltage signal end, the fourth signal end and an eighth node; the third input circuit is configured to transmit the third signal to the eighth node under control of a fifth voltage signal transmitted by the fifth voltage signal terminal or to transmit the second voltage signal to the eighth node under control of the second signal; the third signal terminal comprises one of the first voltage signal terminal, the first clock signal terminal, and the fifth voltage signal terminal;

the sixth control circuit is electrically connected with the eighth node, the first node and the second voltage signal terminal; the sixth control circuit is configured to transmit the second voltage signal to the first node under control of the voltage of the eighth node;

the second output circuit is also electrically connected with the eighth node; the second output circuit is further configured to transmit the second voltage signal to the output signal terminal under control of the voltage of the eighth node;

the second signal end further comprises a sixth voltage signal end;

in the case where the second signal terminal is the sixth voltage signal terminal, the second input circuit is further configured to transmit the third signal to the eighth node under control of a sixth voltage signal transmitted by the sixth voltage signal terminal;

the fifth voltage signal and the sixth voltage signal are inverse signals.

18. The shift register of claim 17, wherein the third input circuit comprises: a seventeenth transistor and an eighteenth transistor;

a gate of the seventeenth transistor is electrically connected to the fifth voltage signal terminal, a first electrode of the seventeenth transistor is electrically connected to the third signal terminal, and a second electrode of the seventeenth transistor is electrically connected to the eighth node;

a grid electrode of the eighteenth transistor is electrically connected with the fourth signal end, a first electrode of the eighteenth transistor is electrically connected with the second voltage signal end, and a second electrode of the eighteenth transistor is electrically connected with the eighth node;

the sixth control circuit includes: a nineteenth transistor;

a gate of the nineteenth transistor is electrically connected to the eighth node, a first electrode of the nineteenth transistor is electrically connected to the second voltage signal terminal, and a second electrode of the nineteenth transistor is electrically connected to the first node;

the second output circuit further includes: a twentieth transistor;

the gate of the twentieth transistor is electrically connected to the eighth node, the first electrode of the twentieth transistor is electrically connected to the second voltage signal terminal, and the second electrode of the twentieth transistor is electrically connected to the output signal terminal.

19. The shift register of claim 18, wherein the third input circuit further comprises: a twenty-first transistor and a twenty-second transistor;

a grid electrode of the twenty-first transistor is electrically connected with a ninth node, a first electrode of the twenty-first transistor is electrically connected with the third signal end, and a second electrode of the twenty-first transistor is electrically connected with the eighth node;

a gate of the twenty-second transistor is electrically connected to the fourth signal terminal, a first electrode of the twenty-second transistor is electrically connected to the second voltage signal terminal, and a second electrode of the twenty-second transistor is electrically connected to the ninth node;

wherein a second pole of the seventeenth transistor is further electrically connected to the ninth node and to the eighth node through the twenty-first transistor.

20. The shift register according to claim 17, further comprising at least one of a seventh control circuit, an eighth control circuit, and a second switch circuit;

the seventh control circuit is electrically connected with the fifth node, the second voltage signal end, the second clock signal end and the eighth node; the seventh control circuit is configured to transmit a second voltage signal to the eighth node under control of a voltage of the fifth node and a second clock signal transmitted by the second clock signal terminal;

the eighth control circuit is electrically connected with the eighth node, the fifth node and the second voltage signal terminal; the eighth control circuit is configured to transmit the second voltage signal to the fifth node under control of the voltage of the eighth node;

the second switch circuit is electrically connected with the first clock signal end, the tenth node and the eighth node; the second switching circuit is configured to transmit a signal of the tenth node to the eighth node under control of the first clock signal;

the third input circuit is also electrically connected to the tenth node and to the eighth node through the second switch circuit.

21. The shift register of claim 20,

the seventh control circuit includes: a twenty-third transistor and a twenty-fourth transistor;

a gate of the twenty-third transistor is electrically connected to the fifth node, a first electrode of the twenty-third transistor is electrically connected to the second voltage signal terminal, and a second electrode of the twenty-third transistor is electrically connected to the first electrode of the twenty-fourth transistor;

a gate of the twenty-fourth transistor is electrically connected to the second clock signal terminal, and a second pole of the twenty-fourth transistor is electrically connected to the eighth node;

the eighth control circuit includes: a twenty-fifth transistor;

a gate of the twenty-fifth transistor is electrically connected with the eighth node, a first electrode of the twenty-fifth transistor is electrically connected with the second voltage signal end, and a second electrode of the twenty-fifth transistor is electrically connected with the fifth node;

the second switching circuit includes: a twenty-seventh transistor;

a gate of the twenty-seventh transistor is electrically connected to the first clock signal terminal, a first electrode of the twenty-seventh transistor is electrically connected to the tenth node, and a second electrode of the twenty-seventh transistor is electrically connected to the eighth node;

in a case where the third input circuit includes the seventeenth transistor and the eighteenth transistor, a second pole of the seventeenth transistor is electrically connected to the tenth node and is electrically connected to the eighth node through the twenty seventh transistor, and a second pole of the eighteenth transistor is electrically connected to the tenth node and is electrically connected to the eighth node through the twenty seventh transistor.

22. The shift register according to any one of claims 8 to 17, further comprising: a first anticreeping circuit;

the first anti-creeping circuit is electrically connected with one of the first node and the output signal terminal, the first voltage signal terminal and a first anti-creeping node; the first leakage prevention circuit is configured to transmit the first voltage signal to the first leakage prevention node under control of a voltage of the first node or an output signal transmitted by the output signal terminal;

the first control circuit is also electrically connected with the first anti-creeping node;

the second output circuit is also electrically connected with the first anti-creeping node;

in a case where the shift register further includes the sixth control circuit, the sixth control circuit is further electrically connected to the first leakage-preventing node.

23. The shift register according to claim 22, wherein the first leakage preventing circuit comprises: a twenty-sixth transistor;

a gate of the twenty-sixth transistor is electrically connected to one of the first node and the output signal terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage signal terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the first leakage-preventing node;

the eighth transistor includes: a first sub-transistor and a second sub-transistor;

the grid electrode of the first sub transistor is electrically connected with the second node, the first electrode of the first sub transistor is electrically connected with the second voltage signal end, and the second electrode of the first sub transistor is electrically connected with the first anti-leakage node;

the grid electrode of the second sub-transistor is electrically connected with the second node, the first pole of the second sub-transistor is electrically connected with the first anti-leakage node, and the second pole of the second sub-transistor is electrically connected with the first node;

the tenth transistor includes: a third sub-transistor and a fourth sub-transistor;

the grid electrode of the third sub-transistor is electrically connected with the second node, the first electrode of the third sub-transistor is electrically connected with the second voltage signal end, and the second electrode of the third sub-transistor is electrically connected with the first anti-leakage node;

a gate of the fourth sub-transistor is electrically connected to the second node, a first electrode of the fourth sub-transistor is electrically connected to the first anti-leakage node, and a second electrode of the fourth sub-transistor is electrically connected to the output signal terminal;

in a case where the sixth control circuit includes the nineteenth transistor, the nineteenth transistor includes: a fifth sub-transistor and a sixth sub-transistor;

a gate of the fifth sub-transistor is electrically connected to the eighth node, a first electrode of the fifth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the fifth sub-transistor is electrically connected to the first anti-leakage node;

a gate of the sixth sub-transistor is electrically connected to the eighth node, a first pole of the sixth sub-transistor is electrically connected to the first anti-leakage node, and a second pole of the sixth sub-transistor is electrically connected to the first node;

in a case where the second output circuit further includes a twentieth transistor, the twentieth transistor includes: a seventh sub-transistor and an eighth sub-transistor;

a gate of the seventh sub-transistor is electrically connected to the eighth node, a first electrode of the seventh sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the seventh sub-transistor is electrically connected to the first anti-leakage node;

the gate of the eighth sub-transistor is electrically connected to the eighth node, the first electrode of the eighth sub-transistor is electrically connected to the first anti-leakage node, and the second electrode of the eighth sub-transistor is electrically connected to the output signal terminal.

24. The shift register according to claim 23, wherein in a case where the shift register further comprises the third control circuit, the third control circuit is further electrically connected to the first leakage preventing node.

25. The shift register of claim 23, wherein in a case where the third control circuit includes an eleventh transistor and a twelfth transistor,

the eleventh transistor includes: a ninth sub-transistor and a tenth sub-transistor;

and/or the presence of a gas in the gas,

the twelfth transistor includes: an eleventh sub-transistor and a twelfth sub-transistor;

a gate of the ninth sub-transistor is electrically connected to the fifth node, a first electrode of the ninth sub-transistor is electrically connected to the second clock signal terminal, and a second electrode of the ninth sub-transistor is electrically connected to the first anti-leakage node;

a gate of the tenth sub-transistor is electrically connected to the fifth node, a first pole of the tenth sub-transistor is electrically connected to the first anti-leakage node, and a second pole of the tenth sub-transistor is electrically connected to the sixth node;

a gate of the eleventh sub-transistor is electrically connected to the second clock signal terminal, a first electrode of the eleventh sub-transistor is electrically connected to the sixth node, and a second electrode of the eleventh sub-transistor is electrically connected to the first anti-leakage node;

the grid electrode of the twelfth sub-transistor is electrically connected with the second clock signal end, the first electrode of the twelfth sub-transistor is electrically connected with the first anti-leakage node, and the second electrode of the twelfth sub-transistor is electrically connected with the first node.

26. The shift register according to claim 23, wherein in a case where the shift register further comprises the fifth control circuit,

the fifth control circuit is also electrically connected with the first anti-creeping node; in the case where the shift register further includes the eighth control circuit, the eighth control circuit is further electrically connected to the first leakage-preventing node;

or the like, or, alternatively,

the shift register further includes: a second anticreeping circuit;

the second anti-creeping circuit is electrically connected with the fifth node, the first voltage signal end and a second anti-creeping node; the second leakage prevention circuit is configured to transmit the first voltage signal to the second leakage prevention node under control of a voltage of the fifth node;

the fifth control circuit is also electrically connected with the second anti-creeping node; the eighth control circuit is further electrically connected to the second anti-leakage node.

27. The shift register of claim 26, wherein in a case where the fifth control circuit is further electrically connected to the first leakage-preventing node, the fifteenth transistor includes: a thirteenth sub-transistor and a fourteenth sub-transistor; in a case where the eighth control circuit is further electrically connected to the first leakage-preventing node, the twenty-fifth transistor includes: a fifteenth sub-transistor and a sixteenth sub-transistor;

a gate of the thirteenth sub-transistor is electrically connected to the second node, a first electrode of the thirteenth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the thirteenth sub-transistor is electrically connected to the first anti-leakage node;

a gate of the fourteenth sub-transistor is electrically connected to the second node, a first pole of the fourteenth sub-transistor is electrically connected to the first anti-leakage node, and a second pole of the fourteenth sub-transistor is electrically connected to the fifth node;

a gate of the fifteenth sub-transistor is electrically connected to the eighth node, a first electrode of the fifteenth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the fifteenth sub-transistor is electrically connected to the first anti-leakage node;

a gate of the sixteenth sub-transistor is electrically connected to the eighth node, a first pole of the sixteenth sub-transistor is electrically connected to the first anti-leakage node, and a second pole of the sixteenth sub-transistor is electrically connected to the fifth node;

in a case where the fifth control circuit is further electrically connected to the second leakage-preventing node, the fifteenth transistor includes: a seventeenth sub-transistor and an eighteenth sub-transistor; in a case where the eighth control circuit is further electrically connected to the second leakage-preventing node, the twenty-fifth transistor includes: a nineteenth sub-transistor and a twentieth sub-transistor;

a gate of the seventeenth sub-transistor is electrically connected to the second node, a first electrode of the seventeenth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the seventeenth sub-transistor is electrically connected to the second anti-leakage node;

a gate of the eighteenth sub-transistor is electrically connected to the second node, a first pole of the eighteenth sub-transistor is electrically connected to the second anti-leakage node, and a second pole of the eighteenth sub-transistor is electrically connected to the fifth node;

a gate of the nineteenth sub-transistor is electrically connected to the eighth node, a first electrode of the nineteenth sub-transistor is electrically connected to the second voltage signal terminal, and a second electrode of the nineteenth sub-transistor is electrically connected to the second anti-leakage node;

the gate of the twentieth sub-transistor is electrically connected to the eighth node, the first pole of the twentieth sub-transistor is electrically connected to the second anti-leakage node, and the second pole of the twentieth sub-transistor is electrically connected to the fifth node.

28. A scan driving circuit, comprising: a plurality of shift registers according to any one of claims 1 to 27.

29. A display device, characterized in that the display device comprises: the scan driver circuit and the plurality of pixel driver circuits according to claim 28;

wherein the pixel driving circuit includes: a switching transistor, a sensing transistor, a driving transistor, a control transistor, and a storage capacitor;

and the shift register in the scanning driving circuit is electrically connected with the grid electrode of the control transistor so as to provide an enabling signal.