CN113726313B - Multi-chip system, chip and clock synchronization method - Google Patents
Multi-chip system, chip and clock synchronization method Download PDFInfo
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- CN113726313B CN113726313B CN202010449155.9A CN202010449155A CN113726313B CN 113726313 B CN113726313 B CN 113726313B CN 202010449155 A CN202010449155 A CN 202010449155A CN 113726313 B CN113726313 B CN 113726313B
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- 238000005070 sampling Methods 0.000 claims description 46
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims 2
- 238000001914 filtration Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 8
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 4
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 4
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 4
- 230000001960 triggered effect Effects 0.000 description 4
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 3
- 230000008713 feedback mechanism Effects 0.000 description 2
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
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Abstract
The multi-chip system comprises a first chip and a second chip. The first chip is used for generating a first symbol clock signal according to a first clock signal from the first oscillator. The second chip is used for generating a second symbol clock signal according to a second clock signal from the second oscillator, detecting the difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronizing the first symbol clock signal and the second symbol clock signal according to the error signal.
Description
Technical Field
The present invention relates to a multi-chip system, and more particularly, to a slave chip and clock synchronization method in a multi-chip system.
Background
In a multi-chip system, clocks between multiple chips need to be synchronized with each other to ensure that data and/or instructions can be received correctly. In the current technology, multiple chips share a clock signal generated by the same oscillator. However, as the number of chips in a multi-chip system increases, the difficulty in circuit wiring design increases, resulting in difficulty in implementation.
Disclosure of Invention
In some embodiments, a multi-chip system includes a first chip and a second chip. The first chip is used for generating a first symbol (symbol) clock signal according to a first clock signal from the first oscillator. The second chip is used for generating a second symbol clock signal according to a second clock signal from the second oscillator, detecting the difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronizing the first symbol clock signal and the second symbol clock signal according to the error signal.
In some embodiments, the chip includes synchronization circuitry, sampling clock generation circuitry, and symbol clock generation circuitry. The synchronization circuitry is configured to detect a difference between a first symbol clock signal and a second symbol clock signal to generate an error signal, wherein the first symbol clock signal is generated from a first clock signal of a first oscillator via a master chip. The sampling clock generation circuit is used for generating a sampling clock signal according to a second clock signal from the second oscillator and the error signal. The symbol clock generating circuit is used for generating a second symbol clock signal synchronous with the first symbol clock signal according to the sampling clock signal.
In some embodiments, the clock synchronization method includes the following operations: receiving a first symbol clock signal from a master chip, wherein the master chip is used for generating the first symbol clock signal according to the first clock signal from a first oscillator; generating a second symbol clock signal based on a second clock signal from a second oscillator; and detecting a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, so as to adjust the second symbol clock signal according to the error signal to synchronize the second symbol clock signal with the first symbol clock signal.
The features, operations and effects of the present invention are described in detail below with reference to the accompanying drawings and preferred embodiments.
Drawings
FIG. 1 is a schematic diagram of a multi-chip system according to some embodiments of the invention;
FIG. 2 is a schematic diagram depicting the synchronization circuitry of FIG. 1 according to some embodiments of the invention;
FIG. 3A is a waveform diagram depicting the correlation signals of FIG. 2 according to some embodiments of the invention;
FIG. 3B is a waveform diagram depicting the correlation signals of FIG. 2 according to some embodiments of the invention; and
Fig. 4 is a flow chart depicting a method of clock synchronization in accordance with some embodiments of the present invention. .
Symbol description:
100: multi-chip system
101. 103: Oscillator
110. 120: Chip
112. 122: Phase-locked loop circuit
114. 124: Sampling clock generating circuit
116. 126: Symbol clock generating circuit
128: Synchronous circuit system
CLK1, CLK2: clock signal
F1, f2: frequency of
Serr: error signal
S sy1、Ssy2: system clock signal
S sa1、Ssa2: sampling clock signal
S sb1、Ssb2: symbol clock signal
202: Phase detector circuit
204: Loop filter circuit
S cnt: count value
P1 to P2: positive edge
1-5, -1 To-5: count value
400: Clock synchronization method
S410, S420, S430: operation of
Detailed Description
All terms used herein have their ordinary meaning. The foregoing words are defined in commonly used dictionaries, and any examples of use of words discussed herein are included in the context of this disclosure by way of example only and should not be interpreted in a limiting sense as to the scope and meaning of the present invention. Likewise, the invention is not limited to the various embodiments shown in this specification.
As used herein, "about" or "approximately" generally refers to an error or range of values within about twenty percent, preferably within about ten percent, and more preferably within about five percent. Unless explicitly stated otherwise, all references to values are to be considered as approximations, by the use of the antecedent "about" or "about" indicated error or range.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements may operate or function with each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected in a manner by at least one transistor and/or at least one active and passive component to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the listed associated items. First, second, third, etc. words are used herein to describe and identify various components. Thus, a first component could also be termed a second component herein without departing from the spirit of the present invention. For ease of understanding, like components in the various figures will be designated with identical numerals.
Fig. 1 is a schematic diagram of a multi-chip system 100 according to some embodiments of the invention. In some embodiments, the multi-chip system 100 may be applied to, but not limited to, a digital storage oscilloscope (digital storage oscillator, DSO) or a communication device located in a different room.
Multichip system 100 includes oscillator 101, oscillator 103, chip 110, and chip 120. The oscillator 101 and the oscillator 103 are two different oscillators, which respectively generate a clock signal CLK1 and a clock signal CLK2. In some embodiments, oscillators 101 and 103 may be, but are not limited to, quartz oscillators. In this example, chip 110 operates as a master chip and chip 120 operates as a slave chip. To ensure that data and/or instructions can be properly exchanged, the clock signal of chip 120 (e.g., symbol) clock signal S sb2) is set to be synchronized with the clock signal of chip 110 (e.g., symbol clock signal S sb1). The chip 110 is coupled to the oscillator 101 to receive the clock signal CLK1 and generate the symbol clock signal S sb1 according to the clock signal CLK 1. The chip 120 is coupled to the chip 110 and the oscillator 103 for receiving the symbol clock signal S sb1 and the clock signal CLK2, respectively. The chip 120 generates a symbol clock signal S sb2 according to the clock signal CLK2, and detects a difference between the symbol clock signal S sb2 and the symbol clock signal S sb1 to generate an error signal S err for adjusting the symbol clock signal S sb2 according to the error signal S err. In this way, the symbol clock signal S sb2 can be synchronized with the symbol clock signal S sb1.
The following paragraphs will illustrate various embodiments of the chip 110 and/or the chip 120, but the present invention is not limited to the following embodiments.
As shown in fig. 1, the chip 110 includes a phase-locked loop circuit 112, a sampling clock generation circuit 114, and a symbol clock generation circuit 116. The phase-locked loop circuit 112 generates a system clock signal S sy1 according to the clock signal CLK 1. In some embodiments, the phase-locked loop circuit 112 is based on control of a negative feedback mechanism (not shown) to keep the system clock signal S sy1 synchronized with the clock signal CLK 1. In some embodiments, the pll circuit 112 may include, but is not limited to, a phase detector circuit (not shown), a low pass filter circuit (not shown), a voltage controlled oscillator circuit (not shown), and/or a frequency divider circuit (not shown), wherein these circuits may be configured as the negative feedback mechanism described above.
The sampling clock generating circuit 114 is coupled to the phase-locked loop circuit 112 for receiving the system clock signal S sy1. The sampling clock generation circuit 114 generates a sampling clock signal S sa1 according to the system clock signal S sy1. In some embodiments, the sampling clock generation circuit 114 may include, but is not limited to, a delay circuit (not shown), a multiplexer circuit (not shown), and/or a phase interpolator circuit (not shown). The delay circuit may delay the system clock signal S sy1 to generate a plurality of clock signals having different phases. The multiplexer circuit may select at least two of the plurality of clock signals to generate a plurality of output signals and provide the output signals to the phase interpolator circuit. The phase interpolator circuit may generate the sampling clock signal S sa1 based on a plurality of output signals. The above-mentioned arrangement of the sampling clock generation circuit 114 is used for illustration, but the invention is not limited thereto. In other embodiments, the sampling clock generation circuit 114 may be an all-digital phase-locked loop.
The symbol clock generating circuit 116 is coupled to the sampling clock generating circuit 114 to receive the sampling clock signal S sa1. The symbol clock generating circuit 116 generates a symbol clock signal S sb1 according to the sampling clock signal S sa1. In some embodiments, the sampling clock signal S sa1 is used to set the time interval between multiple data samples (i.e., to set the data sampling rate), and the symbol clock signal S sb1 is used to set the period during which the chip 110 processes a burst of data. In some embodiments, the frequency of the sampling clock signal S sa1 is higher than the frequency of the symbol clock signal S sb1. In some embodiments, the symbol clock generation circuit 116 may be implemented by, but is not limited to, a frequency divider circuit.
The chip 120 includes a phase locked loop circuit 122, a sampling clock generation circuit 124, a symbol clock generation circuit 126, and synchronization circuitry 128. The phase-locked loop circuit 122 generates a system clock signal S sy2 according to the clock signal CLK 2. In some embodiments, the phase-locked loop circuit 122 is configured in a similar manner to the phase-locked loop circuit 112. In some embodiments, the phase-locked loop circuit 122 does not receive the clock signal CLK1 from the oscillator 101.
The sampling clock generating circuit 124 is coupled to the pll circuit 122 for receiving the system clock signal S sy2. The sampling clock generating circuit 124 generates a sampling clock signal S sa2 according to the system clock signal S sy2. In some embodiments, the sampling clock generation circuit 124 is configured in a similar manner to the sampling clock generation circuit 122.
The symbol clock generating circuit 126 is coupled to the sampling clock generating circuit 124 for receiving the sampling clock signal S sa2. The symbol clock generating circuit 126 generates the symbol clock signal S sb2 according to the sampling clock signal S sa2. In some embodiments, the sampling clock signal S sa2 is used to set the time interval between multiple data samples, and the symbol clock signal S sb2 is used to set the period during which the chip 120 processes a piece of data. In some embodiments, the sampling clock signal S sa2 is used to sample data, and the period of one symbol in the sampled recovered data corresponds to the duty cycle of the symbol clock signal S sb2. In some embodiments, as shown in fig. 1, the frequency f 1 of the sampling clock signal S sa2 is higher than the frequency f 2 of the symbol clock signal S sb2. In some embodiments, the frequency f 1 of the sampling clock signal S sa2 may be about 64-8192 times the frequency f 2 of the symbol clock signal S sb2. In some embodiments, the symbol clock generation circuit 126 may be implemented by, but is not limited to, a frequency divider circuit.
The synchronization circuitry 128 is coupled to the chip 110 to receive the symbol clock signal S sb1, to the symbol clock generating circuit 126 to receive the symbol clock signal S sb2, and to the pll circuit 122 to receive the system clock signal S sy2. The synchronization circuitry 128 detects the difference between the symbol clock signal S sb1 and the symbol clock signal S sb2 to generate an error signal S err. For example, the synchronization circuitry 128 counts at least one pulse of the system clock signal S sy2 according to the symbol clock signal S sb1 and the symbol clock signal S sb2 to generate the error signal S err. For example, the synchronization circuitry 128 begins counting the at least one pulse based on one of the symbol clock signal S sb1 and the symbol clock signal S sb2 (e.g., a signal having a leading phase) and stops counting the at least one pulse based on the other of the symbol clock signal S sb1 and the symbol clock signal S sb2. Some embodiments and operations of the synchronization circuitry 128 are described below with reference to fig. 2, 3A, and 3B.
In some embodiments, the sampling clock generating circuit 124 is further configured to adjust the sampling clock signal S sa2 according to the error signal S err. Accordingly, the symbol clock generating circuit 126 can update the symbol clock signal S sb2 according to the adjusted sampling clock signal S sa2. In this way, the symbol clock signal S sb2 can remain synchronous with the symbol clock signal S sb1. For example, the sampling clock generation circuit 124 may include, but is not limited to, a delay circuit (not shown), a multiplexer circuit (not shown), and/or a phase interpolator circuit (not shown). The delay circuit may delay the system clock signal S sy2 to generate a plurality of clock signals having different phases. The multiplexer circuit may select at least two of the plurality of clock signals to generate a plurality of output signals according to the error signal S err and provide the output signals to the phase interpolator circuit. The phase interpolator circuit may generate the sampling clock signal S sa2 based on a plurality of output signals. The above-mentioned arrangement of the sampling clock generating circuit 124 is used for illustration, but the invention is not limited thereto.
It should be understood that the number of chips shown in fig. 1 is for illustration, and the invention is not limited thereto. In one or more embodiments, the number of chips in multi-chip system 100 may be two or more.
In some related art, each chip in a multi-chip system shares the same oscillator to achieve clock synchronization. In these techniques, when the number of chips increases, an additional buffer circuit is added between the oscillator and the chips to improve the driving capability of the oscillator. However, the extra buffer will create difficulties in wiring design of the multi-chip system on the circuit board and will cause a significant increase in overall cost.
In some embodiments of the present invention, different oscillators (e.g., oscillator 101 and oscillator 103) are used for the plurality of chips (e.g., chip 110 and chip 120), and one of the plurality of chips (e.g., chip 120 operating as a slave chip) can perform clock synchronization according to a signal generated by another one of the plurality of chips (e.g., chip 110 operating as a master chip). Thus, the number of buffer circuits can be reduced and the difficulty of wiring design can be reduced.
Fig. 2 is a schematic diagram depicting the synchronization circuitry 128 of fig. 1 in accordance with some embodiments of the invention. The synchronization circuitry 128 includes a phase detector circuit 202 and a loop filter circuit 204. The phase detector circuit 202 counts at least one pulse of the system clock signal S sy2 according to the symbol clock signal S sb1 and the symbol clock signal S sb2 to generate a count value S cnt. The loop filter circuit 204 is coupled to the phase detector circuit 202 to receive the count value S cnt. Loop filter circuit 204 filters count value S cnt to produce error signal S err. In some embodiments, the phase detector circuit 202 may include, but is not limited to, a flip-flop circuit (not shown) and/or a counter circuit (not shown), the operation of which will be described later with reference to fig. 3A and 3B. In some embodiments, loop filter circuit 204 may be a low pass filter circuit.
Fig. 3A is a waveform diagram depicting the correlation signals of fig. 2 according to some embodiments of the invention. In this example, the phase of the symbol clock signal S sb1 leads the phase of the symbol clock signal S sb2. As shown in fig. 3A, the positive edge P1 of the symbol clock signal S sb1 is earlier than the positive edge P2 of the symbol clock signal S sb2. The phase detector circuit 202 is triggered to start counting at least one pulse of the system clock signal S sy2 based on the positive edge P1 of the symbol clock signal S sb1 to generate a count value S cnt, and is triggered to stop counting at least one pulse of the system clock signal S sy2 based on the positive edge P2 of the symbol clock signal S sb2. Thus, the phase detector circuit 202 can detect that the difference between the symbol clock signal S sb1 and the symbol clock signal S sb2 corresponds to 5 pulses, and output a count value S cnt of 5.
Fig. 3B is a waveform diagram depicting the correlation signals of fig. 2 according to some embodiments of the invention. In this example, the phase of the symbol clock signal S sb1 is later than the phase of the symbol clock signal S sb2. As shown in fig. 3B, the positive edge P2 of the symbol clock signal S sb2 is earlier than the positive edge P1 of the symbol clock signal S sb1. The phase detector circuit 202 is triggered to start counting at least one pulse of the system clock signal S sy2 based on the positive edge P2 of the symbol clock signal S sb2 to generate a count value S cnt, and is triggered to stop counting at least one pulse of the system clock signal S sy2 based on the positive edge P1 of the symbol clock signal S sb1. Thus, the phase detector circuit 202 can detect that the difference between the symbol clock signal S sb1 and the symbol clock signal S sb2 is equivalent to 5 pulses, and output the count value S cnt as-5 (a negative value is used to indicate that the phase of the symbol clock signal S sb1 is behind the phase of the symbol clock signal S sb2).
Fig. 4 is a flow chart depicting a method 400 of clock synchronization according to some embodiments of the invention. In some embodiments, the clock synchronization method 400 may be performed by, but is not limited to, the chip 120 of fig. 1 (operating as a slave chip).
In operation S410, the master chip receives a first symbol clock signal, wherein the master chip generates the first symbol clock signal according to the first clock signal from the first oscillator. In operation S420, a second symbol clock signal is generated according to a second clock signal from a second oscillator. In operation S430, a difference between the second symbol clock signal and the first symbol clock signal is detected to generate an error signal, so that the second symbol clock signal is adjusted according to the error signal to synchronize the second symbol clock signal with the first symbol clock signal.
The above description of the operations of the clock synchronization method 400 may refer to the above embodiments, and thus will not be repeated herein. The above-described operations are merely examples and are not limited to being performed in the order in this example. The various operations under the clock synchronization method 400 may be added, replaced, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the invention. Or one or more operations under clock synchronization method 400 may be performed simultaneously or partially simultaneously.
In summary, through the multi-chip system, the chip and the clock synchronization method according to some embodiments of the present invention, the plurality of chips can utilize different oscillators to perform clock synchronization. Thus, the number of buffer circuits can be reduced and the difficulty of wiring design can be reduced.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art may make modifications and adjustments to the technical features of the present invention according to the descriptions or the implicit descriptions of the present invention, but various changes are possible within the protection scope of the present invention, in other words, the protection scope of the present invention should be considered as the scope defined by the claims of the present application.
Claims (8)
1. A multi-chip system, the multi-chip system comprising:
A first chip for generating a first symbol clock signal from a first oscillator; and
A second chip for generating a second symbol clock signal according to a second clock signal from a second oscillator, detecting a difference between the second symbol clock signal and the first symbol clock signal to generate an error signal, and synchronizing the first symbol clock signal and the second symbol clock signal according to the error signal;
wherein the second chip comprises:
a phase-locked loop circuit for generating a system clock signal based on the second clock signal;
synchronizing circuitry for counting at least one pulse in the system clock signal in accordance with the first and second symbol clock signals to generate the error signal;
The sampling clock generation circuit is used for generating a sampling clock signal according to the system clock signal and the error signal; and
And the symbol clock generating circuit is used for generating the second symbol clock signal synchronous with the first symbol clock signal according to the sampling clock signal.
2. The multi-chip system of claim 1, wherein the synchronization circuitry is further to begin counting the at least one pulse based on one of the first and second symbol clock signals and to stop counting the at least one pulse based on the other of the first and second symbol clock signals.
3. The multi-chip system of claim 1, wherein the synchronization circuitry comprises:
A phase detection circuit for counting the at least one pulse according to the first symbol clock signal and the second symbol clock signal to generate a count value; and
And a loop filter circuit for filtering the count value to generate the error signal.
4. The multi-chip system of claim 1, wherein the frequency of the sampling clock signal is higher than the frequency of the second symbol clock signal.
5. The multi-chip system of claim 1, wherein the first oscillator is different from the second oscillator.
6. A chip, the chip comprising:
synchronization circuitry to detect a difference between a first symbol clock signal and a second symbol clock signal to generate an error signal, wherein the first symbol clock signal is generated via a master chip from a first clock signal of a first oscillator;
A sampling clock generating circuit for generating a sampling clock signal according to a second clock signal from a second oscillator and the error signal; and
A symbol clock generating circuit for generating the second symbol clock signal synchronized with the first symbol clock signal based on the sampling clock signal;
Wherein, the chip still contains:
a phase-locked loop circuit for generating a system clock signal based on the second clock signal,
Wherein the synchronization circuitry is to count at least one pulse in the system clock signal based on the first and second symbol clock signals to generate the error signal.
7. The chip of claim 6, wherein the synchronization circuitry comprises:
A phase detection circuit for counting the at least one pulse according to the first symbol clock signal and the second symbol clock signal to generate a count value; and
And a loop filter circuit for filtering the count value to generate the error signal.
8. A clock synchronization method for a chip according to claim 6, characterized in that the clock synchronization method comprises:
receiving a first symbol clock signal from a master chip, wherein the master chip is configured to generate the first symbol clock signal according to a first clock signal from a first oscillator;
generating a second symbol clock signal based on a second clock signal from a second oscillator; and
A difference between the second symbol clock signal and the first symbol clock signal is detected to generate an error signal, and the second symbol clock signal is adjusted according to the error signal to synchronize the second symbol clock signal with the first symbol clock signal.
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| US8917806B1 (en) * | 2013-10-18 | 2014-12-23 | Richtek Technology Corp | Digital phase-locked loop and phase/frequency detector module thereof |
| KR101807850B1 (en) * | 2016-12-13 | 2017-12-11 | 한림대학교 산학협력단 | Multi-Chip System Clock Signal Distribution Synchronization Technology with In-Phase Clock Lines |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7571359B2 (en) * | 2000-07-31 | 2009-08-04 | Massachusetts Institute Of Technology | Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals |
| JP2004180125A (en) * | 2002-11-28 | 2004-06-24 | Renesas Technology Corp | Semiconductor device |
| US7902928B2 (en) * | 2008-02-08 | 2011-03-08 | Mediatek Inc. | Phase-locked circuit employing capacitance multiplication |
| DE112012006735B4 (en) * | 2012-07-25 | 2019-03-28 | Hytera Communications Corp., Ltd. | Synchronization method and apparatus for transmitting and receiving symbols for fully digital receivers |
| CN103888136B (en) * | 2012-12-20 | 2017-01-25 | 澜起科技（上海）有限公司 | No-crystal clock generation system of broadcast system-on-chip |
| KR20210021018A (en) * | 2018-06-15 | 2021-02-24 | 퀀텀-에스아이 인코포레이티드 | Data acquisition control for advanced analysis instruments with pulsed optical sources |
| CN108540108B (en) * | 2018-06-27 | 2024-02-23 | 宗仁科技(平潭)股份有限公司 | IC built-in oscillator circuit and integrated circuit chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8917806B1 (en) * | 2013-10-18 | 2014-12-23 | Richtek Technology Corp | Digital phase-locked loop and phase/frequency detector module thereof |
| KR101807850B1 (en) * | 2016-12-13 | 2017-12-11 | 한림대학교 산학협력단 | Multi-Chip System Clock Signal Distribution Synchronization Technology with In-Phase Clock Lines |
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