CN113593471B

CN113593471B - Pixel driving circuit, driving method thereof, display panel and display device

Info

Publication number: CN113593471B
Application number: CN202110864788.0A
Authority: CN
Inventors: 付焕章; 杨映帆; 刘宇熙; 张礼厅
Original assignee: BOE Technology Group Co Ltd; Mianyang BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Mianyang BOE Optoelectronics Technology Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2022-12-02
Anticipated expiration: 2041-07-29
Also published as: CN113593471A

Abstract

The embodiment of the invention provides a pixel driving circuit and a driving method thereof, a display panel and a display device, relates to the technical field of display, and aims to solve the problem of black picture brightness of the display device in a high-brightness mode. The pixel driving circuit includes: a drive sub-circuit and a first reset sub-circuit, the drive sub-circuit comprising a control terminal, a first terminal and a second terminal, the drive sub-circuit configured to control a drive current flowing through the first terminal and the second terminal; the first terminal of the driving sub-circuit is coupled to the first power voltage terminal, and the second terminal of the driving sub-circuit is coupled to the first node. The first reset subcircuit is coupled between a first node and a reset voltage terminal and configured to form a first path between the reset voltage terminal and the first node in response to a first control signal in a first reset phase; in the second reset phase, a second path is formed between the reset voltage terminal and the first node in response to a second control signal. Wherein the equivalent resistance of the first path is greater than the equivalent resistance of the second path.

Description

Pixel driving circuit, driving method thereof, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a pixel driving circuit, a driving method thereof, a display panel and a display device.

Background

With the popularization of electronic devices such as smart phones and tablet computers and the continuous development of electronic technologies, the application scenes of the electronic devices gradually tend to be diversified. The display screen in the electronic equipment is used as a bridge for information intercommunication with the user, a specific display mode is provided for different application scenes, and the use experience of the user can be greatly improved. For example, in the outdoors where the sunlight is intense, a High Brightness Mode (HBM for short) of the display screen may provide higher display Brightness than the highest Brightness in the normal Mode, so that the user can easily see the display content on the display screen.

However, in other application scenarios, the display brightness provided by the high-brightness mode of the display screen still cannot meet the use requirement of the user, for example, when the user uses the payment two-dimensional code to perform payment operation, since the display brightness of the image required by the scanning device is higher than the display brightness of the display screen in the high-brightness mode, the image of the payment two-dimensional code displayed in the high-brightness mode cannot be recognized by the scanning device, thereby limiting the application of the electronic device in these scenarios. Then, how to increase the display brightness of the display screen in the high brightness mode becomes a problem to be solved by the designer.

In the related art, the display brightness of the display panel in the high brightness mode is improved by adjusting the power supply voltage for supplying power to the pixel driving circuit in the display panel. Referring to fig. 1, fig. 1 is an equivalent circuit diagram of a pixel driving circuit and a Light Emitting device 20 (i.e., an OLED device) coupled in an Organic Light Emitting Diode (OLED) display panel, and as shown in the figure, two poles of the Light Emitting device 20 are respectively coupled to a first power voltage terminal VDD and a second power voltage terminal VSS, wherein the first power voltage terminal VDD provides a stable voltage, the second power voltage terminal VSS is adjustable in voltage, and the voltage of the second power voltage terminal VSS in a high brightness mode is lower than that in a normal mode. Thus, when the display screen is in the high brightness mode, the driving current flowing through the light emitting device 20 is increased due to the fact that the voltage across the first power voltage terminal VDD and the second power voltage terminal VSS is larger than that in the normal mode, and the light emitting brightness of the light emitting device 20 is further improved. However, as the voltage of the second power supply voltage terminal VSS decreases, the light emitting state of the light emitting device 20 is also affected, for example, when the display panel displays a black screen in a high brightness mode, the cross voltage between the second power supply voltage terminal VSS and the reset signal terminal Vint increases, which increases the leakage current flowing through the transistor T', and under the combined action of the leakage current and the driving current, the light emitting device 20 emits light when it should not emit light, that is, the black screen is bright.

Disclosure of Invention

In order to improve the problem of the brightness of a black picture generated by a display device in a high-brightness mode, the embodiment of the invention adopts the following technical scheme:

in a first aspect, a pixel driving circuit is provided, which includes: a drive sub-circuit and a first reset sub-circuit, the drive sub-circuit comprising a control terminal, a first terminal and a second terminal, the drive sub-circuit configured to control a drive current flowing through the first terminal and the second terminal of the drive sub-circuit; the first terminal of the driving sub-circuit is coupled to a first power voltage terminal, the second terminal of the driving sub-circuit is coupled to a first node, and the first node and the second power voltage terminal are configured to be coupled to two poles of the light emitting device, respectively. The first reset subcircuit is coupled between a first node and a reset voltage end and is configured to form a first path between the reset voltage end and the first node in response to a first control signal in a first reset phase; in the second reset phase, a second path is formed between the reset voltage terminal and the first node in response to the second control signal. Wherein the equivalent resistance of the first path is greater than the equivalent resistance of the second path.

Optionally, the first reset sub-circuit comprises: the first transistor comprises a control electrode coupled with a first control signal end and configured to receive a first control signal, a first electrode coupled with a reset voltage end, and a second electrode coupled with a first node. A control electrode of the second transistor is coupled to the second control signal terminal and configured to receive the second control signal, a first electrode of the second transistor is coupled to the reset voltage terminal, and a second electrode of the second transistor is coupled to the first node. Wherein the width-to-length ratio of the first transistor is smaller than that of the second transistor.

Optionally, the width-to-length ratio of the first transistor ranges from 0.4 to 0.48; and/or the width-to-length ratio of the second transistor ranges from 0.49 to 0.73.

Optionally, the width of the channel of the first transistor is the same as that of the channel of the second transistor, and the length of the channel of the first transistor is greater than that of the channel of the second transistor.

Optionally, the first reset sub-circuit further comprises a third transistor. A control electrode of the third transistor is coupled to the first scan signal terminal and configured to receive a first scan signal, a first electrode of the third transistor is coupled to the second electrode of the first transistor and the second electrode of the second transistor, and a second electrode of the third transistor is coupled to the first node; alternatively, a control electrode of the third transistor is coupled to the first scan signal terminal and configured to receive the first scan signal, a first electrode of the third transistor is coupled to the reset voltage terminal, and a second electrode of the third transistor is coupled to the first electrode of the first transistor and the first electrode of the second transistor.

Optionally, the driving sub-circuit comprises a driving transistor, a control electrode of the driving transistor serves as a control terminal of the driving sub-circuit, a first electrode of the driving transistor serves as a first terminal of the driving sub-circuit, and a second electrode of the driving transistor serves as a second terminal of the driving sub-circuit.

Optionally, the pixel driving circuit further includes at least one of a data writing sub-circuit, a compensation sub-circuit, a first light emission control sub-circuit, a second light emission control sub-circuit, and a second reset sub-circuit. The data writing sub-circuit is coupled with the first end of the driving sub-circuit and the data signal end, and the data writing sub-circuit is configured to respond to the second scanning signal and transmit the data signal provided by the data signal end to the first end of the driving sub-circuit. The compensation sub-circuit is coupled to the first power voltage terminal, the control terminal of the driving sub-circuit, and the second terminal of the driving sub-circuit, and the compensation sub-circuit is configured to respond to the second scan signal and transmit the compensated data signal to the control terminal of the driving sub-circuit in cooperation with the data writing sub-circuit. The first light emission control sub-circuit is coupled to a first power voltage terminal and a first terminal of the driver sub-circuit, and the first light emission control sub-circuit is configured to form a path between the first power voltage terminal and the first terminal of the driver sub-circuit in response to a light emission control signal. The second light emission control sub-circuit is coupled to the second terminal of the driving sub-circuit and the first node, and the second light emission control sub-circuit is configured to form a path between the second terminal of the driving sub-circuit and the first node in response to the light emission control signal. The second reset sub-circuit is coupled to the control terminal of the complementary driving sub-circuit and the reset voltage terminal, and the second reset sub-circuit is configured to form a path between the reset voltage terminal and the control terminal of the driving sub-circuit in response to the first scan signal.

Optionally, the data writing sub-circuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the second scan signal terminal and configured to receive the second scan signal, a first electrode of the fourth transistor is coupled to the data signal terminal, and a second electrode of the fourth transistor is coupled to the first terminal of the driving sub-circuit. The compensation sub-circuit comprises: a fifth transistor and a storage capacitor, wherein a control electrode of the fifth transistor is coupled to the second scan signal terminal and configured to receive the second scan signal, a first electrode of the fifth transistor is coupled to the second terminal of the driving sub-circuit, and a second electrode of the fifth transistor is coupled to the control terminal of the driving sub-circuit; the first plate of the storage capacitor is coupled with the control end of the driving sub-circuit, and the second plate of the storage capacitor is coupled with the first power voltage end. The first light emission control sub-circuit includes a sixth transistor having a gate coupled to the light emission control signal terminal and configured to receive the light emission control signal, a first gate coupled to the first power voltage terminal, and a second gate coupled to the first terminal of the driving sub-circuit. The second emission control sub-circuit includes a seventh transistor having a gate coupled to the emission control signal terminal and configured to receive the emission control signal, a first gate coupled to the second terminal of the driving sub-circuit, and a second gate coupled to the first node. The second reset sub-circuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the first scan signal terminal and configured to receive the first scan signal, a first electrode of the eighth transistor is coupled to the reset voltage terminal, and a second electrode of the eighth transistor is coupled to the control terminal of the driving sub-circuit.

In the embodiment of the present invention, since the equivalent resistance of the first path is larger than that of the second path, the driving current flowing through the first path is smaller than that flowing through the second path. When the voltage of the second power supply voltage end is reduced to improve the light-emitting brightness of the light-emitting device, the anode of the light-emitting device can be reset through the second path in the pixel driving circuit, and the problem of black picture brightness caused by overlarge driving current flowing through the light-emitting device is solved.

In a second aspect, there is provided a display panel comprising: the pixel driving circuit and the plurality of light emitting devices described in any of the above embodiments; wherein one pixel driving circuit is coupled to one light emitting device.

The beneficial effects that can be achieved by the display panel provided by the embodiment of the present invention are the same as those that can be achieved by the pixel driving circuit described in any of the above embodiments, and are not described herein again.

In a third aspect, a display device is provided, which comprises the display panel described in any of the above embodiments.

Optionally, the display device further comprises a control drive circuit. The control driving circuit is configured to provide a first voltage to a second power supply voltage end of the display panel and drive at least one pixel driving circuit in the display panel to enter a first reset phase; the control drive circuit is also configured to provide a second voltage to a second power supply voltage terminal of the display panel and drive at least one pixel drive circuit in the display panel into a second reset phase; wherein the first voltage is less than the second voltage.

The beneficial effects that can be achieved by the display device provided by the embodiment of the present invention are the same as those that can be achieved by the pixel driving circuit described in any of the above embodiments, and are not described herein again.

In a fourth aspect, a driving method of a pixel driving circuit is provided, where the pixel driving circuit is the pixel driving circuit described in any of the above embodiments. The driving method includes:

providing a first voltage to a second power supply voltage terminal coupled to the pixel driving circuit, and forming a first path between a reset voltage terminal and a first node in response to a first control signal during a first reset phase;

providing a second voltage to the second power supply voltage terminal, and forming a second path between the reset voltage terminal and the first node in response to the second control signal during a second reset phase;

the first voltage is less than the second voltage, and the equivalent resistance of the first path is greater than that of the second path.

The advantageous effects that can be achieved by the driving method of the pixel driving circuit provided in the embodiment of the present invention are the same as those that can be achieved by the pixel driving circuit described in any of the above embodiments, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a circuit diagram of a sub-pixel in the related art;

FIG. 2A is a block diagram of a display device according to some embodiments of the present invention;

FIG. 2B is a block diagram of a display panel according to some embodiments of the invention;

fig. 2C is a block diagram of a light emitting device according to some embodiments of the present invention;

FIG. 3 is a circuit diagram of a sub-pixel according to some embodiments of the present invention;

FIG. 4 is a circuit diagram of another sub-pixel provided in some embodiments of the present invention;

FIG. 5A is a circuit diagram of another sub-pixel provided by some embodiments of the present invention;

FIG. 5B is a circuit diagram of another sub-pixel provided by some embodiments of the present invention;

FIG. 6 is a timing diagram of a pixel driving circuit in the sub-pixel shown in FIG. 4;

FIG. 7A is a signal transmission diagram of the pixel driving circuit shown in FIG. 4 at different stages in the high brightness mode;

fig. 7B is a signal transmission diagram of the pixel driving circuit shown in fig. 4 at different stages in the normal mode.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expressions "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "at least one of A, B or C" and includes combinations of the following A, B and C: a alone, B alone, C alone, a combination of A and B, A and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

"plurality" means at least two.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" or "according to" means open and inclusive, as a process, step, calculation, or other action that is "based on" or "according to" one or more stated conditions or values may in practice be based on additional conditions or exceeding the stated values.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

The display device refers to a product having an image display function, and may be, for example: a display, a television, a billboard, a Digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a Digital camera, a camcorder, a viewfinder, a monitor, a navigator, a vehicle, a large-area wall, a home appliance, an information inquiry apparatus (e.g., a business inquiry apparatus, a monitor, etc. in the departments of e-government, banking, hospital, electric power, etc.).

In some embodiments, referring to fig. 2A, the display device includes a display panel, but is not limited thereto, and for example, a control driving circuit, a processor, a brightness sensor, and the like connected to the display panel may be further included.

Wherein, controlling the driving circuit may include: a driver chip (i.e., a driver chip) that may include: a Display Driver IC (DDIC), a Source Driver IC (Source Driver IC), and the like. The driving chip is configured to provide data signals to the plurality of pixel driving circuits to drive the display panel to display images.

And the processor is a control center of the display device, can be coupled with the control driving circuit and is configured to provide the data to be displayed to the control driving circuit, so that the source driving chip can generate a data signal corresponding to the data to be displayed. Illustratively, the processor may include at least one of an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a Field Programmable Gate Array (FPGA), and the like.

And the brightness sensor is coupled with the processor and is configured to sense the brightness of the ambient light of the environment where the display device is located and transmit the sensed brightness to the processor so as to enable the processor to execute the operation corresponding to the received brightness.

The display panel is used for displaying images (i.e. pictures), and the display panel may be an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro LED (including a miniLED or a micro LED) display panel, or the like.

Fig. 2B is a top view of a display panel according to some embodiments of the invention. Referring to fig. 2B, the display panel 1 has a display Area (AA) and a peripheral Area S located on at least one side of the display Area AA, for example, the peripheral Area S may be disposed around the display Area AA.

The display panel 1 includes: a plurality of sub-pixels P located in the area AA, each of which includes one pixel driving circuit 10 and one light emitting device 20 coupled thereto. The sub-pixels P may be named according to their light emission colors, for example, the light emission colors of the sub-pixels are the three primary colors of light: red (R), green (G), and blue (B), then the corresponding sub-pixels may be named red, green, and blue sub-pixels, respectively. It should be noted that fig. 2B only exemplarily illustrates the coupling relationship between the pixel driving circuit 10 and the light emitting devices 20 in the sub-pixel P, and is not intended to limit the forms, sizes, arrangements, etc. of each pixel driving circuit 10 and each light emitting device 20, for example, the sizes of at least two light emitting devices 20 may be different; as another example, the light emitting device 20 and the coupled pixel driving circuit 10 may have an overlapping portion in the thickness direction of the display panel 1.

The light emitting device 20 emits light under the driving action of the pixel driving circuit 10 coupled thereto. Illustratively, the Light Emitting device may include a Light Emitting Diode (LED) or an Organic Light Emitting Diode (OLED), and the like. For example, as shown in fig. 2C, the light-emitting device 20 includes a cathode 21 and an anode 22, and a light-emitting functional layer 23 located between the cathode 21 and the anode 22. The light-emitting function Layer 23 may include, for example, a light-emitting Layer 231, a Hole Transporting Layer (HTL) 232 located between the light-emitting Layer 231 and the anode 22, and an Electron Transporting Layer (ETL) 233 located between the light-emitting Layer 231 and the cathode 21. Of course, in some embodiments, a Hole Injection Layer (HIL) 234 may be disposed between the Hole transport Layer 232 and the anode 22, and an Electron Injection Layer (EIL) 235 may be disposed between the electron transport Layer 233 and the cathode 21.

Illustratively, the anode 22 may include, for example, a conductive layer formed of a conductive material having a high work function, which may include Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Oxide (IGO), gallium Zinc Oxide (GZO), zinc oxide (ZnO), indium oxide (In 2O 3), aluminum Zinc Oxide (AZO), carbon nanotubes, and the like; the cathode 21 may include, for example, a conductive layer formed of a material having high conductivity and low work function, and the conductive material may include an alloy such as magnesium aluminum alloy (MgAl) and lithium aluminum alloy (LiAl) or a simple metal such as magnesium (Mg), aluminum (Al), lithium (Li), and silver (Ag). The material of the light-emitting layer may be selected according to the color of light emitted therefrom. For example, the material of the light-emitting layer includes a fluorescent light-emitting material or a phosphorescent light-emitting material. For example, in at least one embodiment of the present invention, the light emitting layer may employ a dopant system, i.e., a dopant material is mixed into the host light emitting material to obtain a useful light emitting material. For example, as the host light-emitting material, a metal compound material, a derivative of anthracene, an aromatic diamine compound, a triphenylamine compound, an aromatic triamine compound, a biphenyldiamine derivative, a triarylamine polymer, or the like can be used.

The pixel driving circuit is configured to drive the light emitting device coupled thereto to emit light according to the received data signal, for example, the pixel driving circuit provides a corresponding driving current to the light emitting device according to the received data signal, wherein the data signal received by the pixel driving circuit may be a voltage signal, and the magnitude of the driving current generated according to the voltage value of the received voltage signal is different, and the magnitude of the driving current can control the light emitting brightness of the light emitting device.

The structure of the pixel driving circuit can be designed according to actual conditions. Illustratively, the pixel driving circuit is composed of electronic devices such as a Transistor (Transistor, abbreviated as T), a capacitor (capacitor, abbreviated as C), and the like. For example, the pixel driving circuit may include seven transistors (six switching transistors and one driving transistor) and one capacitor, constituting a 7T1C structure. The Transistor may be a Thin Film Transistor (TFT), a field effect Transistor (MOS), or a switching device with other characteristics.

Some embodiments of the present invention provide a pixel driving circuit, and referring to fig. 3, the pixel driving circuit 10 includes: a driving sub-circuit 11, a first reset sub-circuit 12 and a first node N1.

Wherein the drive sub-circuit 11 comprises a control terminal 110, a first terminal 111 and a second terminal 112, the drive sub-circuit 11 being configured to control a drive current Id flowing through the first terminal 111 and the second terminal 112 of the drive sub-circuit 11.

Illustratively, the driving sub-circuit 11 is configured to control a driving current Id flowing through the first terminal 111 and the second terminal 112 in response to a voltage of the control terminal 110. The magnitude of the driving current Id depends on the magnitude of the voltage at the control terminal 111 of the driving sub-circuit 11, for example, in a value range of the voltage at the control terminal 110, the larger the absolute value of the voltage at the control terminal 110 of the driving sub-circuit 11 is, the larger the driving current Id flows through the first terminal 111 and the second terminal 112 of the driving sub-circuit.

The first terminal 111 of the driving sub-circuit 11 is coupled to a first power voltage terminal VDD, the second terminal 112 of the driving sub-circuit 11 is coupled to a first node N1, and the first node N1 and the second power voltage terminal VSS are configured to be coupled to two poles of the light emitting device 20, respectively.

In the embodiment of the present invention, the first node N1 does not represent an actually existing component, but represents a junction of related circuit connections in the circuit diagram, that is, the first node N1 is a node equivalent to the junction of related circuit connections in the circuit diagram.

Illustratively, the voltage provided by the first power supply voltage terminal VDD is greater than the voltage provided by the second power supply voltage terminal VSS. The first terminal 111 of the driving sub-circuit 11 is coupled to the first power voltage terminal VDD, and the second terminal 112 of the driving sub-circuit 11 is coupled to the second power voltage terminal VSS via the first node N1 and the light emitting device 20; at this time, the first node N1 is coupled to the anode of the light emitting device 20, and the second power voltage terminal VSS is coupled to the cathode of the light emitting device 20. When the first terminal 111 and the second terminal 112 of the driving sub-circuit 11 are turned on, a voltage difference (also referred to as a voltage difference or a voltage cross) between the first power voltage terminal VDD and the second power voltage terminal VSS causes a driving current Id, which flows through the light emitting device 20, such that the light emitting device 20 is driven to emit light.

In the embodiment of the invention, the voltage provided by the first power supply voltage terminal VDD can be constant, and the voltage provided by the second power supply voltage terminal VSS can be adjustable. Under the condition that the voltage of the control terminal 110 of the driving sub-circuit 11 is constant, the larger the voltage difference between the first power voltage terminal VDD and the second power voltage terminal VSS, the larger the driving current Id flowing through the first terminal 111 and the second terminal 112 of the driving sub-circuit 11, and the larger the light emitting luminance of the light emitting device 20. Therefore, the voltage provided by the second power voltage terminal VSS is adjustable, so that the display brightness of the display device (or the display panel) can be adjusted. Wherein, the display brightness is: the display device can achieve a brightness level when displaying a white screen (for example, when all the gray scale values of the red sub-pixel, the green sub-pixel and the blue sub-pixel in the display panel are the maximum gray scale). Illustratively, the second power supply voltage terminal VSS may provide different voltages in different operation modes of the display device. For example, the operation modes of the display device include a normal mode and a high luminance mode, wherein the display luminance of the display device in the high luminance mode may be higher than the highest display luminance thereof in the normal mode. The display device may have a plurality of display luminances in the normal mode, where the highest display luminance refers to a maximum value among the plurality of display luminances. For example, the display device displays an interface containing a brightness bar, and a user can adjust the display brightness by adjusting the length of the brightness bar (belonging to a brightness adjustment parameter); when the luminance bar is longest, the display luminance of the display device may be set as the highest display luminance in the normal mode. In addition, the display device may have only one display luminance in the normal mode, which is the highest display luminance. The second power supply voltage terminal VSS supplies a voltage lower (i.e., less than) the lowest voltage supplied in its normal mode in the high brightness mode. For example, the voltage provided by the first power supply voltage terminal VDD is 4.6 ± 0.5V (i.e. between 4.1V and 5.1V), for example, 4.6V; the voltage supplied from the second power voltage terminal VSS in the high brightness mode is (-4.8) — (-2) V, and the voltage supplied from the second power voltage terminal VSS in the normal mode is 2-4.4V.

Since the second power supply voltage terminal VSS provides a lower voltage in the high luminance mode of the display device than it provides in the normal mode, a voltage cross between the first power supply voltage terminal VDD and the second power supply voltage terminal VSS causes the driving current Id to be larger in the high luminance mode than in the normal mode, and thus, the display device can provide a higher luminance in the high luminance mode than in the normal mode.

Illustratively, the processor in the display device may be further configured to determine an operation mode of the display device according to the brightness sensed by the brightness sensor. For example, the processor determines the operation mode of the display apparatus as a high brightness mode in a case where the brightness sensed by the brightness sensor is higher than a brightness threshold, and determines the operation mode of the display apparatus as a normal mode in a case where the brightness sensed by the brightness sensor is lower than the brightness threshold.

A control drive circuit (e.g., a driver chip) in the display device is configured to supply a voltage to the second power supply voltage terminal VSS based on the operation mode determined by the processor. In some embodiments, the control driving circuit is configured to supply the first voltage V1 to the second power supply voltage terminal VSS of the display panel, or supply the second voltage V2 to the second power supply voltage terminal VSS of the display panel, wherein the first voltage V1 is less than the second voltage V2. Illustratively, the control driving circuit supplies the first voltage V1 to the second power voltage terminal VSS in a case where the processor determines the operation mode of the display device as the high brightness mode, and supplies the second voltage V2 to the second power voltage terminal VSS in a case where the processor determines the operation mode of the display device as the normal mode. For example, the first voltage V1 ranges from (-4.8) to (-2) V, and the second voltage V2 ranges from 2 to 4.4V.

In addition, in any operation mode of the display device, for example, in a normal operation mode of the display device, the voltage provided by the second power supply voltage terminal VSS is adjustable within a certain range, so that the display brightness of the display device is adjusted. Illustratively, the processor in the display device may be further configured to determine a brightness adjustment parameter; the control driving circuit (e.g., driving chip) is configured to supply a voltage to the second power supply voltage terminal VSS based on the operation mode determined by the processor and the brightness adjustment parameter. For example, as in the above example, in the case where the display device is in the normal mode, the control driving circuit (e.g., the source drive IC) in the display device may supply one of 2 to 4.4V corresponding to the luminance adjustment parameter to the second power supply voltage terminal VSS according to the luminance adjustment parameter, so that the display device can display at a luminance corresponding to the voltage.

The first reset sub-circuit 12 is coupled between the first node N1 and a reset voltage terminal (also referred to as an initialization signal terminal) Vint, and configured to form a first path L1 between the reset voltage terminal Vint and the first node N1 in response to a first control signal; in a second reset phase, in response to a second control signal, a second path L2 is formed between the reset voltage terminal Vint and the first node N1, wherein the equivalent resistance of the first path L1 is greater than the equivalent resistance of the second path L2.

The first reset sub-circuit 12 is configured to reset the light emitting device 20, e.g. the first reset sub-circuit 12 is configured to reset the anode voltage of the light emitting device 20 to a corresponding reset voltage in a reset phase (also referred to as initialization phase). The reset phase may be a first reset phase or a second reset phase, for example, the first reset phase is a reset phase of the pixel driving circuit 10 when the display device is in the high brightness mode, and the second reset phase is a reset phase of the pixel driving circuit 10 when the display device is in the normal mode.

Illustratively, the first control signal VH may output an active voltage and an inactive voltage, wherein the reset sub-circuit 12 forms a first path L1 between the reset voltage terminal Vint and the first node N1 in response to the active voltage of the first control signal VH in a case where the first control signal VH outputs the active voltage; similarly, the second control signal VN may also output an active voltage and an inactive voltage, wherein the reset sub-circuit 12 forms the second path L2 between the reset voltage terminal Vint and the first node N1 in response to the active voltage of the second control signal VN in a case where the second control signal VN outputs the active voltage. For example, the active voltage may be low, and the inactive voltage may be high; and vice versa.

The equivalent resistance refers to a ratio of a voltage difference between the reset voltage terminal Vint and the first node N1 to a current flowing through a path formed by the reset voltage terminal Vint and the first node N1. Illustratively, in a case where a first path L1 is formed between the reset voltage terminal Vint and the first node N1, a voltage difference between the reset voltage terminal Vint and the first node N1 is Δ U1, and a current flowing through the first path L1 is Id2 ₁ Then, at this time, the first equivalent resistance R1=Δu1/Id2 between the reset voltage terminal Vint and the first node N1 ₁ (ii) a When the second path L2 is formed between the reset voltage terminal Vint and the first node N1, a voltage difference between the reset voltage terminal Vint and the first node N1 is Δ U2, and a current flowing through the second path L2 is Id2 ₂ Then, at this time, the second equivalent resistance R2= =Δu2/Id2 between the reset voltage terminal Vint and the first node N1 ₂ 。

In the embodiment of the invention, since the first equivalent resistance R1 is greater than the second equivalent resistance R2, the driving current Id2 flowing through the first path L1 is constant under the condition that the voltage difference between the reset voltage terminal Vint and the first node N1 is constant ₁ Less than the drive current Id2 of L2 flowing through the second path ₂ 。

In the related art pixel driving circuit, referring to fig. 1, a path L ' is formed between the reset voltage terminal Vint and the first node N1' in the reset stage, and exemplarily, an equivalent resistance of the path L ' is the same as an equivalent resistance of the second path L2 in the embodiment of the present invention. In addition, in the case where the first reset sub-circuit 12' includes the transistor T ', the driving current Id2' flowing through the path L ' may be a drain current of the transistor T '.

When the display apparatus displays a black screen, the magnitude of the driving current flowing through the light emitting device 20 may be controlled to be less than the critical light emitting current of the light emitting device 20 in the normal mode of the display apparatus so that the light emitting device 20 does not emit light. In the high brightness mode of the display device, since the voltage of the second power voltage terminal VSS is lower than that in the normal mode, at this time, the voltage across the first power voltage terminal VDD and the second power voltage terminal VSS increases, so that the driving current Id1' flowing from the first power voltage terminal VDD through the first node increases compared with that in the normal mode; the voltage across the reset voltage terminal Vint and the second power voltage terminal VSS also increases, so that the driving current Id2' flowing through the first node N1 along the path L ' also increases, and thus, the driving current Id3' = Id1' + Id2' flowing through the light emitting device 20 may be greater than the critical light emitting current of the light emitting device 20, resulting in the light emitting device 20 emitting light. When the display apparatus displays a black screen in the high brightness mode, the display apparatus displays a screen having a certain brightness instead of the black screen due to the light emission of the light emitting device 20, that is, a problem of the black screen being bright occurs.

In the embodiment of the invention, referring to fig. 3, when the voltage of the control terminal 110 of the driving sub-circuit 11 is constant, the driving current flowing through the first terminal 111 and the second terminal 112 of the driving sub-circuit 11 (i.e. the driving current flowing from the first power voltage terminal VDD through the first node N1) in the high brightness mode is Id1, and the driving current flowing along the first path L1 through the first node N1 is Id2 ₁ At this time, the driving current Id3= Id1+ Id2 flowing through the light emitting device 20 ₁ . Here, the driving current Id1 is the same as the driving current Id1 'in the related art, and in the case where the equivalent resistance of the second path L2 in the embodiment of the present invention is the same as the equivalent resistance of the path L' in the related art, the driving current Id2 ₁ Smaller than the driving current Id2', the driving current Id3 flowing through the light emitting device 20 in the embodiment of the present invention is smaller than the driving current Id3' flowing through the light emitting device 20 in the related art, so that the driving current flowing through the light emitting device 20 can be reduced, thereby improving the problem of black frame luminance generated by the display device in the high luminance mode to a certain extent.

For example, in the case that the display apparatus is in the high brightness mode, the pixel driving circuit 10 may be controlled to enter the second reset phase to reset the anode of the light emitting device through the second path L2 formed between the reset signal terminal Vint and the first node NI, so as to avoid the situation that the driving current flowing through the light emitting device is too large due to the reset using the first path L1.

In some embodiments, in the case where the display device includes a control drive circuit, the control drive circuit in the display device drives at least one pixel drive circuit 10 in the display panel into the first reset phase or the second reset phase. Wherein, in a first reset stage, the driving circuit is controlled to provide a first voltage V1 to a second power supply voltage terminal VSS of the display panel; in a second reset phase, the driving circuit is controlled to provide a second voltage V2 to the second power voltage terminal VSS of the display panel, wherein the first voltage V1 is less than the second voltage V2.

In some embodiments, referring to fig. 3, the pixel driving circuit 10 may further include at least one of a data writing sub-circuit 13, a compensation sub-circuit 14, a first light emission control sub-circuit 15, a second light emission control sub-circuit 16, and a second resetting sub-circuit 17.

Wherein the second reset sub-circuit 17 is coupled to the control terminal 110 of the driving sub-circuit 11 and the reset voltage terminal Vint, the second reset sub-circuit 17 is configured to form a path between the reset voltage terminal Vint and the control terminal 110 of the driving sub-circuit 11 in response to the first scan signal G1, so as to apply the voltage of the reset voltage terminal Vint to the control terminal 110 of the driving sub-circuit 11.

The data writing sub-circuit 13 is coupled to the first terminal 111 of the driving sub-circuit 11 and the data signal terminal Vdata, and the data writing sub-circuit 13 is configured to transmit the data signal Vdata provided by the data signal terminal Vdata to the first terminal 111 of the driving sub-circuit 11 in response to the second scan signal G2 (a signal provided by the second scan signal terminal G2).

The compensation sub-circuit 14 is coupled to the first power voltage terminal VDD, the control terminal 110 of the driving sub-circuit 11, and the second terminal 112 of the driving sub-circuit 11, and the compensation sub-circuit 14 is configured to respond to the second scan signal G2 and transmit the compensated data signal Vdata' to the control terminal 110 of the driving sub-circuit 11 in cooperation with the data writing sub-circuit 13; for example, the data signal Vdata' is a data signal compensated by the threshold voltage of the driving sub-circuit 11. The compensation sub-circuit 14 may also be configured to store the compensated data signal Vdata'.

The first emission control sub-circuit 15 is coupled to the first power voltage terminal VDD and the first terminal 111 of the driving sub-circuit 11, and the first emission control sub-circuit 15 is configured to form a path between the first power voltage terminal VDD and the first terminal 111 of the driving sub-circuit 11 in response to the emission control signal EM to apply the voltage of the first power voltage terminal VDD to the first terminal 111 of the driving sub-circuit 11.

The second emission control sub-circuit 16 is coupled to the second terminal 112 of the driving sub-circuit 11 and the first node N1, and the second emission control sub-circuit 16 is configured to form a path between the second terminal 112 of the driving sub-circuit 11 and the first node in response to the emission control signal EM to apply the driving current Id to the light emitting device 20 through the first node N1.

Referring to fig. 4-5B, some embodiments of the invention provide a pixel driving circuit 10, and these pixel driving circuits 10 may be implemented as some specific implementations of the pixel driving circuit provided in fig. 3, which may not be limited to implementing the functions that can be implemented by the sub-circuits in fig. 3.

It should be noted that each of the sub-circuits in the embodiments of the present invention may include one or more transistors, and each of the transistors is exemplified as a thin film transistor, wherein a control electrode of the thin film transistor is a gate electrode, a first electrode of the thin film transistor is one of a source electrode and a drain electrode, and a second electrode of the thin film transistor is the other of the source electrode and the drain electrode. Since the source and drain electrodes of the thin film transistor can perform the same function in the thin film transistor, the source and drain electrodes may not be particularly distinguished. In one example, in the case where the thin film transistor is a P-type transistor, the first pole of the thin film transistor is a source electrode and the second pole is a drain electrode. In another example, in the case where the thin film transistor is an N-type transistor, the first pole of the transistor is a drain and the second pole is a source.

In the pixel driving circuit provided by the embodiment of the present invention, the thin film transistor is exemplified as a P-type transistor. It should be noted that the embodiments of the present invention include but are not limited thereto. For example, one or more thin film transistors in the pixel driving circuit provided in the embodiment of the present invention may also be N-type transistors, and it is only necessary to connect the respective poles of the selected type of thin film transistors with reference to the respective poles of the corresponding thin film transistors in the embodiment of the present invention, and to make the corresponding control poles supply the corresponding high-level voltage or low-level voltage.

In some embodiments, referring to fig. 4, the first reset sub-circuit 12 includes a first transistor T1 and a second transistor T2. A control electrode of the first transistor T1 is coupled to the first control signal terminal VH and configured to receive the first control signal VH, a first electrode of the first transistor T1 is coupled to the reset voltage terminal Vint, and a second electrode of the first transistor T1 is coupled to the first node N1. A control electrode of the second transistor T2 is coupled to the second control signal terminal VN and configured to receive the second control signal VN, a first electrode of the second transistor T2 is coupled to the reset voltage terminal Vint, and a second electrode of the second transistor T2 is coupled to the first node N1. The width-to-length ratio of the first transistor T1 is smaller than the width-to-length ratio of the second transistor T2.

The width to length ratio of a transistor refers to the ratio of the width to the length of the channel of the transistor. When the voltage across the transistor is constant, the larger the aspect ratio, the larger the current through the transistor. For example, referring to fig. 4, under the condition that the voltage difference between the reset signal terminal Vint and the first node N1 is constant, in the first reset stage, the first transistor T1 is turned on, the second transistor T2 is turned off, and the first path L1 is formed, at this time, the current flowing through the first transistor T1 is the driving current Id2 flowing through the first path L1 ₁ (ii) a In the second reset stage, the first transistor T1 is turned off, the second transistor T2 is turned on, and a second path L2 is formed, at this time, the current flowing through the second transistor T2 is the driving current Id2 flowing through the second path L2 ₂ Wherein the drive current Id2 ₁ Less than the drive current Id2 ₂ . In some embodiments, in the first reset phase, the current flowing through the first transistor T1 is a leakage current of the first transistor T1; in the second timeIn the bit phase, the current flowing through the second transistor T2 is the leakage current of the second transistor T2.

In some embodiments, the width-to-length ratio of the first transistor T1 ranges from 0.4 to 0.48, and the width-to-length ratio of the second transistor T2 ranges from 0.49 to 0.73. Illustratively, the width-to-length ratio of the first transistor T1 may be designed to be 2.2/4.5 or 2.2/5.5, and the width-to-length ratio of the second transistor T2 may be designed to be 2.2/3, 2.2/4, 2.2/5.5, etc.

In some embodiments, the width of the channel of the first transistor T1 is the same as that of the second transistor T2, and the length of the channel of the first transistor T1 is greater than that of the channel of the second transistor T2. Illustratively, the widths of the channels of the first transistor T1 and the second transistor T2 are each designed to be 2.2 μm, and the width-to-length ratios of the respective channels are adjusted by adjusting the lengths of the channels of the first transistor T1 and the second transistor T2. In the pixel driving circuit 10, the aspect ratio of each transistor is generally smaller than 1, that is, the length of the channel of the transistor is generally larger than the width of the channel, and it is easier to adjust the aspect ratio by adjusting the channel length of the transistor to meet the manufacturing accuracy of the transistor in terms of process.

In some embodiments, referring to fig. 5A and 5B, the first reset sub-circuit 12 further includes a third transistor T3. Referring to fig. 5A, a control electrode of the third transistor T3 is coupled to the first scan signal terminal G1 and configured to receive the first scan signal G1, a first electrode of the third transistor T3 is coupled to a second electrode of the first transistor T1 and a second electrode of the second transistor T2, and a second electrode of the third transistor T3 is coupled to the first node N1.

The third transistor T3 is configured to be turned on in the first reset phase and the second reset phase, and exemplarily, the turn-on period of the third transistor T3 is the same as one of the first transistor T1 and the second transistor T2. For example, in the first reset phase, the first transistor T1 and the third transistor T3 in the reset sub-circuit 12 are turned on, and the second transistor T2 is turned off, so as to form a first path L1 between the reset signal terminal Vint and the first node N1; in the second reset phase, the second transistor T2 and the third transistor T3 in the reset sub-circuit 12 are turned on, and the first transistor T1 is turned off to form a second path L2 between the reset signal terminal Vint and the first node N1.

Also exemplarily, the turn-on period of the third transistor T3 is different from both the first transistor T1 and the second transistor T2. For example, in the case where the display device is in the high brightness mode, the first transistor T1 is continuously turned on and the second transistor T2 is continuously turned off, and in the case where the display device is in the normal mode, the first transistor T1 is continuously turned off and the second transistor T2 is continuously turned on, while the third transistor T3 is turned on in the corresponding first and second reset phases, and the first path L1 or the second path L2 is formed. The continuous on or continuous off refers to a state that the transistor is always on or off from the starting time of the corresponding mode to the ending time of the corresponding mode.

In other embodiments, referring to fig. 5B, the third transistor T3 may also be connected as follows: a control electrode of the third transistor T3 is coupled to the first scan signal terminal G1 and configured to receive the first scan signal G1, a first electrode of the third transistor T3 is coupled to the reset voltage terminal Vint, and a second electrode of the third transistor T3 is coupled to the first electrode of the first transistor T1 and the first electrode of the second transistor T2. The control method is similar to the above embodiment and is not described again.

In some embodiments, referring to fig. 4 to 5B, the driving sub-circuit 11 includes a driving transistor DT, a control electrode of the driving transistor DT serves as a control terminal 110 of the driving sub-circuit 11, a first electrode of the driving transistor DT serves as a first terminal 111 of the driving sub-circuit 11, and a second electrode of the driving transistor DT serves as a second terminal 112 of the driving sub-circuit 11.

In some embodiments, in the pixel driving circuit 10, the data writing sub-circuit 13 includes a fourth transistor T4, the compensation sub-circuit 14 includes a fifth transistor T5 and a storage capacitor Cst, the first light emission control sub-circuit 15 includes a sixth transistor T6, the second light emission control sub-circuit 16 includes a seventh transistor T7, and the second reset sub-circuit 17 includes an eighth transistor T8.

A control electrode of the fourth transistor T4 is coupled to the second scan signal terminal G2 and configured to receive the second scan signal G2, a first electrode of the fourth transistor T4 is coupled to the data signal terminal Vdata, and a second electrode of the fourth transistor T4 is coupled to the first terminal 111 of the driving sub-circuit 11.

A control electrode of the fifth transistor T5 is coupled to the second scan signal terminal G2 and configured to receive the second scan signal G2, a first electrode of the fifth transistor T5 is coupled to the second terminal 112 of the driving sub-circuit 11, and a second electrode of the fifth transistor T5 is coupled to the control terminal 110 of the driving sub-circuit 11.

A control electrode of the sixth transistor T6 is coupled to the emission control signal terminal EM and configured to receive the emission control signal EM, a first electrode of the sixth transistor T6 is coupled to the first power voltage terminal VDD, and a second electrode of the sixth transistor T6 is coupled to the first terminal 111 of the driving sub-circuit 11.

A control electrode of the seventh transistor T7 is coupled to the emission control signal terminal EM and configured to receive the emission control signal EM, a first electrode of the seventh transistor T7 is coupled to the second terminal 112 of the driving sub-circuit 11, and a second electrode of the seventh transistor T7 is coupled to the first node N1.

A control electrode of the eighth transistor T8 is coupled to the first scan signal terminal G1 and configured to receive the first scan signal G1, a first electrode of the eighth transistor T8 is coupled to the reset voltage terminal Vint, and a second electrode of the eighth transistor T8 is coupled to the control terminal 110 of the driving sub-circuit 11.

A first plate of the storage capacitor Cst is coupled to the control terminal 110 of the driving sub-circuit 11, and a second plate of the storage capacitor Cst is coupled to the first power voltage terminal VDD.

In the description of the embodiment of the present invention, the symbol VH may represent both the first control signal terminal and the first control signal, the symbol VN may represent both the second control signal terminal and the second control signal, the symbol G1 may represent both the first scan signal terminal and the first scan signal, the symbol G2 may represent both the second scan signal terminal and the second scan signal, the symbol Vdata may represent both the data signal terminal and the data signal, and the symbol EM may represent both the emission control signal terminal and the emission control signal. The following embodiments are the same and will not be described again.

The embodiment of the invention also provides a driving method of the pixel driving circuit, and the pixel driving circuit can be the pixel driving circuit described in any one of the embodiments. The control method comprises the following steps:

providing a second voltage to the second power supply voltage terminal, and forming a second path between the reset voltage terminal and the first node in response to a second control signal during a second reset phase;

the first voltage is smaller than the second voltage, and the equivalent resistance of the first path is larger than that of the second path.

Illustratively, a display device (e.g., a control drive circuit in a display device) provides a first voltage to a second power supply voltage terminal coupled to a pixel drive circuit in a high brightness mode and drives the corresponding pixel drive circuit into a first reset phase; in the first reset phase, a first reset sub-circuit in the pixel driving circuit forms a first path between a reset voltage terminal and a first node in response to a first control signal.

Also illustratively, the display device (e.g., a control driver circuit in the display device) provides a second voltage to a second power supply voltage terminal coupled to the pixel driver circuit in the normal mode, and drives the corresponding pixel driver circuit into a second reset phase; in the second reset phase, the first reset sub-circuit in the pixel driving circuit forms a second path between the reset voltage terminal and the first node in response to the second control signal.

In some embodiments, the driving method of the pixel driving circuit further includes:

in a reset phase (a first reset phase or a second reset phase), the second reset sub-circuit forms a path between the reset voltage terminal and the control terminal of the driving sub-circuit in response to the first scan signal to apply the voltage of the reset voltage terminal to the control terminal of the driving sub-circuit;

in the data writing stage, the data writing sub-circuit responds to the second scanning signal and transmits the data signal provided by the data signal end to the driving sub-circuit; the compensation sub-circuit responds to the second scanning signal and transmits the compensated data signal to the control end of the driving sub-circuit in cooperation with the data writing sub-circuit;

in the light emitting phase, the first light emitting control sub-circuit responds to the light emitting control signal and forms a path between a first power supply voltage terminal and a first terminal of the driving sub-circuit so as to apply the voltage of the first power supply voltage terminal to the first terminal of the driving sub-circuit; the second light emission control sub-circuit forms a path between the second terminal of the driving sub-circuit and the first node in response to the light emission control signal to apply the driving current to the light emitting device through the first node.

A driving method of the pixel driving circuit according to the above-described embodiment will be described with reference to a signal timing chart shown in fig. 6 and the pixel driving circuit shown in fig. 4. Where (a) in fig. 6 shows a signal timing chart of the pixel driving circuit when the display device is in the normal mode, and (b) in fig. 6 shows a signal timing chart of the pixel driving circuit when the display device is in the high luminance mode. As shown in fig. 6, the display process of each frame image of the pixel drive circuit includes three stages, a reset stage, a data write stage, and a light emission stage, and fig. 6 shows timing waveforms of respective signals in each stage.

Fig. 7A and 7B are signal transmission diagrams of the pixel driving circuit shown in fig. 4 at different stages, wherein fig. 7A is the signal transmission diagram in the high brightness mode, and fig. 7B is the signal transmission diagram in the normal mode. Fig. 7A and 7B (a) are signal transfer diagrams when the pixel driving circuit shown in fig. 4 is in a reset phase (a first reset phase or a second reset phase), fig. 7A and 7B (B) are signal transfer diagrams when the pixel driving circuit shown in fig. 4 is in a data writing phase, and fig. 7A and 7B (c) are signal transfer diagrams when the pixel driving circuit shown in fig. 4 is in a light emitting phase. Transistors identified by "x" in fig. 7A and 7B each indicate being in an off state in a corresponding stage, and solid lines with arrows in fig. 7A and 7B indicate signal transmission paths of the pixel drive circuit in the corresponding stage. The transistors shown in fig. 7A and 7B are each illustrated as P-type transistors, i.e., the gate of each P-type transistor is turned on when a high level is turned on and turned off when a low level is turned on.

Referring to fig. 7A, a driving process of the pixel driving circuit shown in fig. 4 will be described with reference to a timing chart of (b) in fig. 6, taking as an example that the display device is in the high luminance mode. It is to be noted that, in the case where the display apparatus is in the high luminance mode, the second control signal VN always outputs the inactive voltage (high level), and the second transistor T2 is always in the off state in the high luminance mode in response to the inactive voltage of the second control signal VN.

Exemplarily, referring to (a) of fig. 7A, in the first reset phase, the first transistor T1 is turned on in response to the first control signal VH, and a first path is formed between the reset voltage terminal Vint and the first node N1 to reset the anode of the light emitting device 20; meanwhile, the eighth transistor T8 is turned on in response to the first scan signal G1, and the voltage of the reset voltage terminal Vint is applied to the control electrode (G) of the driving transistor DT through the eighth transistor T8, thereby resetting the control electrode (G) of the driving transistor DT.

In the data writing phase, referring to (b) of fig. 7A, the fifth transistor T5 and the fourth transistor T4 are turned on in response to the second scan signal G2, and when the fifth transistor T5 is turned on, the control electrode (G) of the driving transistor DT is coupled to the second electrode (d) such that the driving transistor DT is in a diode-on state. At this time, the data signal Vdata provided from the data signal terminal Vdata is transmitted to the first pole(s) of the driving transistor DT through the fourth transistor T4, and compensates for the threshold voltage (Vth) of the driving transistor DT.

In the light emitting phase, referring to (c) of fig. 7A, the sixth transistor T6 and the seventh transistor T7 are turned on in response to the light emission control signal EM, and the current path between the first power supply voltage terminal VDD and the second power supply voltage terminal VSS is turned on. Under the control of the voltage of the control electrode (g) of the driving transistor DT, the driving current Id flowing through the first electrode(s) and the second electrode (d) of the driving transistor DT is transmitted to the light emitting device 20 through the first node N1, and the light emitting device 20 is driven to emit light.

In the case where the display device is in the normal mode, referring to fig. 7B, the driving process of the pixel driving circuit is similar to that in the high luminance mode described above, except that in the high luminance mode, the second transistor T2 is turned on in a reset phase (i.e., a second reset phase) in response to the second control signal VH, while the first control signal VH always outputs an inactive voltage (high level), and the first transistor T1 is always in an off state in response to the inactive voltage of the first control signal VH.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A pixel driving circuit, comprising:

a drive sub-circuit comprising a control terminal, a first terminal, and a second terminal, the drive sub-circuit configured to control a drive current flowing through the first and second terminals of the drive sub-circuit; a first terminal of the driving sub-circuit is coupled to a first power voltage terminal, a second terminal of the driving sub-circuit is coupled to a first node, and the first node and the second power voltage terminal are configured to be coupled to two poles of the light emitting device respectively;

a first reset sub-circuit coupled between the first node and a reset voltage terminal and configured to form a first path between the reset voltage terminal and the first node in response to a first control signal during a first reset phase; forming a second path between the reset voltage terminal and the first node in response to a second control signal during a second reset phase;

wherein an equivalent resistance of the first path is greater than an equivalent resistance of the second path.

2. The pixel driving circuit according to claim 1,

the first reset sub-circuit includes:

a first transistor having a control electrode coupled to a first control signal terminal configured to receive the first control signal, a first electrode coupled to the reset voltage terminal, and a second electrode coupled to the first node;

a second transistor having a control electrode coupled to a second control signal terminal and configured to receive the second control signal, a first electrode coupled to the reset voltage terminal, and a second electrode coupled to the first node;

wherein the width-to-length ratio of the first transistor is smaller than the width-to-length ratio of the second transistor.

3. The pixel driving circuit according to claim 2,

the value range of the width-length ratio of the first transistor is 0.4-0.48;

and/or the presence of a gas in the gas,

the width-length ratio of the second transistor ranges from 0.49 to 0.73.

4. The pixel driving circuit according to claim 2,

the width of the channel of the first transistor is the same as that of the channel of the second transistor, and the length of the channel of the first transistor is larger than that of the channel of the second transistor.

5. The pixel driving circuit according to claim 2,

the first reset sub-circuit further comprises: a third transistor;

a control electrode of the third transistor is coupled to a first scan signal terminal and configured to receive a first scan signal, a first electrode of the third transistor is coupled to a second electrode of the first transistor and a second electrode of the second transistor, and a second electrode of the third transistor is coupled to the first node;

or,

a control electrode of the third transistor is coupled to the first scan signal terminal and configured to receive a first scan signal, a first electrode of the third transistor is coupled to the reset voltage terminal, and a second electrode of the third transistor is coupled to the first electrode of the first transistor and the first electrode of the second transistor.

6. The pixel driving circuit according to claim 1,

the driving sub-circuit includes:

and a control electrode of the driving transistor is used as a control end of the driving sub-circuit, a first electrode of the driving transistor is used as a first end of the driving sub-circuit, and a second electrode of the driving transistor is used as a second end of the driving sub-circuit.

7. The pixel driving circuit according to claim 1,

the pixel driving circuit further comprises at least one of a data writing sub-circuit, a compensation sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit and a second resetting sub-circuit;

the data writing sub-circuit is coupled with the first end of the driving sub-circuit and a data signal end, and the data writing sub-circuit is configured to respond to a second scanning signal and transmit a data signal provided by the data signal end to the first end of the driving sub-circuit;

the compensation sub-circuit is coupled with the first power voltage terminal, the control terminal of the driving sub-circuit and the second terminal of the driving sub-circuit, and the compensation sub-circuit is configured to respond to the second scanning signal and transmit a compensated data signal to the control terminal of the driving sub-circuit in cooperation with the data writing sub-circuit;

the first emission control sub-circuit is coupled to the first power supply voltage terminal, the first terminal of the driver sub-circuit, and configured to form a path between the first power supply voltage terminal and the first terminal of the driver sub-circuit in response to an emission control signal;

the second emission control sub-circuit is coupled to the first node and the second terminal of the driving sub-circuit, the second emission control sub-circuit being configured to form a path between the first node and the second terminal of the driving sub-circuit in response to an emission control signal;

the second reset sub-circuit is coupled to the control terminal of the driving sub-circuit and a reset voltage terminal, and the second reset sub-circuit is configured to form a path between the reset voltage terminal and the control terminal of the driving sub-circuit in response to a first scan signal.

8. The pixel driving circuit according to claim 7,

the data write sub-circuit includes:

a fourth transistor having a control electrode coupled to a second scan signal terminal and configured to receive the second scan signal, a first electrode coupled to the data signal terminal, and a second electrode coupled to the first terminal of the driving sub-circuit;

the compensation sub-circuit comprises:

a fifth transistor, a control electrode of the fifth transistor being coupled to the second scan signal terminal and configured to receive the second scan signal, a first electrode of the fifth transistor being coupled to the second terminal of the driving sub-circuit, and a second electrode of the fifth transistor being coupled to the control terminal of the driving sub-circuit;

a first plate of the storage capacitor is coupled with the control end of the driving sub-circuit, and a second plate of the storage capacitor is coupled with the first power voltage end;

the first emission control sub-circuit includes:

a sixth transistor having a control electrode coupled to a light emission control signal terminal and configured to receive the light emission control signal, a first electrode coupled to the first power supply voltage terminal, and a second electrode coupled to the first terminal of the driving sub-circuit;

the second emission control sub-circuit includes:

a seventh transistor having a control electrode coupled to a light emission control signal terminal and configured to receive the light emission control signal, a first electrode coupled to the second terminal of the driving sub-circuit, and a second electrode coupled to the first node;

the second reset sub-circuit includes:

an eighth transistor, a control electrode of which is coupled to the first scan signal terminal and configured to receive a first scan signal, a first electrode of which is coupled to the reset voltage terminal, and a second electrode of which is coupled to the control terminal of the driving sub-circuit.

9. A display panel, comprising:

a plurality of pixel drive circuits according to any one of claims 1 to 8 and a plurality of light emitting devices;

wherein one pixel driving circuit is coupled to one light emitting device.

10. A display device, comprising:

the display panel of claim 9.

11. The display device according to claim 10, further comprising:

a control drive circuit;

the control drive circuit is configured to provide a first voltage to a second power supply voltage terminal of the display panel and drive at least one pixel drive circuit in the display panel into a first reset phase; the control drive circuit is further configured to provide a second voltage to a second power supply voltage terminal of the display panel and drive at least one pixel drive circuit in the display panel into a second reset phase;

wherein the first voltage is less than the second voltage.

12. A driving method of a pixel driving circuit is characterized in that,

the pixel drive circuit is the pixel drive circuit of any one of claims 1 to 8;

the driving method includes:

wherein the first voltage is less than the second voltage, and the equivalent resistance of the first path is greater than the equivalent resistance of the second path.