CN113535631B - Data distribution method, device, integrated chip and video image processing system - Google Patents
Data distribution method, device, integrated chip and video image processing system Download PDFInfo
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Abstract
The invention discloses a data distribution method, a data distribution device, an integrated chip and a video image processing system. The method comprises the following steps: determining a working frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and a maximum working frequency threshold of data processing; adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy; and distributing the data to be processed to at least one data stream according to the working parameters. By the technical scheme, the working frequency of the integrated chip is reduced, and the running stability of the video image processing system is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of data communication, in particular to a data distribution method, a data distribution device, an integrated chip and a video image processing system.
Background
Video image processing systems are increasingly being used in numerous fields of equipment inspection/detection, security monitoring, industrial vision, artificial intelligence, and the like. With the continuous improvement of the resolution of the video image processing system, the number of channels (Lane) used on the terminal equipment of the video display is increased, and the Link Rate (Link Rate, LR) is also continuously improved, which has higher requirements on the stability, coordination and the like of the hardware platform of the video image processing system.
Under the scene of greatly increased data processing capacity, the working frequency inside the chip bearing the data is higher due to the fact that the data is too concentrated, the data processing performance of the chip is affected, and the running stability of the video image processing system is reduced.
Disclosure of Invention
The invention provides a data distribution method, a data distribution device, an integrated chip and a video image processing system.
In a first aspect, an embodiment of the present invention provides a data allocation method, including:
Determining a working frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and a maximum working frequency threshold of data processing;
Adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy;
and distributing the data to be processed to at least one data stream according to the working parameters.
Further, before determining the operation frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum operation frequency threshold of the data processing, the method further comprises:
The pixel clock frequency of the video image processing system is calculated based on panel timing parameters, frame rate (FRAME RATE, FR) parameters, and the number of input pixels per clock supported by the video image processing system.
Further, determining an operating frequency adjustment strategy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum operating frequency threshold of data processing, including:
comparing the pixel clock frequency to the maximum operating frequency threshold;
If the pixel clock frequency is greater than the maximum working frequency threshold, selecting a corresponding working frequency adjustment strategy according to a preset strategy threshold so that the pixel clock frequency is less than or equal to the maximum working frequency threshold;
wherein the preset strategy threshold value is at least one, and the working frequency adjustment strategy is at least one.
Further, the method further comprises the following steps:
And if the pixel clock frequency corresponding to the adjusted working parameter is greater than the maximum working frequency threshold, re-determining a working frequency adjustment strategy, and adjusting the working parameter of the video image processing system according to the working frequency adjustment strategy until the pixel clock frequency corresponding to the working parameter is less than or equal to the maximum working frequency threshold, so as to obtain the adjusted working parameter.
Further, the operating frequency adjustment strategy includes at least one of:
adjusting the number of input pixels of each clock;
adjusting the pixel number processed by each clock of the data carrying chip;
adjusting the buffer memory quantity of the data stream;
adjusting the number of channels supported by the video image processing system;
the default or current values of the operating parameters are employed.
Further, the method further comprises the following steps: generating a data allocation instruction, wherein the data allocation instruction comprises:
a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing;
a channel number indication field, configured to indicate the number of channels supported by the video image processing system;
a frame rate indication field for indicating an actual frame rate of the panel;
and the data stream buffer quantity indication field is used for indicating the buffer and output format of the data.
Further, the data allocation instruction further includes:
and a master-slave module definition field for indicating the signaling interaction relationship between the integrated chip and the module of the video image processing system in the data distribution process.
In a second aspect, an embodiment of the present invention provides a data distribution device, including:
the decision module is used for determining the working frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold value of data processing;
The adjusting module is used for adjusting the working parameters of the video image processing system according to the working frequency adjusting strategy;
and the distribution module is used for distributing the effective data to be processed to the data stream according to the working parameters.
In a third aspect, an embodiment of the present invention provides an integrated chip, including:
One or more processors;
a storage means for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the data allocation method as described in the first aspect.
In a fourth aspect, an embodiment of the present invention further provides a video image processing system, including: an embedded control module, an external module, and the integrated chip of claim 9, wherein the integrated chip is connected to the embedded control module and the external module, respectively;
the embedded control module is used for initiating a data distribution request to the integrated chip;
the external module is used for storing the video data to be processed and providing a physical layer interface for displaying the video image data.
The embodiment of the invention provides a data distribution method, a data distribution device, an integrated chip and a video image processing system. The method comprises the following steps: determining a working frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and a maximum working frequency threshold of data processing; adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy; and distributing the data to be processed to at least one data stream according to the working parameters. By the technical scheme, the working frequency of the integrated chip is reduced, and the running stability of the video image processing system is improved.
Drawings
Fig. 1 is a flowchart of a data allocation method according to a first embodiment of the present invention;
Fig. 2 is a flowchart of a data allocation method according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a data distribution device according to a third embodiment of the present invention;
fig. 4 is a schematic hardware structure of an integrated chip according to a fourth embodiment of the present invention;
Fig. 5 is a schematic structural diagram of a video image processing system according to a fifth embodiment of the present invention;
Fig. 6 is a schematic implementation diagram of a video image processing system according to a fifth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a flowchart of a data distribution method according to an embodiment of the present invention, where the embodiment is applicable to a situation of splitting data to be processed in a video image processing system, and in particular, to a video image processing system based on a field programmable gate array (Field Programmable GATE ARRAY, FPGA) and an embedded system, and especially relates to a video image processing system with digital video interface standards (DisplayPort, DP), mobile industry processor interface standards (Mobile Industry Processor Interface, MIPI), high-definition multimedia interface standards (High Definition Multimedia Interface, HDMI) of video electronics standards association (Video Electronics Standards Association, VESA).
The data distribution method of the present embodiment may be performed by a data distribution device, which may be implemented in software and/or hardware and integrated in an integrated chip. In this embodiment, the data to be processed includes video image data, which is a sequence of continuous still images, and the video image processing system is a system that processes video images based on an image processing algorithm. The integrated chip includes, but is not limited to, an FPGA, a micro control unit (Microcontroller Unit, MCU), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), and the like.
As shown in fig. 1, the method specifically includes the following steps:
S110, determining a working frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold of data processing.
Specifically, the pixel clock frequency refers to the frequency of a pixel clock signal, which is related to the working parameters of a display panel in a video image processing system, and the higher the resolution of the display panel is, the higher the frequency of the pixel clock signal is, and the pixel clock signal can instruct the orderly transmission of RGB color signals to the display panel, and ensure the accuracy of data transmission. If the pixel clock frequency in the system is higher than the maximum operating frequency threshold of the chip in the video image processing system, the data processing performance of the chip is reduced, and the running stability of the system is reduced. In this embodiment, by calculating the pixel clock frequency and using the maximum operating frequency threshold of the chip for data processing as the reference for operating frequency optimization, the operating parameters in the system are adjusted according to a certain policy, so that the actual operating pixel clock frequency is lower than the maximum operating frequency threshold, and the pixel clock frequency is kept within a lower range, so as to improve the stability of the system operation.
S120, adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy.
Specifically, the operating parameters may include the number of pixels input in each clock of the video image processing system, the number of pixels processed in each clock inside the chip, the number of buffered data streams, the number of channels, and the like, and the operating frequency adjustment policy may include increasing or decreasing one or more of the above operating parameters, so as to adjust the total number of pixels, the pixel clock frequency, the frame rate, and the like in the system, and reduce the actual pixel clock frequency.
S130, distributing the data to be processed to at least one data stream according to the working parameters.
Specifically, on the premise that the actual pixel clock frequency is reduced below the maximum working frequency threshold, data to be processed is split, including modes of cutting parallel input data stream numbers, cutting parallel output data stream numbers, caching data stream numbers and the like, so that the data processing pressure of a chip is reduced, the performance of the chip is more stable, and the data processing is more reliable.
According to the data distribution method provided by the embodiment of the invention, the pixel clock frequency is calculated, the corresponding maximum working frequency threshold is set, the corresponding working frequency adjustment strategy is selected according to the calculated pixel clock frequency, so that the working parameters are adjusted, the actual working frequency is kept within the maximum working frequency threshold, the data to be processed is split on the basis, the internal actual working frequency of the chip is obviously reduced, and the stability and reliability of the data processed by the system are improved.
Example two
Fig. 2 is a flowchart of a data allocation method according to a second embodiment of the present invention, where the optimization is performed on the basis of the foregoing embodiment, and a specific description is given of an adjustment process of an operation frequency adjustment policy and an operation parameter. It should be noted that technical details not described in detail in this embodiment may be found in any of the above embodiments.
Specifically, as shown in fig. 2, the method specifically includes the following steps:
s210, calculating the pixel clock frequency of the video image processing system according to the panel time sequence parameter, the frame rate parameter and the input pixel number of each clock supported by the video image processing system.
Specifically, the pixel clock frequency is calculated according to panel timing parameters, frame rate parameters and the number of input pixels of each clock supported by the video image processing system. For example, the panel timing parameters include:
Line leading edge (Horizontal Front Porch, HFP): 48;
line Start (Horizontal Start, HS): 32;
Row trailing edge (Horizontal Back Porch, HBP): 80;
Line blanking (HB): hfp+hs+hbp= 48+32+80=160;
Number of row available pixels (Horizontal Active, XDOT): 3840;
total number of rows (HT): hb+xdot=3840+160=4000;
Field front (Vertical Front Porch, HFP): 3, a step of;
Field start (VERTICAL START, HS): 5, a step of;
field trailing edge (Vertical Back Porch, HBP): 54;
vertical blanking (HB): vfp+vs+vbp= 3+5+54=62;
number of field available pixels (VERTICAL ACTIVE, YDOT): 2160;
total field (VT): vb+ YDOT =2160+62=2222;
According to the panel timing parameters, the pixel clock frequency is calculated by the following steps:
Pixel clock frequency = total number of rows HT x total number of fields VT x frame rate/number of pixels per clock input; the pixel clock frequency is also related to the frame rate and the number of pixels per clock input.
Table 1 is a mapping relation table of pixel clock frequency, frame rate, and input pixel number. As shown in table 1, in the case of the panel timing parameter determination, the pixel clock frequency is positively correlated with the frame rate and negatively correlated with the number of pixels in each clock.
Table 1 mapping relation table of pixel clock frequency, frame rate and input pixel number
S220, is the pixel clock frequency greater than the maximum operating frequency threshold? If yes, S230 is executed, and if no, S270 is executed.
Specifically, comparing the calculated pixel clock frequency with a maximum working frequency threshold, and if the pixel clock frequency is greater than the maximum working frequency threshold, selecting a corresponding working frequency adjustment strategy to adjust working parameters; if the pixel clock frequency is not greater than the maximum working frequency threshold, the working parameters can be not adjusted, the stability requirement of the chip can be met by adopting the current working parameters, and the data to be processed can be directly shunted according to the current working parameters.
S230, selecting a corresponding working frequency adjustment strategy according to a preset strategy threshold value so that the pixel clock frequency is smaller than or equal to the maximum working frequency threshold value.
Specifically, when the pixel clock frequency is greater than the maximum operating frequency threshold, a corresponding operating frequency adjustment strategy may be selected according to a preset strategy threshold, where the preset strategy threshold is determined according to the maximum operating frequency threshold, and may be used to measure the magnitude of a frequency value of the pixel clock frequency that exceeds the maximum operating frequency threshold, or to measure the magnitude of the pixel clock frequency. In this embodiment, the preset policy threshold is at least one, and the operating frequency adjustment policy is at least one.
In one embodiment, the operating frequency adjustment strategy includes at least one of: adjusting the number of input pixels of each clock; adjusting the pixel number processed by each clock of the data carrying chip (IP Core); adjusting the buffer memory quantity of the data stream; adjusting the number of channels supported by the video image processing system; the default or current values of the operating parameters are employed.
Table 2 is a mapping relation table of a preset strategy threshold value and a working frequency adjustment strategy. As shown in table 2, for example, different operation frequency adjustment strategies may be determined according to the magnitude of the frequency value of the pixel clock frequency exceeding the maximum operation frequency threshold, and when the frequency value exceeding the maximum operation frequency threshold is greater than the preset strategy threshold 1, the operation frequency adjustment strategy 1 may be adopted; when the frequency value exceeding the maximum operating frequency threshold is smaller than the preset policy threshold 1 but larger than the preset policy threshold 2, the operating frequency adjustment policy 2 or the like may be employed.
Table 2 mapping relation table of preset policy threshold and working frequency adjusting policy
S240, adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy.
For example, if the operating frequency adjustment strategy 1 is selected, the number of input pixels within each clock is adjusted; if the operating frequency adjustment strategy 3 is selected, the number of data stream buffers is adjusted, etc. It should be noted that, a combination of the above strategies may be selected, for example, the number of input pixels in each clock and the number of data stream buffers may be adjusted simultaneously.
S250, the pixel clock frequency corresponding to the operating parameter is less than or equal to the maximum operating frequency threshold? If yes, S260 is executed, and if no, S230 is executed again.
In this embodiment, if the pixel clock frequency corresponding to the adjusted working parameter is greater than the maximum working frequency threshold, the working frequency adjustment policy is redetermined, and the working parameter of the video image processing system is adjusted according to the working frequency adjustment policy until the pixel clock frequency corresponding to the working parameter is less than or equal to the maximum working frequency threshold, so as to obtain the adjusted working parameter.
In an embodiment, in the case that the pixel clock frequency is greater than the maximum operating frequency threshold, different strategies may be adopted successively until the pixel clock frequency falls below the maximum operating frequency threshold. For example, the maximum operating frequency threshold of the data carrying chip (the chip for video image data processing in the integrated chip) is 135MHz, and according to table 1, in the case that the frame rate is 60Hz and the input pixel number/clock is 1, the pixel clock frequency is 533.28Hz, and is greater than the maximum operating frequency threshold, in this case, policy 1 may be adopted first, the input pixel number in each clock is adjusted to 2, and then a new pixel clock frequency is 266.64MHz; the pixel clock frequency is still greater than the maximum working frequency threshold, at this time, policy 2 and policy 3 may be adopted, and in general, when policy 2 is adopted to adjust the number of pixels/clock processed in the chip, the buffered data stream is adjusted along with policy 3, so as to obtain a new pixel clock frequency of 133.32MHz, which is less than the maximum working frequency threshold, and the finally determined working frequency adjustment policy is policy 1+policy 2+policy 3. Similarly, if the pixel clock frequency obtained according to strategy 1+strategy 2+strategy 3 is still greater than the maximum operating frequency threshold, then the operating parameters may continue to be adjusted according to strategy 4 and/or strategy 5.
Table 3 is a mapping table of the pixel clock frequency and the operating frequency adjustment strategy. As shown in table 3, the preset policy threshold may be used to measure the pixel clock frequency, for example, in the case that the frame rate is 30 and the number of input pixels in each clock is 1, the pixel clock frequency is 266.64Hz, and the corresponding operating frequency adjustment policies include policy 1, policy 2, and policy 3, which need to be executed in multiple steps, first, policy 1 is executed, and then policy 2 and policy 3 are executed; when the frame rate is 30 and the number of input pixels in each clock is 2, the pixel clock frequency is 133.32Hz, and the splitting is directly performed according to strategy 5.
Table 3 mapping relationship table of pixel clock frequency and operating frequency adjustment strategy
And S260, distributing the data to be processed to at least one data stream according to the adjusted working parameters. Specifically, the integrated chip finally determines the working parameters of the system, such as the number of input pixels in each clock, the frequency of the pixel clock and the like, according to the finally determined working frequency adjustment strategy, and branches the data to be processed accordingly, so that the actual working frequency of the chip is reduced.
S270, distributing the data to be processed to at least one data stream according to the current working parameters.
Specifically, under the condition that the pixel clock frequency is smaller than the maximum working frequency threshold, the integrated chip does not need to adjust working parameters, and can shunt data to be processed according to the current working parameters such as the input pixel number and the pixel clock frequency in each clock, so that the actual working frequency of the chip is reduced.
In an embodiment, further comprising: generating a data allocation instruction, wherein the data allocation instruction comprises: a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing; a channel number indication field, configured to indicate the number of channels supported by the video image processing system; a frame rate indication field for indicating an actual frame rate of the panel; and the data stream buffer quantity indication field is used for indicating the buffer and output format of the data.
Specifically, the integrated chip determines the maximum working frequency threshold and working parameters in various systems by generating a data distribution instruction according to a preset format, provides a basis for calculating the pixel clock frequency, selecting a working frequency adjustment strategy and adjusting the working parameters, performs signaling interaction between modules in the video image processing system according to the format, improves the transmission efficiency of data streams, and ensures the stability of data stream transmission.
In an embodiment, the data allocation instructions further comprise: and a master-slave module definition field for indicating the signaling interaction relationship between the integrated chip and the module of the video image processing system in the data distribution process.
Specifically, the master-slave module definition field defines that the modules of the video image processing system include a master module and a slave module, where the master module and the slave module are defined according to an initiator and a receiver of a command, and master-slave relationships between modules corresponding to different signaling interaction processes may be different. For example, the embedded control module may initiate a data allocation signaling integration chip as a master module to an integration chip (such as an FPGA) as a slave module to receive signaling and execute; the integrated chip may also act as a master module, signaling is initiated to the embedded control module, which is then the slave module. For another example, the data distribution signaling of the integrated chip is forwarded to the slave module from the master module among the modules in the integrated chip, the slave module completes data distribution and feeds back to the master module, the master module feeds back to the embedded control module, and the like, in the process, the data distribution signaling and the feedback information are transmitted according to the master-slave structure among the modules without jump transmission, and each group of modules with master-slave relationship carries out layered forwarding and interaction of signaling in respective links, so that the organization structure of the system is standardized, and the reliability and efficiency of interaction are improved. The data allocation instruction may further include a feedback field, configured to define a module state after the data allocation signaling interaction is completed, where the module state includes an ACK state and a NACK state, and complete a confirmation operation of the signaling interaction.
According to the data distribution method provided by the second embodiment of the invention, optimization is performed on the basis of the second embodiment, and under the condition that the pixel clock frequency is greater than the maximum working frequency threshold, corresponding working frequency adjustment strategies can be selected according to the preset strategy threshold, or different strategies are adopted in sequence according to the set sequence until the pixel clock frequency is reduced below the maximum working frequency threshold, so that the flexibility and reliability of working frequency adjustment are improved; splitting the data to be processed according to the adjusted working parameters, and obviously reducing the working frequency of the chip; the signaling interaction among the modules of the video image processing system is realized by generating a data distribution instruction according to a preset format and according to a master-slave structure relationship, so that the transmission efficiency of the data stream is improved, and the stability of the data stream transmission is ensured.
Example III
Fig. 3 is a schematic structural diagram of a data distribution device according to a third embodiment of the present invention. As shown in fig. 3, the data distribution device provided in this embodiment includes:
A decision module 310, configured to determine an operating frequency adjustment policy of the video image processing system according to a pixel clock frequency of the video image processing system and a maximum operating frequency threshold of data processing;
an adjusting module 320, configured to adjust an operating parameter of the video image processing system according to the operating frequency adjustment policy;
And the allocation module 330 is configured to allocate the valid data to be processed to a data stream according to the working parameter.
According to the data distribution device provided by the third embodiment of the invention, the working parameters are adjusted and data are distributed according to the pixel clock frequency and the maximum working frequency threshold value of data processing, so that the actual working frequency is lower than the maximum working frequency threshold value, the working frequency of an integrated chip is reduced, and the running stability of a video image processing system is improved.
On the basis of the above embodiment, the method further comprises:
And the calculating module is used for calculating the pixel clock frequency of the video image processing system according to the panel time sequence parameter, the frame rate parameter and the input pixel number of each clock supported by the video image processing system.
On the basis of the above embodiment, the decision module 310 includes:
A comparing unit for comparing the pixel clock frequency with the maximum operating frequency threshold;
the decision unit is used for selecting a corresponding working frequency adjustment strategy according to a preset strategy threshold value if the pixel clock frequency is larger than the maximum working frequency threshold value so that the pixel clock frequency is smaller than or equal to the maximum working frequency threshold value;
wherein the preset strategy threshold value is at least one, and the working frequency adjustment strategy is at least one.
Further, the method further comprises the following steps:
And the readjusting module is used for determining a working frequency adjustment strategy again and adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy if the pixel clock frequency corresponding to the adjusted working parameters is larger than the maximum working frequency threshold value until the pixel clock frequency corresponding to the working parameters is smaller than or equal to the maximum working frequency threshold value, so as to obtain the adjusted working parameters.
Further, the operating frequency adjustment strategy includes at least one of:
adjusting the number of input pixels of each clock;
adjusting the pixel number processed by each clock of the data carrying chip;
adjusting the buffer memory quantity of the data stream;
adjusting the number of channels supported by the video image processing system;
the default or current values of the operating parameters are employed.
Further, the method further comprises the following steps:
The generating module is used for generating a data distribution instruction, wherein the data distribution instruction comprises:
a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing;
a channel number indication field, configured to indicate the number of channels supported by the video image processing system;
a frame rate indication field for indicating an actual frame rate of the panel;
and the data stream buffer quantity indication field is used for indicating the buffer and output format of the data.
Further, the data allocation instruction further includes:
and a master-slave module definition field for indicating the signaling interaction relationship between the integrated chip and the module of the video image processing system in the data distribution process.
The data distribution device provided by the third embodiment of the present invention can be used to execute the data distribution method provided by any of the above embodiments, and has corresponding functions and beneficial effects.
Example IV
Fig. 4 is a schematic hardware structure of an integrated chip according to a fourth embodiment of the present invention. The integrated chip may be a field programmable gate array (Field Programmable GATE ARRAY, FPGA), a micro-control unit (Microcontroller Unit, MCU), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), or the like. As shown in fig. 4, an integrated chip provided in this embodiment includes: a processor 410 and a storage 420. The processor in the integrated chip may be one or more, for example, a processor 410 in fig. 4, and the processor 410 and the memory device 420 in the integrated chip may be connected by a bus or other means, for example, by a bus connection in fig. 4.
The one or more programs are executed by the one or more processors 410 to cause the one or more processors to implement the data allocation method as described in any of the above embodiments.
The storage 420 in the integrated chip is used as a computer readable storage medium, and may be used to store one or more programs, such as a software program, a computer executable program, and modules, such as program instructions/modules corresponding to the data distribution method in the embodiment of the present invention (for example, the modules in the data distribution device shown in fig. 3 include the decision module 310, the adjustment module 320, and the distribution module 330). The processor 410 executes various functional applications of the integrated chip and data processing by running software programs, instructions and modules stored in the storage 420, i.e. implements the data distribution method in the above-described method embodiments.
The storage device 420 mainly includes a storage program area and a storage data area, wherein the storage program area can store an operating system and at least one application program required by functions; the storage data area may store data created according to the use of the integrated chip, etc. (e.g., the operating parameters, the operating frequency adjustment policy, etc. in the above-described embodiment). In addition, the storage 420 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, the storage 420 may further include memory remotely located with respect to the processor 410, which may be connected to the integrated chip through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
And, when one or more programs included in the above integrated chip are executed by the one or more processors 410, the following operations are performed: determining a working frequency adjustment strategy of the video image processing system according to the pixel clock frequency of the video image processing system and a maximum working frequency threshold of data processing; adjusting the working parameters of the video image processing system according to the working frequency adjustment strategy; and distributing the data to be processed to at least one data stream according to the working parameters.
The integrated chip provided in this embodiment and the data distribution method provided in the foregoing embodiments belong to the same inventive concept, and technical details not described in detail in this embodiment can be found in any of the foregoing embodiments, and this embodiment has the same advantages as those of executing the data distribution method.
Example five
The fifth embodiment of the invention provides a video image processing system. Fig. 5 is a schematic structural diagram of a video image processing system according to a fifth embodiment of the present invention. As shown in fig. 5, the system includes an embedded control module 10, an external module 30, and an integrated chip 20, the integrated chip 20 being connected to the embedded control module 10 and the external module 30, respectively; wherein, the embedded control module 10 is used for initiating a data distribution request to the integrated chip 20; the external module 30 is used to store video data to be processed and provide a physical layer interface for video image data display.
The embedded control module 10 may employ any embedded chip and system for initiating a data allocation request, and may also be used for requesting read/write of register data, requesting to enable/disable a video display unit or module, requesting peripheral control or requesting to modify a parameter setting of a video display module, etc. The integrated chip 20 is used for determining an operating frequency adjustment policy according to a clock pixel frequency, adjusting an operating parameter and distributing data to be processed, and is also used for implementing or executing operations requiring a large amount of data processing and low round trip delay (latency), such as storage control, peripheral control, video interface IP core implementation, and the like.
Fig. 6 is a schematic implementation diagram of a video image processing system according to a fifth embodiment of the present invention. As shown in fig. 6, the external module 30 includes an external storage module, a flash memory module, a peripheral module, and a video interface physical layer implementation module, where the external storage module is used to store an original data stream of a video or an image to be displayed in the system. For example, the external storage module may employ a storage medium such as a Flash memory (e.g., NAND FLASH, nand Flash memory), a Solid state drive (Solid STATE DRIVE, SSD), or the like. In the case where a large amount of data processing and low round trip delay (latency) signaling is required inside the integrated chip 20, a fast and low latency physical device, such as a Double-rate synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR) or the like, may be used for temporarily storing data in order to further reduce latency, the peripheral module may be a General-purpose input/output (General-purpose input/output, GPIO), universal asynchronous Receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), universal serial bus (Universal Serial Bus, USB), network Port, etc. the video interface physical layer implementation module is used to drive the physical layer implementation of the Display module, e.g., the Port physical layer (PHYSICAL LAYER, PHY) of the transceiver Transmitter (TX/RX) of the Display interface (Display Port, DP), the Port physical layer (DISPLAY SERIAL INTERFACE PHYSICAL LAYER, D-PHY) of the serial Display interface of the mobile industry processor interface (Mobile Industry Processor Interface, MIPI), etc.
As shown in fig. 6, the integrated chip 20 may specifically include one or more of the following: the system comprises a bus interaction module, an MCU, a video stream preprocessing unit, a video data stream transmission control module, a clock control module, an embedded soft core control module, a bus controller module, a video pattern processing module, an internal storage controller module, a peripheral control module, a display clock generator module, a video time sequence controller module and a video interface IP core module.
The bus interaction module is used for selecting or deciding all modules connected with the bus interaction module; the MCU video stream preprocessing unit is used for preprocessing and converting the video data stream input from the external storage module according to the format and the parameter type set by the system so as to facilitate the subsequent processing; the video data stream transmission control module is used for controlling the time sequence and parameters of the data stream after the data stream pretreatment and conversion; the clock control module is responsible for generating and controlling a global clock in the video or image processing process; the embedded soft core control module is a control core of the FPGA module and is used for realizing core functions such as time sequence control, parameter configuration, physical process realization and the like of all modules in the FPGA module, and soft processors (MicroBlaze) of Xilinx and the like can be adopted; the bus controller module is used for controlling all modules connected with the bus interaction module; the video pattern processing module is in charge of adapting to the mode conversion and time sequence control of the video image data stream corresponding to the video interface IP core module; the internal memory controller module is used for realizing the control of the quick memory module, including the writing/reading of data stream, frame control and the like; the peripheral control module is used for controlling all peripheral modules, including starting/closing of peripheral, working mode control and the like; the display clock generator module is used for controlling the time sequence of all the modules which are connected with the video interface IP core module and the video interface physical layer; the video time sequence controller module is responsible for data conversion, time sequence control and other processes in the process of transmitting the data input by the video pattern processing module to the video interface IP core module. It should be noted that, there may be a master-slave relationship between the plurality of modules within the integrated chip 20 and between the embedded control module 10 and the external module 30.
The video image processing system of the embodiment can establish a perfect signaling interaction mechanism by defining a preset message structure and format, each group of modules with master-slave relation carries out signaling forwarding and interaction in respective links, the interaction structure and specification of each module are defined, organized and accurate signaling interaction between the master module and the slave module is realized, the data stream conversion is completed under the conditions of ensuring that a hardware system and a platform are seamless, smooth and free from dead halt and the like, meanwhile, the system is ensured to have minimum effective system time delay under the premise of event driving, and the reliability and efficiency of interaction are improved.
The video image processing system provided in the fifth embodiment may be used to execute the data distribution method provided in any of the foregoing embodiments, and has corresponding functions and beneficial effects.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. A data distribution method applied to an integrated chip of a video image processing system, comprising:
Adjusting the working frequency of a video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold of data processing;
Adjusting the working parameters of the video image processing system according to the method for adjusting the working frequency;
distributing the data to be processed to at least one data stream according to the working parameters;
Wherein the adjusting the working frequency of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold of the data processing comprises:
if the pixel clock frequency is greater than the maximum working frequency threshold, selecting a corresponding working frequency adjustment method according to a preset strategy threshold so that the pixel clock frequency is less than or equal to the maximum working frequency threshold;
the preset strategy threshold is determined according to the maximum working frequency threshold, and at least one of the preset strategy thresholds is used for determining the maximum working frequency threshold; the working frequency adjusting method is at least one.
2. The method of claim 1, further comprising, prior to adjusting the operating frequency of the video image processing system based on the pixel clock frequency of the video image processing system and a maximum operating frequency threshold for data processing:
and calculating the pixel clock frequency of the video image processing system according to the panel time sequence parameter, the frame rate parameter and the input pixel number of each clock supported by the video image processing system.
3. The method as recited in claim 1, further comprising:
And if the pixel clock frequency corresponding to the adjusted working parameter is greater than the maximum working frequency threshold, re-determining a working frequency adjusting method, and adjusting the working parameter of the video image processing system according to the working frequency adjusting method until the pixel clock frequency corresponding to the working parameter is less than or equal to the maximum working frequency threshold, so as to obtain the adjusted working parameter.
4. The method of claim 1, wherein the method of adjusting the operating frequency comprises at least one of:
adjusting the number of input pixels of each clock;
Adjusting the pixel number processed by each clock of the integrated chip;
adjusting the buffer memory quantity of the data stream;
adjusting the number of channels supported by the video image processing system;
the default or current values of the operating parameters are employed.
5. The method of any one of claims 1-4, further comprising: generating a data allocation instruction, wherein the data allocation instruction comprises:
a maximum operating frequency threshold indication field for indicating a maximum operating frequency threshold for data processing;
a channel number indication field, configured to indicate the number of channels supported by the video image processing system;
a frame rate indication field for indicating an actual frame rate of the panel;
and the data stream buffer quantity indication field is used for indicating the buffer and output format of the data.
6. The method of claim 5, wherein the data allocation instruction further comprises:
and a master-slave module definition field for indicating the signaling interaction relationship between the integrated chip and the module of the video image processing system in the data distribution process.
7. A data distribution device, comprising:
the decision module is used for adjusting the working frequency of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold value of data processing;
The adjusting module is used for adjusting the working parameters of the video image processing system according to the method of adjusting the working frequency;
the distribution module is used for distributing the data to be processed to at least one data stream according to the working parameters;
Wherein the adjusting the working frequency of the video image processing system according to the pixel clock frequency of the video image processing system and the maximum working frequency threshold of the data processing comprises:
if the pixel clock frequency is greater than the maximum working frequency threshold, selecting a corresponding working frequency adjustment method according to a preset strategy threshold so that the pixel clock frequency is less than or equal to the maximum working frequency threshold;
the preset strategy threshold is determined according to the maximum working frequency threshold, and at least one of the preset strategy thresholds is used for determining the maximum working frequency threshold; the working frequency adjusting method is at least one.
8. An integrated chip, comprising:
One or more processors;
a storage means for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the data allocation method of any of claims 1-6.
9. A video image processing system, comprising: an embedded control module, an external module, and the integrated chip of claim 8, wherein the integrated chip is connected to the embedded control module and the external module, respectively;
the embedded control module is used for initiating a data distribution request to the integrated chip;
the external module is used for storing the video data to be processed and providing a physical layer interface for displaying the video image data.
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| CN1697514A (en) * | 2005-05-31 | 2005-11-16 | 四川长虹电器股份有限公司 | Video signal processing method in high definition format |
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