CN113496874B

CN113496874B - Semiconductor structure and forming method thereof

Info

Publication number: CN113496874B
Application number: CN202010252120.6A
Authority: CN
Inventors: 甘露; 郑春生; 师兰芳; 张文广; 张华�
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-04-01
Filing date: 2020-04-01
Publication date: 2024-04-19
Anticipated expiration: 2040-04-01
Also published as: CN113496874A

Abstract

A semiconductor structure and a method for forming the semiconductor structure, wherein the method comprises the following steps: providing a layer to be etched; forming an initial first flat layer on the layer to be etched, wherein the initial first flat layer has a first thickness; forming an initial first mask layer on the initial first planar layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness; and forming a second mask layer on the initial first mask layer, wherein the second mask layer exposes part of the surface of the initial first mask layer, the second mask layer has a third thickness, and the third thickness is smaller than the first thickness. Thus, the performance of the semiconductor device is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.

Background

With the continuous progress of semiconductor integrated circuit manufacturing technology, performance is continuously improved and simultaneously miniaturization and microminiaturization of devices are also accompanied. In more advanced processes, it is desirable to implement as many devices as possible in as small a region as possible.

In an advanced photolithography process, extreme Ultraviolet (EUV) light may be used as a light source, and the wavelength of the EUV light is short, so that a photolithography pattern with a smaller critical dimension can be formed, thereby enabling more devices to be implemented in a smaller area and improving the integration level of semiconductor devices.

However, the performance of semiconductor devices is still in need of improvement.

Disclosure of Invention

The invention provides a semiconductor structure and a method for forming the semiconductor structure to improve the performance of a semiconductor device.

In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a layer to be etched; an initial first planar layer on the layer to be etched, the initial first planar layer having a first thickness; an initial first mask layer on the initial first planar layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness; and the second mask layer is positioned on the initial first mask layer, part of the surface of the initial first mask layer is exposed by the second mask layer, the second mask layer has a third thickness, and the third thickness is smaller than the first thickness.

Optionally, the material of the initial first planar layer comprises a carbon-containing organic material.

Optionally, the material of the initial first mask layer includes a carbon-containing organic material.

Optionally, the first thickness ranges from 150 nm to 300 nm.

Optionally, the second thickness ranges from 30 nm to 100 nm.

Optionally, the third thickness is above 12 nanometers.

Optionally, the method further comprises: an initial first stop layer located between the initial first planarization layer and the initial first mask layer.

Optionally, the initial first stop layer has a fourth thickness, the fourth thickness being less than the second thickness.

Optionally, the material of the initial first stop layer includes a metal oxide.

Optionally, the fourth thickness is in a range of

Optionally, the material of the initial first stop layer comprises amorphous silicon.

Optionally, the fourth thickness ranges from 5 nm to 10nm.

Optionally, the material of the second mask layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a layer to be etched; forming an initial first flat layer on the layer to be etched, wherein the initial first flat layer has a first thickness; forming an initial first mask layer on the initial first planar layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness; and forming a second mask layer on the initial first mask layer, wherein the second mask layer exposes part of the surface of the initial first mask layer, the second mask layer has a third thickness, and the third thickness is smaller than the first thickness.

Optionally, the process of forming the initial first mask layer includes a deposition process.

Optionally, the process of forming the initial first planar layer includes a spin-coating process.

Optionally, the process parameters of the spin-coating process include: the film forming temperature is below 400 ℃.

Optionally, the method for forming the second mask layer includes: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein the photoresist pattern layer exposes part of the surface of the second mask material layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer is exposed.

Optionally, the method further comprises: and etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first flat layer is exposed so as to form a first mask layer.

Optionally, the method further comprises: etching the initial first flat layer by taking the first mask layer as a mask until the surface of the layer to be etched is exposed, so as to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

Optionally, the method further comprises: an initial first stop layer is formed on the initial first planar layer surface prior to forming the initial first mask layer.

Optionally, the method further comprises: etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first stop layer is exposed so as to form a first mask layer; and etching the initial first stop layer by taking the first mask layer as a mask until the surface of the initial first flat layer is exposed so as to form a first stop layer.

Optionally, the method further comprises: etching the initial first flat layer by taking the first stop layer as a mask until the surface of the layer to be etched is exposed, so as to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

Optionally, the method further comprises: and before etching the initial first stop layer, performing first thinning etching on the side wall of the first mask layer for more than 1 time.

Optionally, the method further comprises: and before etching the initial first flat layer, performing second thinning etching on the side wall of the first stop layer for more than 1 time.

Optionally, the method further comprises: removing part of the initial first stop layer on the surface of the initial first flat layer after forming the initial first stop layer so as to form a first stop layer; after the first stop layer is formed, forming a mask side wall on the surface of the side wall of the first stop layer; removing the first stop layer after forming the mask side wall; and after the first stop layer is removed, etching the initial first flat layer by taking the mask side wall as a mask until the surface of the layer to be etched is exposed, so as to form a first flat layer.

Optionally, the method further comprises: and etching the layer to be etched by taking the first flat layer as a mask.

Optionally, the method for forming the first stop layer includes: removing part of the initial first mask layer on the surface of the initial first stop layer to form a first mask layer; forming a first side wall on the side wall surface of the first mask layer; after the first side wall is formed, removing the first mask layer; and after the first mask layer is removed, etching the initial first stop layer by taking the first side wall as a mask until the surface of the initial first flat layer is exposed.

Optionally, the method for forming the first mask layer includes: forming a second side wall on the side wall surface of the second mask layer after forming the second mask layer; removing the second mask layer after the second side wall is formed; and after the second mask layer is removed, etching the initial first mask layer by taking the second side wall as a mask until the surface of the initial first stop layer is exposed.

Optionally, the method for forming the second mask layer includes: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein the photoresist pattern layer exposes part of the surface of the second mask material layer; forming a third side wall on the side wall of the photoresist pattern layer; removing the photoresist pattern layer after the third side wall is formed; and after the photoresist pattern layer is removed, etching the second mask material layer by taking the third side wall as a mask until the surface of the initial first mask layer is exposed.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

In the semiconductor structure provided by the technical scheme of the invention, the initial first flat layer is used for repairing the surface of the layer to be etched. The initial first mask layer is used for forming a first mask layer, and the second mask layer and the first mask layer are used for transferring the photoetching patterns of the photoresist layer so as to improve the stability of the photoetching patterns. In the photoetching process with extreme ultraviolet light as a light source, the photoresist layer is thinner. Because the third thickness is smaller than the first thickness, when the photoresist layer is used as a mask to etch the material layer of the second mask layer, the thinner material layer of the second mask layer can form the second mask layer before the photoresist layer is completely worn, so that transfer of a photoetching pattern under an extreme ultraviolet photoetching process is realized. Because the second thickness is smaller than the first thickness, on one hand, when the second mask layer is used as a mask for etching the initial first mask layer, the thinner initial first mask layer can form the first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first flat layer can enable the semiconductor structure to have higher flatness, and when the photoetching patterns are transferred to the layer to be etched through the initial first flat layer, the initial first mask layer and the second mask layer, the pattern precision in the transfer process is improved. In summary, by the semiconductor structure, the photolithography process of extreme ultraviolet light is processed to improve the integration level, and meanwhile, the pattern precision of the photolithography pattern in the transferring process can be increased to improve the performance of the semiconductor device.

Further, since the semiconductor structure further includes the initial first stop layer located between the initial first planarization layer and the initial first mask layer, on one hand, when the initial first mask layer is etched, the initial first stop layer can protect the initial first planarization layer, and reduce the influence of the etching process for etching the initial first mask layer on the initial first planarization layer, so that the accuracy of the lithography pattern transferred to the initial first planarization layer can be improved; on the other hand, when it is detected that the accuracy of the photolithography pattern transferred to the initial first mask layer is poor, when the initial first mask layer is removed and a new initial first mask layer is formed again, the influence of the process of removing the initial first mask layer on the initial first planarization layer can be reduced by the initial first stop layer, thereby improving the performance of the semiconductor device.

Further, since the initial first stop layer has a fourth thickness, and the fourth thickness is smaller than the second thickness, the initial first stop layer having a smaller thickness forms the first stop layer, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase a process window of an etching process for etching the initial first flat layer, thereby improving the performance of the semiconductor device.

Correspondingly, in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial first flat layer is formed to repair the surface of the layer to be etched. The initial first mask layer is used for forming a first mask layer subsequently, and the first mask layer and the second mask layer are used for transferring the photoetching patterns of the photoresist layer so as to improve the stability of the photoetching patterns. In the photoetching process with extreme ultraviolet light as a light source, the photoresist layer is thinner. Because the third thickness is smaller than the first thickness, when the photoresist layer is used as a mask to etch the material layer of the second mask layer, the thinner material layer of the second mask layer can form the second mask layer before the photoresist layer is completely worn, so that transfer of a photoetching pattern under an extreme ultraviolet photoetching process is realized. Because the second thickness is smaller than the first thickness, on one hand, when the initial first mask layer is etched by taking the second mask layer as a mask, the thinner initial first mask layer can form the first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first flat layer can enable the semiconductor structure to have higher flatness, and when the photoetching patterns are transferred to the layer to be etched through the initial first flat layer, the initial first mask layer and the second mask layer, the pattern precision in the transfer process is improved. In summary, by the method for forming a semiconductor structure, the photolithography process of extreme ultraviolet light is dealt with to improve the integration level, and meanwhile, the pattern precision of a photolithography pattern in the transfer process can be increased to improve the performance of a semiconductor device.

Further, since the process of forming the initial first mask layer includes a deposition process, the deposition process has the process characteristics that the defect number of the formed material layer is small and the defect number is less affected by the thickness of the material layer, the defect in the initial first mask layer can be reduced when the initial first mask layer with small thickness is formed by adopting the deposition process, and thus, the pattern precision of the photoetching pattern formed by the initial first mask layer can be improved.

Furthermore, the spin coating process has good filling performance, and because the process for forming the initial first flat layer comprises the spin coating process, the uneven part on the layer to be etched can be filled better through the spin coating process, so that the flatness of the initial first flat layer is further improved.

Further, since the second thinning etching is performed on the side wall of the first stop layer, the critical dimension of the pattern of the first stop layer can be reduced, and thus, a pattern with smaller critical dimension can be formed on the layer to be etched, so that the design requirement with smaller critical dimension can be met, and the integration level of the semiconductor device is further improved.

Drawings

FIGS. 1-2 are schematic cross-sectional views of steps of a method for forming a semiconductor structure;

Fig. 3 to 9 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

Fig. 10 to 16 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention;

Fig. 17 to 22 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, the performance of semiconductor devices is still in need of improvement. The analysis will now be described with reference to specific examples.

Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 to 2 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure.

Referring to fig. 1, a layer to be etched 10 is provided; forming an initial planarization layer 20 on the surface of the layer to be etched 10 by adopting a spin coating process; forming a mask material layer 30 on the surface of the initial planarization layer 20; a photoresist layer 40 is formed on the surface of the mask material layer 30, and a portion of the surface of the mask material layer 30 is exposed by the photoresist layer 40.

The method of forming the photoresist layer 40 includes: forming a photoresist material layer (not shown) on the surface of the mask material layer 30; and exposing and developing the photoresist material layer. The light source of the exposure process is extreme ultraviolet light.

Referring to fig. 2, the photoresist layer 40 is used as a mask to etch the mask material layer 30 until the surface of the initial planarization layer 20 is exposed, so as to form a mask layer 31; after forming the mask layer 31, removing the photoresist layer 40; after removing the photoresist layer 40, etching the initial planarization layer 20 by using the mask layer 31 as a mask until the surface of the layer to be etched 10 is exposed, so as to form a planarization layer 21; after forming the planarization layer 21, the layer to be etched 10 is etched using the planarization layer 21 as a mask.

In the above embodiment, on the one hand, since the light source for exposing the photoresist material layer is extreme ultraviolet light, the light wave of the extreme ultraviolet light is short, and therefore, the photoresist layer 40 having the photolithography pattern with smaller critical dimension and higher integration level can be formed, thereby improving the integration level of the semiconductor device. On the other hand, since the initial planarization layer 20 is formed by using a spin coating process with good filling performance, the surface flatness of the semiconductor structure can be improved, and the interface state of the layer to be etched 10 can be improved.

To meet the extreme ultraviolet lithography process requirements, a photoresist layer 40 having a smaller thickness M3 (as shown in fig. 1) is required. In order to avoid the problem of over-etching caused by the smaller thickness M3, it is necessary to reduce the thickness M2 of the mask material layer 30 (shown in fig. 1) and the thickness M1 of the initial planarization layer 20 (shown in fig. 1).

However, since the initial planarization layer 20 is formed using the spin coating process, the number of defects in the formed initial planarization layer 20 is greatly affected by the thickness M1, i.e., the reduction of the thickness M1, which is affected by the spin coating process, may result in an increase of defects in the initial planarization layer 20, thereby resulting in poor performance of the subsequently formed semiconductor device.

In order to solve the technical problem, the embodiment of the invention provides a method for forming a semiconductor structure, which is characterized in that an initial first mask layer with smaller thickness is formed between an initial first flat layer and a second mask layer, so that the second mask layer with smaller thickness can be corresponding to the initial first flat layer without reducing the thickness of the initial first flat layer, the flatness of the surface of the semiconductor structure is improved, the interface state of the surface of a layer to be etched is improved, the defect of the initial first flat layer can be reduced, and the requirement of the lithography process of extreme ultraviolet light can be met. Thus, the performance of the semiconductor device is improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 9 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 3, a layer to be etched 100 is provided.

The material of the layer to be etched 100 includes a semiconductor material.

In this embodiment, the material of the layer to be etched 100 includes silicon.

In other embodiments, the material of the layer to be etched includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

In this embodiment, the layer to be etched 100 has a device layer (not shown) therein. The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may further include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

Referring to fig. 4, an initial first planarization layer 110 is formed on the layer to be etched 100.

The initial first planarization layer 110 is used to repair the surface of the layer to be etched 100, and to provide a material for forming the first planarization layer subsequently.

The initial first planarization layer 110 has a first thickness H1 in a direction perpendicular to the surface of the layer to be etched 100.

In this embodiment, the process of forming the initial first planarization layer 110 includes a spin-coating process.

The reason for forming the initial first planarization layer 110 using the spin-coating process is that: the spin coating process has better filling performance, so that the initial first flat layer 110 formed by the spin coating process can better fill the uneven part on the layer to be etched 100, thereby improving the interface state of the initial layer to be etched 100, and the formed initial first flat layer 110 has higher flatness, so as to improve the graphic precision of the semiconductor structure and improve the performance of the semiconductor structure.

In this embodiment, the first thickness H1 ranges from 150 nm to 300 nm.

The reason for selecting the range of the first thickness H1 is that: if the first thickness H1 is too large, on the one hand, the process time and material cost for forming the semiconductor structure may be increased. On the other hand, when the initial first flat layer 110 is etched later to form the first flat layer, the pattern of the first flat layer has a larger aspect ratio, so that the reaction gas in the etching process is difficult to reach the portion close to the initial first flat layer of the layer to be etched 100, which not only increases the difficulty of the etching process, but also causes the formed first flat layer to have a poorer morphology. Since the initial first planarization layer 110 is formed by using the spin coating process, the number of defects in the initial first planarization layer 110 is related to the size of the first thickness H1, and the smaller the first thickness H1 is, the more the number of defects is, and thus, if the first thickness H1 is too small, the number of defects in the initial first planarization layer 110 is too large, thereby resulting in poor performance of the semiconductor device. Therefore, by making the first thickness H1 in the range of 150 nm to 300 nm, the process time and the material cost for forming the semiconductor structure can be within a reasonable range, and not only can the difficulty of the etching process for subsequently etching the initial first flat layer 110 be reduced, but also the first flat layer with better morphology can be formed, and meanwhile, the number of defects in the initial first flat layer 110 can be reduced, so that the performance of the semiconductor device can be improved.

In this embodiment, the process parameters of the spin-coating process include: the film forming temperature is below 400 ℃. The film forming temperature is high, so that the influence of the temperature on the initial first flat layer 110 in the subsequent process of forming the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the material of the initial first planarization layer 110 includes a carbon-containing organic material.

Referring to fig. 5, an initial first stop layer 120 is formed on the surface of the initial first planarization layer 110.

The initial first stop layer 120 provides material for the subsequent formation of the first stop layer.

Subsequently, an initial first mask layer is formed on the surface of the initial first stop layer, and the initial first stop layer 120 is used as an etching stop layer for subsequently etching the initial first mask layer.

Since the initial first stop layer 120 is formed, on the one hand, when the initial first mask layer is etched, the initial first stop layer 120 can protect the initial first flat layer 110, and reduce the influence of the etching process for etching the initial first mask layer on the initial first flat layer 110, so that the accuracy of the lithography pattern transferred to the initial first flat layer 110 can be improved; on the other hand, when it is detected that the accuracy of the photolithography pattern transferred to the initial first mask layer is poor, the influence of the process of removing the initial first mask layer on the initial first planarization layer 110 can be reduced through the initial first stop layer when removing the initial first mask layer and re-forming a new initial first mask layer, thereby improving the performance of the semiconductor device, and the initial first mask layer is removed without removing the initial first planarization layer 110, simplifying the formation process of the semiconductor structure, reducing the formation time of the semiconductor structure, and improving the efficiency of manufacturing the semiconductor structure.

In this embodiment, the material of the initial first stop layer 120 includes a metal oxide.

Since the subsequent etching process for etching the initial first mask layer has a larger selective etching ratio to the material of the initial first mask layer and the material of the initial first stop layer 120, the influence of the etching process for etching the initial first mask layer on the initial first stop layer 120 can be reduced, and the accuracy of the transferred lithography pattern can be further improved.

In this embodiment, the initial first stop layer 120 has a fourth thickness H4 in a direction perpendicular to the surface of the layer to be etched 100.

In the present embodiment, the fourth thickness H4 is in the range of

The reason why the range of the fourth thickness H4 is selected is that if the fourth thickness H4 is too large, the process time and material cost for forming the semiconductor structure are increased, and when the first stop layer is used as a mask, the mask pattern has a large aspect ratio, reducing a process window of the etching process for etching the initial first planarization layer 110; if the fourth thickness H4 is too small, the function of the initial first stop layer 120 as an etch stop layer is affected. Therefore, with the above-described fourth thickness H4 range of the initial first stop layer 120, the pattern of the first stop layer as a mask can be made to have a smaller aspect ratio while ensuring a function as an etch stop layer, thereby increasing a process window of an etching process for etching the initial first planarization layer 110, improving the performance of the semiconductor device, and enabling reduction in thickness of the semiconductor structure, and reduction in process time and material cost for forming the semiconductor structure.

In other embodiments, the initial first stop layer is not formed.

Referring to fig. 6, an initial first mask layer 130 is formed on the initial first planarization layer 110.

Specifically, in this embodiment, forming the initial first mask layer 130 on the initial first planarization layer 110 means that the initial first mask layer 130 is formed on the surface of the initial first stop layer 120.

In other embodiments, since the initial first stop layer is not formed, an initial first mask layer is formed on the initial first planar layer surface.

The initial first mask layer 130 provides material for the subsequent formation of the first mask layer.

In this embodiment, in a direction perpendicular to the surface of the layer to be etched 100, the initial first mask layer 130 has a second thickness H2, the second thickness H2 is smaller than the first thickness H1, and the fourth thickness H4 is smaller than the second thickness H2.

Because the second thickness H2 is smaller than the first thickness H1, on one hand, when a second mask layer is formed subsequently and the initial first mask layer 130 is etched by taking the second mask layer as a mask, the thinner initial first mask layer 130 can form the first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first planarization layer 110 can enable the semiconductor structure to have higher flatness, which is beneficial to improving the pattern accuracy in the transfer process when transferring the photolithography pattern to the layer to be etched 100 by using the initial first planarization layer 110, the initial first mask layer 130 and the second mask layer.

Since the fourth thickness H4 is smaller than the second thickness H2, the first stop layer has a smaller thickness, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase a process window of an etching process for etching the initial first planarization layer 110, thereby improving the performance of the semiconductor device.

In this embodiment, the second thickness H2 ranges from 30 nm to 100 nm.

The reason for selecting the range of the second thickness H2 is that if the second thickness H2 is too large, the first mask layer cannot be formed before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized, and if the second thickness H2 is too small, the process difficulty of forming the initial first mask layer is increased, so that the selection of the second thickness H2 can realize the transfer of the lithography pattern under the extreme ultraviolet process, and meanwhile, the process difficulty of forming the initial first mask layer is reduced.

In this embodiment, the process of forming the initial first mask layer 130 includes a deposition process.

The reason why the first mask layer 130 is formed using the deposition process is that the deposition process has a process characteristic in that the number of defects of the formed material layer is small and the number of defects is less affected by the thickness of the material layer. Therefore, by forming the initial first mask layer 130 using the deposition process, it is possible to cope with the transfer of the photolithography pattern under the extreme ultraviolet process while forming the initial first mask layer 130 having the smaller second thickness H2, and at the same time, it is also possible to reduce the number of defects in the initial first mask layer 130, thereby improving the pattern accuracy of the first mask layer.

In this embodiment, the deposition process includes a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the material of the initial first mask layer 130 includes a carbon-containing organic material.

Referring to fig. 7, a second mask layer 140 is formed on the surface of the initial first mask layer 130, and a portion of the surface of the initial first mask layer 130 is exposed by the second mask layer 140.

The second mask layer 140 and the first mask layer are used for transferring the photolithography pattern of the photoresist layer, so as to improve the stability of the photolithography pattern.

In this embodiment, in a direction perpendicular to the surface of the layer to be etched 100, the second mask layer 140 has a third thickness H3, and the third thickness H3 is smaller than the first thickness H1.

In a photolithography process using extreme ultraviolet light as a light source, the photoresist layer is thinner. Because the third thickness H3 is smaller than the first thickness H1, when the photoresist layer is used as a mask to etch the material layer of the second mask layer 140, the thinner material layer of the second mask layer 140 can form the second mask layer 140 before the photoresist layer is completely worn, so as to realize the transfer of the photolithography pattern under the euv photolithography process.

In this embodiment, the third thickness H3 is 12 nm or more.

In this embodiment, the material of the second mask layer 140 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the method for forming the second mask layer 140 includes: forming a second mask material layer (not shown) on the surface of the initial first mask layer 130; forming a photoresist pattern layer (not shown) on the surface of the second mask material layer, wherein the photoresist pattern layer exposes a part of the surface of the second mask material layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer 130 is exposed.

The process of etching the second mask material layer comprises a dry etching process or a wet etching process.

In this embodiment, the process of etching the second mask material layer includes a dry etching process.

In this embodiment, the photoresist pattern layer is removed after the second mask layer 140 is formed and before the initial first mask layer 130 is subsequently etched.

Subsequently, the method for forming the semiconductor structure further comprises the following steps: and forming a first flat layer, and etching the layer to be etched by taking the first flat layer as a mask. Specifically, the first planarization layer is formed, and the step of etching the layer to be etched is shown in fig. 8 and fig. 9.

Referring to fig. 8, after the second mask layer 140 is formed, the second mask layer 140 is used as a mask to etch the initial first mask layer 130 until the surface of the initial first stop layer 120 is exposed, so as to form a first mask layer 131; the initial first stop layer 120 is etched using the first mask layer 131 as a mask until the surface of the initial first planarization layer 110 is exposed, so as to form a first stop layer 121.

In other embodiments, since the first stop layer is not formed, the method of forming the first mask layer includes: and etching the initial first mask layer by taking the second mask layer as a mask until the surface of the first flat layer is exposed.

The process of etching the initial first mask layer 130 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first mask layer 130 includes a dry etching process.

The process of etching the initial first stop layer 120 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first stop layer 120 includes a dry etching process.

In this embodiment, after the first stop layer 121 is formed, and before the initial first planarization layer 110 is subsequently etched, the first mask layer 131 is removed.

In other embodiments, the first mask layer is not removed after forming the first stop layer and before subsequently etching the initial first planar layer.

Referring to fig. 9, the first stop layer 121 is used as a mask to etch the initial first planarization layer 110 until the surface of the layer to be etched 100 is exposed, so as to form a first planarization layer 111; and etching the layer to be etched 100 by taking the first flat layer 111 as a mask.

In other embodiments, since the first stop layer is not formed, or after the first stop layer is formed and before etching the initial first planarization layer, the method of forming the first planarization layer includes: after the second mask layer is formed, the first mask layer is used as a mask, and the initial first flat layer is etched until the surface of the layer to be etched is exposed.

In summary, by the method for forming a semiconductor structure, the photolithography process of extreme ultraviolet light is dealt with to improve the integration level, and meanwhile, the pattern precision of a photolithography pattern in the transfer process can be increased to improve the performance of a semiconductor device.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above forming method, referring to fig. 7, including: the layer to be etched 100; an initial first planarization layer 110 on the layer to be etched 100; an initial first mask layer 130 located on the initial first planarization layer 110; and a second mask layer 140 positioned on the initial first mask layer 130, wherein the second mask layer 140 exposes a portion of the surface of the initial first mask layer 130.

The initial first planarization layer 110 is used to repair the surface of the layer to be etched 100 and provide a material for forming the first planarization layer.

The initial first mask layer 130 is used to form a first mask layer.

In a direction perpendicular to the surface of the layer to be etched 100, the initial first planarization layer 110 has a first thickness H1, the initial first mask layer 130 has a second thickness H2, the second mask layer 140 has a third thickness H3, and the second thickness H2 is smaller than the first thickness H1, and the third thickness H3 is smaller than the first thickness H1.

Because the second thickness H2 is smaller than the first thickness H1, on the one hand, when the second mask layer 140 is used as a mask to etch the initial first mask layer 130 to form a first mask layer, the thinner initial first mask layer 130 can form a first mask layer before the second mask layer 140 is completely worn, so as to realize the transfer of the pattern of the second mask layer 140; on the other hand, the thicker initial first planarization layer 110 can enable the semiconductor structure to have higher flatness, which is beneficial to improving the pattern accuracy in the transfer process when transferring the photolithography pattern to the layer to be etched 100 by using the initial first planarization layer 110, the initial first mask layer 130 and the second mask layer 140.

In summary, by the semiconductor structure, the photolithography process of extreme ultraviolet light is processed to improve the integration level, and meanwhile, the pattern precision of the photolithography pattern in the transferring process can be increased to improve the performance of the semiconductor device.

The material of the layer to be etched 100 includes a semiconductor material.

In this embodiment, the first thickness H1 ranges from 150 nm to 300 nm.

The reason for selecting the range of the first thickness H1 is that: if the first thickness H1 is too large, on the one hand, the process time and material cost for forming the semiconductor structure may be increased. On the other hand, when the initial first flat layer 110 is etched to form a first flat layer, the pattern of the first flat layer has a larger aspect ratio, so that the reaction gas of the etching process is more difficult to reach the portion close to the initial first flat layer of the layer to be etched 100, which not only increases the difficulty of the etching process, but also causes the formed first flat layer to have a poorer morphology. Furthermore, when the initial first planarization layer 110 is formed using the spin coating process, the number of defects in the initial first planarization layer 110 is related to the size of the first thickness H1, and the smaller the first thickness H1, the more the number of defects, and thus, if the first thickness H1 is too small, the number of defects in the initial first planarization layer 110 may be excessive, thereby resulting in poor performance of the semiconductor device. Therefore, by making the first thickness H1 in the range of 150 nm to 300 nm, the process time and the material cost for forming the semiconductor structure can be within a reasonable range, and at the same time, the difficulty of the etching process for etching the initial first flat layer 110 can be reduced, the first flat layer with better morphology can be formed, the number of defects in the initial first flat layer 110 can be reduced, and the performance of the semiconductor device can be improved.

In this embodiment, the second thickness H2 ranges from 30 nm to 100 nm.

The reason why the second thickness H2 is selected is that if the second thickness H2 is too large, a first mask layer cannot be formed before the second mask layer 140 is completely consumed, so as to realize the transfer of the pattern of the second mask layer 140, and if the second thickness H2 is too small, the process difficulty of forming the initial first mask layer 130 is increased, so that the selection of the second thickness H2 can realize the transfer of the lithography pattern under the extreme ultraviolet process, and meanwhile, the process difficulty of forming the initial first mask layer 130 is reduced.

In this embodiment, the third thickness H3 is 12 nm or more.

In this embodiment, the semiconductor structure further includes: an initial first stop layer 120 located between the initial first planarization layer 110 and the initial first mask layer 130.

The initial first stop layer 120 provides material for forming the first stop layer, and the initial first stop layer 120 is used as an etch stop layer when etching the initial first mask layer 130.

Since the semiconductor structure further includes the initial first stop layer 120, on the one hand, when the initial first mask layer 130 is etched, the initial first stop layer 120 can protect the initial first flat layer 110, and reduce the influence of the etching process for etching the initial first flat layer 110 on the initial first mask layer 130, so that the accuracy of the lithography pattern transferred to the initial first flat layer 110 can be improved; on the other hand, when it is detected that the accuracy of the photolithography pattern transferred to the initial first mask layer 130 is poor, the influence of the process of removing the initial first mask layer 130 on the initial first planarization layer 110 can be reduced through the initial first stop layer 120 when removing the initial first mask layer 130 and re-forming a new initial first mask layer, thereby improving the performance of the semiconductor device, and the initial first mask layer 130 is removed without removing the initial first planarization layer 110, thereby simplifying the formation process of the semiconductor structure, reducing the formation time of the semiconductor structure, and improving the efficiency of manufacturing the semiconductor structure.

In other embodiments, the semiconductor structure does not include the initial first stop layer.

Since the etching process for etching the initial first mask layer 130 to form the first mask layer has a larger selective etching ratio to the material of the initial first mask layer 130 and the material of the initial first stop layer 120, the influence of the etching process for etching the initial first mask layer 130 on the initial first stop layer 120 can be reduced, and the accuracy of the transferred lithography pattern can be further improved.

In this embodiment, the initial first stop layer 120 has a fourth thickness H4 in a direction perpendicular to the surface of the layer to be etched 100, and the fourth thickness H4 is smaller than the second thickness H2.

Since the fourth thickness H4 is smaller than the second thickness H2, the first stop layer formed with the initial first stop layer 120 has a smaller thickness, and the pattern of the first stop layer has a smaller aspect ratio when the first stop layer is used as a mask, which can increase a process window of an etching process for etching the initial first planarization layer 110, thereby improving the performance of the semiconductor device.

In the present embodiment, the fourth thickness H4 is in the range of

Fig. 10 to 16 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

Referring to fig. 10, a layer to be etched 200 is provided.

The material of the layer to be etched 200 includes a semiconductor material.

In this embodiment, the material of the layer to be etched 200 includes silicon.

In this embodiment, the layer to be etched 200 has a device layer (not shown) therein. The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may further include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

Referring to fig. 11, an initial first planarization layer 210 is formed on the layer to be etched 200.

The initial first planarization layer 210 is used to repair the surface of the layer to be etched 200, and to provide a material for forming the first planarization layer subsequently.

The initial first planarization layer 210 has a first thickness T1 in a direction perpendicular to the surface of the layer to be etched 200.

In this embodiment, the process of forming the initial first planarization layer 210 includes a spin-coating process.

The reason for forming the initial first planarization layer 210 using the spin-coating process is that: the spin coating process has better filling performance, so that the initial first flat layer 210 formed by the spin coating process can better fill the uneven part on the layer to be etched 200, thereby improving the interface state of the initial layer to be etched 200, and the formed initial first flat layer 210 has higher flatness, so as to improve the graphic precision of the semiconductor structure and improve the performance of the semiconductor structure.

In this embodiment, the first thickness T1 ranges from 150 nm to 300 nm.

The range of the first thickness T1 is selected because: if the first thickness T1 is too large, on the one hand, the process time and material cost for forming the semiconductor structure are increased. On the other hand, when the initial first flat layer 210 is etched later to form the first flat layer, the pattern of the first flat layer has a larger aspect ratio, so that the reaction gas in the etching process is harder to reach the portion close to the initial first flat layer of the layer to be etched 200, which not only increases the difficulty of the etching process, but also causes the formed first flat layer to have a poorer morphology. Since the initial first planarization layer 210 is formed by using the spin-coating process, the number of defects in the initial first planarization layer 210 is related to the size of the first thickness T1, and the smaller the first thickness T1 is, the more the number of defects is, and thus, if the first thickness T1 is too small, the number of defects in the initial first planarization layer 210 is too large, thereby resulting in poor performance of the semiconductor device. Therefore, by making the range of the first thickness T1 between 150 nm and 300 nm, the process time and the material cost for forming the semiconductor structure are within a reasonable range, and not only can the difficulty of the subsequent etching process for etching the initial first flat layer 210 be reduced, but also the first flat layer with better morphology can be formed, and meanwhile, the number of defects in the initial first flat layer 210 can be reduced, so that the performance of the semiconductor device is improved.

In this embodiment, the process parameters of the spin-coating process include: the film forming temperature is below 400 ℃. The film forming temperature is higher, so that the influence of the temperature on the initial first planarization layer 210 in the subsequent process of forming the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the material of the initial first planarization layer 210 includes a carbon-containing organic material.

Referring to fig. 12, an initial first stop layer 220 is formed on the surface of the initial first planarization layer 210.

The initial first stop layer 220 provides material for the subsequent formation of the first stop layer.

Subsequently, an initial first mask layer is formed on the surface of the initial first stop layer, and the initial first stop layer 220 is used as an etching stop layer for subsequently etching the initial first mask layer.

Since the initial first stop layer 220 is formed, on the one hand, when the initial first mask layer is etched, the initial first stop layer 220 can protect the initial first flat layer 210, and reduce the influence of the etching process for etching the initial first mask layer on the initial first flat layer 210, so that the accuracy of the lithography pattern transferred to the initial first flat layer 210 can be improved; on the other hand, when it is detected that the accuracy of the photolithography pattern transferred to the initial first mask layer is poor, the influence of the process of removing the initial first mask layer on the initial first planarization layer 210 can be reduced through the initial first stop layer when removing the initial first mask layer and re-forming a new initial first mask layer, thereby improving the performance of the semiconductor device, and the initial first mask layer 210 does not need to be removed when removing the initial first mask layer, simplifying the formation process of the semiconductor structure, reducing the formation time of the semiconductor structure, and improving the efficiency of manufacturing the semiconductor structure.

In this embodiment, the material of the initial first stop layer 220 includes amorphous silicon.

Amorphous silicon is selected because: when the sidewall of the first stop layer formed with the initial first stop layer 220 is subsequently thinned etched, a simpler fabrication process with a larger process window can be used, thereby better forming a pattern with smaller critical dimensions. When the first stop layer is used as a sacrificial layer in the follow-up process and a side wall is formed on the side wall surface of the first stop layer, the etchant used in the etching process for etching the material layer of the side wall or the etchant used in the etching process for removing the first stop layer has a higher selective etching ratio on the material of the first stop layer and the material of the side wall, so that the influence of the etching process on the first stop layer or the side wall is reduced, and the pattern morphology of the semiconductor structure is improved.

In this embodiment, the initial first stop layer 220 has a fourth thickness T4 in a direction perpendicular to the surface of the layer to be etched 200.

In this embodiment, the fourth thickness T4 ranges from 5 nm to 10 nm.

The reason why the range of the fourth thickness T4 is selected is that if the fourth thickness T4 is too large, the process time and material cost for forming the semiconductor structure are increased, and when the first stop layer is used as a mask, the mask pattern has a large aspect ratio, reducing a process window of the etching process for etching the initial first planarization layer 210. If the fourth thickness T4 is too small, on the one hand, the function of the initial first stop layer 220 as an etching stop layer is affected, and on the other hand, when the first stop layer is used as a mask to etch the initial first flat layer 210 to form the first flat layer, the first stop layer is easily worn out before the first flat layer is formed, so that the transfer of the pattern of the first stop layer cannot be realized. Therefore, with the above-described fourth thickness T4 range of the initial first stop layer 220, not only can the function as an etch stop layer be ensured and, on the one hand, the transfer of the pattern of the first stop layer be achieved, but also the pattern of the first stop layer as a mask can be made to have a smaller aspect ratio, thereby increasing the process window of the etching process for etching the initial first planarization layer 210, improving the performance of the semiconductor device, and enabling the reduction of the thickness of the semiconductor structure and the reduction of the process time and material cost for forming the semiconductor structure. In addition, when the second thinning etching is performed on the sidewall of the first stop layer, the range of the fourth thickness T4 can also provide a margin for thinning etching for the first stop layer after the second thinning etching to have a proper thickness.

Referring to fig. 13, an initial first mask layer 230 is formed on the initial first planarization layer 210.

Specifically, in this embodiment, forming the initial first mask layer 230 on the initial first planarization layer 210 means that the initial first mask layer 230 is formed on the surface of the initial first stop layer 220.

The initial first mask layer 230 provides material for the subsequent formation of the first mask layer.

In this embodiment, in a direction perpendicular to the surface of the layer to be etched 200, the initial first mask layer 230 has a second thickness T2, the second thickness T2 is smaller than the first thickness T1, and the fourth thickness T4 is smaller than the second thickness T2.

Because the second thickness T2 is smaller than the first thickness T1, on one hand, when a second mask layer is formed subsequently and the initial first mask layer 230 is etched by taking the second mask layer as a mask, the thinner initial first mask layer 230 can form the first mask layer before the second mask layer is completely worn, so that the transfer of the pattern of the second mask layer is realized; on the other hand, the thicker initial first planarization layer 210 can enable the semiconductor structure to have higher flatness, which is beneficial to improving the pattern accuracy in the transfer process when transferring the photolithography pattern to the layer 200 to be etched with the initial first planarization layer 210, the initial first mask layer 230 and the second mask layer.

Since the fourth thickness T4 is smaller than the second thickness T2, the first stop layer has a smaller thickness, and when the first stop layer is used as a mask, the pattern of the first stop layer has a smaller aspect ratio, which can increase a process window of an etching process for etching the initial first planarization layer 210, thereby improving the performance of the semiconductor device.

In this embodiment, the second thickness T2 ranges from 30 nm to 100 nm.

The reason why the second thickness T2 is selected is that if the second thickness T2 is too large, the first mask layer cannot be formed before the second mask layer is completely worn, so as to realize the transfer of the pattern of the second mask layer, and if the second thickness T2 is too small, the process difficulty of forming the initial first mask layer is increased, so that the second thickness T2 is selected, on one hand, the transfer of the lithography pattern under the extreme ultraviolet process can be realized, and meanwhile, the process difficulty of forming the initial first mask layer is reduced.

In this embodiment, the process of forming the initial first mask layer 230 includes a deposition process.

The reason why the first mask layer 230 is formed using the deposition process is that the deposition process has a process characteristic in that the number of defects of the formed material layer is small and the number of defects is less affected by the thickness of the material layer. Therefore, by forming the initial first mask layer 230 using the deposition process, it is possible to cope with the transfer of the photolithography pattern in the extreme ultraviolet process while forming the initial first mask layer 230 having the smaller second thickness T2, and at the same time, it is also possible to reduce the number of defects in the initial first mask layer 230, thereby improving the pattern accuracy of the first mask layer.

In this embodiment, the material of the initial first mask layer 230 includes a carbon-containing organic material.

Referring to fig. 14, a second mask layer 240 is formed on the surface of the initial first mask layer 230, and a portion of the surface of the initial first mask layer 230 is exposed by the second mask layer 240.

The second mask layer 240 and the first mask layer are used to transfer the photolithography pattern of the photoresist layer, so as to improve the stability of the photolithography pattern.

In this embodiment, in a direction perpendicular to the surface of the layer to be etched 200, the second mask layer 240 has a third thickness T3, and the third thickness T3 is smaller than the first thickness T1.

In a photolithography process using extreme ultraviolet light as a light source, the photoresist layer is thinner. Because the third thickness T3 is smaller than the first thickness T1, when the photoresist layer is used as a mask to etch the material layer of the second mask layer 240, the thinner material layer of the second mask layer 240 can form the second mask layer 240 before the photoresist layer is completely worn, so as to realize the transfer of the photolithography pattern under the euv photolithography process.

In this embodiment, the third thickness T3 is 12 nm or more.

In this embodiment, the material of the second mask layer 240 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

In this embodiment, the method for forming the second mask layer 240 includes: forming a second mask material layer (not shown) on the surface of the initial first mask layer 230; forming a photoresist pattern layer (not shown) on the surface of the second mask material layer, wherein the photoresist pattern layer exposes a part of the surface of the second mask material layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer 230 is exposed.

In other embodiments, a method of forming a second mask layer includes: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein the photoresist pattern layer exposes part of the surface of the second mask material layer; forming a third side wall on the side wall of the photoresist pattern layer; removing the photoresist pattern layer after the third side wall is formed; and after the photoresist pattern layer is removed, etching the second mask material layer by taking the third side wall as a mask until the surface of the initial first mask layer is exposed.

In this embodiment, the photoresist pattern layer is removed after the second mask layer 240 is formed and before the initial first mask layer 230 is subsequently etched.

Subsequently, the method for forming the semiconductor structure further comprises the following steps: and forming a first flat layer, and etching the layer to be etched by taking the first flat layer as a mask. Specifically, the first planarization layer is formed, and the step of etching the layer to be etched is shown in fig. 15 and fig. 16.

Referring to fig. 15, after the second mask layer 240 is formed, the initial first mask layer 230 is etched with the second mask layer 240 as a mask until the surface of the initial first stop layer 220 is exposed, so as to form a first mask layer 231; the initial first stop layer 220 is etched using the first mask layer 231 as a mask until the surface of the initial first planarization layer 210 is exposed to form a first stop layer 221.

The process of etching the initial first stop layer 220 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first stop layer 220 includes a dry etching process.

The process of etching the initial first mask layer 230 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the initial first mask layer 230 includes a dry etching process.

In this embodiment, the first thinning etching is performed on the sidewall of the first mask layer 231 more than 1 time before the initial first stop layer 220 is etched.

Since the first thinning etching is performed on the sidewall of the first mask layer 231 for more than 1 time, the critical dimension of the pattern of the first mask layer 231 can be reduced, so that a pattern with smaller critical dimension can be formed on the layer to be etched, thereby meeting the design requirement of smaller critical dimension and further improving the integration level of the semiconductor device.

In this embodiment, the method for performing the first thinning etching on the sidewall of the first mask layer 231 for 1 time includes: performing first modification treatment on the first mask layer 231, and converting the side wall surface of the first mask layer 231 into a first layer to be removed; and etching the first layer to be removed until the first layer to be removed is removed.

In this embodiment, the process of the first modification treatment includes a thermal oxidation process.

The process of etching the first layer to be removed comprises a dry etching process or a wet etching process.

In this embodiment, the process of etching the first layer to be removed includes a dry etching process.

In other embodiments, the first thinning etch process is not performed.

In this embodiment, after forming the first stop layer 221 and before subsequently etching the initial first planarization layer 210, the first mask layer 231 is removed.

Referring to fig. 16, the initial first planarization layer 210 is etched with the first stop layer 221 as a mask until the surface of the layer to be etched 200 is exposed, so as to form a first planarization layer 211; and etching the layer to be etched 200 by taking the first flat layer 211 as a mask.

In this embodiment, the second thinning-out etching is performed on the sidewall of the first stop layer 221 more than 1 time before the initial first planarization layer 210 is etched.

Since the second thinning etching is performed on the sidewall of the first stop layer 221 for more than 1 time, the critical dimension of the pattern of the first stop layer 221 can be reduced, so that a pattern with smaller critical dimension can be formed on the layer to be etched, thereby meeting the design requirement of smaller critical dimension and further improving the integration level of the semiconductor device.

In this embodiment, the method for performing the second thinning-out etching on the sidewall of the first stop layer 221 for 1 time includes: performing a second modification treatment on the first stop layer 221 to convert the sidewall surface of the first stop layer 221 into a second layer to be removed; and etching the second layer to be removed until the second layer to be removed is removed.

In this embodiment, the second modification treatment process includes a thermal oxidation process.

The process of etching the second layer to be removed comprises a dry etching process or a wet etching process.

In this embodiment, the process of etching the second layer to be removed includes a dry etching process.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned forming method, referring to fig. 14, including: the layer to be etched 200; an initial first planarization layer 210 located on the layer to be etched 200; an initial first mask layer 230 located on the initial first planarization layer 210; and a second mask layer 240 positioned on the initial first mask layer 230, the second mask layer 240 exposing a portion of the surface of the initial first mask layer 230.

The initial first planarization layer 210 is used to repair the surface of the layer to be etched 200 and provide a material for forming the first planarization layer.

The initial first mask layer 230 is used to form a first mask layer.

In a direction perpendicular to the surface of the layer to be etched 200, the initial first planarization layer 210 has a first thickness T1, the initial first mask layer 230 has a second thickness T2, the second mask layer 240 has a third thickness T3, and the second thickness T2 is smaller than the first thickness T1, and the third thickness T3 is smaller than the first thickness T1.

Because the second thickness T2 is smaller than the first thickness T1, on the one hand, when the second mask layer 240 is used as a mask to etch the initial first mask layer 230 to form a first mask layer, the thinner initial first mask layer 230 can form a first mask layer before the second mask layer 240 is completely worn, so as to realize the transfer of the pattern of the second mask layer 240; on the other hand, the thicker initial first planarization layer 210 can enable the semiconductor structure to have higher flatness, which is beneficial to improving the pattern accuracy in the transfer process when transferring the photolithography pattern to the layer 200 to be etched with the initial first planarization layer 210, the initial first mask layer 230 and the second mask layer 240.

The material of the layer to be etched 200 includes a semiconductor material.

In this embodiment, the first thickness T1 ranges from 150 nm to 300 nm.

The range of the first thickness T1 is selected because: if the first thickness T1 is too large, on the one hand, the process time and material cost for forming the semiconductor structure are increased. On the other hand, when the initial first flat layer 210 is etched to form a first flat layer, the pattern of the first flat layer has a larger aspect ratio, so that the reaction gas of the etching process is more difficult to reach the portion close to the initial first flat layer of the layer to be etched 200, which not only increases the difficulty of the etching process, but also causes the formed first flat layer to have a poorer morphology. Furthermore, when the initial first planarization layer 210 is formed using the spin coating process, the number of defects in the initial first planarization layer 210 is related to the size of the first thickness T1, and the smaller the first thickness T1, the more the number of defects, and thus, if the first thickness T1 is too small, the number of defects in the initial first planarization layer 210 may be excessive, thereby resulting in poor performance of the semiconductor device. Therefore, by making the range of the first thickness T1 between 150 nm and 300 nm, the process time and the material cost for forming the semiconductor structure can be within a reasonable range, and at the same time, the difficulty of the etching process for etching the initial first flat layer 210 can be reduced, the first flat layer with better morphology can be formed, the number of defects in the initial first flat layer 210 can be reduced, and the performance of the semiconductor device can be improved.

In this embodiment, the second thickness T2 ranges from 30 nm to 100 nm.

The reason why the second thickness T2 is selected is that if the second thickness T2 is too large, a first mask layer cannot be formed before the second mask layer 240 is completely consumed, so as to realize the transfer of the pattern of the second mask layer 240, and if the second thickness T2 is too small, the process difficulty of forming the initial first mask layer 230 is increased, so that the selection of the second thickness T2 can realize the transfer of the lithography pattern under the extreme ultraviolet process, and meanwhile, the process difficulty of forming the initial first mask layer 230 is reduced.

In this embodiment, the third thickness T3 is 12 nm or more.

In this embodiment, the semiconductor structure further includes: an initial first stop layer 220 located between the initial first planarization layer 210 and the initial first mask layer 230.

The initial first stop layer 220 provides material for forming the first stop layer, and the initial first stop layer 220 is used as an etch stop layer when etching the initial first mask layer 230.

Since the semiconductor structure further includes the initial first stop layer 220, on the one hand, when the initial first mask layer 230 is etched, the initial first stop layer 220 can protect the initial first planarization layer 210, and reduce the influence of the etching process for etching the initial first planarization layer 210 on the initial first planarization layer 210, so that the accuracy of the lithography pattern transferred to the initial first planarization layer 210 can be improved; on the other hand, when it is detected that the accuracy of the photolithography pattern transferred to the initial first mask layer 230 is poor, the influence of the process of removing the initial first mask layer 230 on the initial first planarization layer 210 can be reduced through the initial first stop layer 220 when removing the initial first mask layer 230 and re-forming a new initial first mask layer, thereby improving the performance of the semiconductor device, and the initial first mask layer 230 is removed without removing the initial first planarization layer 210, simplifying the formation process of the semiconductor structure, reducing the formation time of the semiconductor structure, and improving the efficiency of manufacturing the semiconductor structure.

Amorphous silicon is selected because: when the sidewall of the first stop layer formed with the initial first stop layer 220 is thinned, a simpler manufacturing process with a larger process window can be used, thereby better forming a pattern with smaller critical dimensions. When the first stop layer is used as a sacrificial layer and a side wall is formed on the side wall surface of the first stop layer, an etchant used in an etching process for etching the material layer of the side wall or an etchant used in an etching process for removing the first stop layer has a higher selective etching ratio on the material of the first stop layer and the material of the side wall, so that the influence of the etching process on the first stop layer or the side wall is reduced, and the pattern morphology of the semiconductor structure is improved.

In this embodiment, the initial first stop layer 220 has a fourth thickness T4 in a direction perpendicular to the surface of the layer to be etched 200, and the fourth thickness T4 is smaller than the second thickness T2.

Since the fourth thickness T4 is smaller than the second thickness T2, the first stop layer formed with the initial first stop layer 220 has a smaller thickness, and the pattern of the first stop layer has a smaller aspect ratio when the first stop layer is used as a mask, which can increase a process window of an etching process for etching the initial first planarization layer 210, thereby improving the performance of the semiconductor device.

In this embodiment, the fourth thickness T4 ranges from 5 nm to 10 nm.

The reason why the range of the fourth thickness T4 is selected is that if the fourth thickness T4 is too large, the process time and material cost for forming the semiconductor structure are increased, and when the first stop layer is used as a mask, the mask pattern has a large aspect ratio, reducing a process window of the etching process for etching the initial first planarization layer 210. If the fourth thickness T4 is too small, on the one hand, the function of the initial first stop layer 220 as an etching stop layer is affected, and on the other hand, when the first stop layer is used as a mask to etch the initial first flat layer 210 to form the first flat layer, the first stop layer is easily worn out before the first flat layer is formed, so that the transfer of the pattern of the first stop layer cannot be realized. Therefore, with the above-described fourth thickness T4 range of the initial first stop layer 220, not only can the function as an etch stop layer be ensured and, on the one hand, the transfer of the pattern of the first stop layer be achieved, but also the pattern of the first stop layer as a mask can be made to have a smaller aspect ratio, thereby increasing the process window of the etching process for etching the initial first planarization layer 210, improving the performance of the semiconductor device, and enabling the reduction of the thickness of the semiconductor structure and the reduction of the process time and material cost for forming the semiconductor structure. In addition, when the second thinning etching is performed on the sidewall of the first stop layer, the range of the fourth thickness T4 can also provide a margin for thinning etching for the first stop layer after the second thinning etching.

Fig. 17 to 22 are schematic cross-sectional structures of steps of a method for forming a semiconductor structure according to still another embodiment of the present invention, and the main difference between the present embodiment and the embodiment shown in fig. 10 to 16 is that after forming the second mask layer 240, the method and structure for forming the first mask layer, the first stop layer, the first planarization layer, and the method and structure for etching the band etching layer 200 are different, so that the present embodiment will continue to describe the process for forming the semiconductor structure based on the above embodiments.

Referring to fig. 17 on the basis of fig. 14, after the second mask layer 240 is formed, a second sidewall 242 is formed on a sidewall surface of the second mask layer 240; after the second sidewall 242 is formed, the second mask layer 240 is removed.

In this embodiment, the method for forming the second sidewall 242 includes: depositing a second sidewall material layer (not shown) on the surface of the second mask layer 240 and the surface of the initial first mask layer 230; and etching back the second sidewall material layer until the top surface of the second mask layer 240 and the surface of the initial first mask layer 230 are exposed.

In this embodiment, the process of removing the second mask layer 240 includes a dry etching process or a wet etching process.

Referring to fig. 18, after the second mask layer 240 is removed, the second sidewall 242 is used as a mask to etch the initial first mask layer 230 until the surface of the initial first stop layer 220 is exposed, so as to form a first mask layer 250.

In this embodiment, after the first mask layer 250 is formed, the second sidewall 242 is removed.

Referring to fig. 19, after the second side walls 242 are removed, first side walls 251 are formed on the side wall surfaces of the first mask layer 250; after the first sidewall 251 is formed, the first mask layer 250 is removed.

In this embodiment, the method for forming the first sidewall 251 includes: depositing a first sidewall material layer (not shown) on the surface of the first mask layer 250 and the initial first stop layer 220; the first sidewall material layer is etched back until the top surface of the first mask layer 250 and the initial first stop layer 220 surface are exposed.

In this embodiment, the process of removing the first mask layer 250 includes a dry etching process or a wet etching process.

Referring to fig. 20, after the first mask layer 250 is removed, the first sidewall 251 is used as a mask to etch the initial first stop layer 220 until the surface of the initial first planarization layer 210 is exposed, so as to form a first stop layer 260.

In this embodiment, after the first stop layer 260 is formed, the first sidewall 251 is removed.

Referring to fig. 21, after the first sidewall 251 is removed, a mask sidewall 261 is formed on the sidewall surface of the first stop layer 260; after forming the mask sidewall 261, the first stop layer 260 is removed.

In this embodiment, the process of removing the first stop layer 260 includes a dry etching process or a wet etching process.

Referring to fig. 22, after the first stop layer 260 is removed, the mask sidewall 261 is used as a mask to etch the initial first planarization layer 210 until the surface of the layer to be etched 200 is exposed, so as to form a first planarization layer 211.

The process of etching the initial first planarization layer 210 includes a dry etching process or a wet etching process.

In this embodiment, after the first planarization layer 211 is formed, the mask sidewall 261 is removed; after the mask sidewall 261 is removed, the first flat layer 211 is used as a mask to etch the layer 200 to be etched.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

A layer to be etched;

An initial first planar layer on the layer to be etched, the initial first planar layer having a first thickness;

An initial first mask layer on the initial first planar layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness;

And the second mask layer is positioned on the initial first mask layer, part of the surface of the initial first mask layer is exposed by the second mask layer, the second mask layer has a third thickness, and the third thickness is smaller than the first thickness.

2. The semiconductor structure of claim 1, wherein the material of the initial first planar layer comprises a carbon-containing organic material.

3. The semiconductor structure of claim 1, wherein the material of the initial first mask layer comprises a carbon-containing organic material.

4. The semiconductor structure of claim 1, wherein the first thickness ranges from 150 nm to 300nm.

5. The semiconductor structure of claim 1, wherein the second thickness ranges from 30 nm to 100 nm.

6. The semiconductor structure of claim 1, wherein the third thickness is above 12 nanometers.

7. The semiconductor structure of claim 1, further comprising: an initial first stop layer located between the initial first planarization layer and the initial first mask layer.

8. The semiconductor structure of claim 7, wherein the initial first stop layer has a fourth thickness that is less than the second thickness.

9. The semiconductor structure of claim 8, wherein the material of the initial first stop layer comprises a metal oxide.

10. The semiconductor structure of claim 9, wherein the fourth thickness is in a range of

11. The semiconductor structure of claim 8, wherein the material of the initial first stop layer comprises amorphous silicon.

12. The semiconductor structure of claim 11, wherein the fourth thickness is in a range of 5 nm to 10 nm.

13. The semiconductor structure of claim 1, wherein the material of the second mask layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

14. A method of forming a semiconductor structure, comprising:

providing a layer to be etched;

Forming an initial first flat layer on the layer to be etched, wherein the initial first flat layer has a first thickness;

forming an initial first mask layer on the initial first planar layer, the initial first mask layer having a second thickness, the second thickness being less than the first thickness;

And forming a second mask layer on the initial first mask layer, wherein the second mask layer exposes part of the surface of the initial first mask layer, the second mask layer has a third thickness, and the third thickness is smaller than the first thickness.

15. The method of forming a semiconductor structure of claim 14, wherein the process of forming the initial first mask layer comprises a deposition process.

16. The method of forming a semiconductor structure of claim 14, wherein the process of forming the initial first planar layer comprises a spin-on process.

17. The method of forming a semiconductor structure of claim 16, wherein the process parameters of the spin-on process comprise: the film forming temperature is below 400 ℃.

18. The method of forming a semiconductor structure of claim 14, wherein the method of forming the second mask layer comprises: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein the photoresist pattern layer exposes part of the surface of the second mask material layer; and etching the second mask material layer by taking the photoresist pattern layer as a mask until the surface of the initial first mask layer is exposed.

19. The method of forming a semiconductor structure of claim 14, further comprising: and etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first flat layer is exposed so as to form a first mask layer.

20. The method of forming a semiconductor structure of claim 19, further comprising: etching the initial first flat layer by taking the first mask layer as a mask until the surface of the layer to be etched is exposed, so as to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

21. The method of forming a semiconductor structure of claim 14, further comprising: an initial first stop layer is formed on the initial first planar layer surface prior to forming the initial first mask layer.

22. The method of forming a semiconductor structure of claim 21, wherein the initial first stop layer has a fourth thickness, the fourth thickness being less than the second thickness.

23. The method of forming a semiconductor structure of claim 21, further comprising: etching the initial first mask layer by taking the second mask layer as a mask until the surface of the initial first stop layer is exposed so as to form a first mask layer; and etching the initial first stop layer by taking the first mask layer as a mask until the surface of the initial first flat layer is exposed so as to form a first stop layer.

24. The method of forming a semiconductor structure of claim 23, further comprising: etching the initial first flat layer by taking the first stop layer as a mask until the surface of the layer to be etched is exposed, so as to form a first flat layer; and etching the layer to be etched by taking the first flat layer as a mask.

25. The method of forming a semiconductor structure of claim 24, wherein the material of the initial first stop layer comprises a metal oxide.

26. The method of forming a semiconductor structure of claim 24, further comprising: and before etching the initial first stop layer, performing first thinning etching on the side wall of the first mask layer for more than 1 time.

27. The method of forming a semiconductor structure of claim 26, further comprising: and before etching the initial first flat layer, performing second thinning etching on the side wall of the first stop layer for more than 1 time.

28. The method of forming a semiconductor structure of claim 26, wherein the material of the initial first stop layer comprises amorphous silicon.

29. The method of forming a semiconductor structure of claim 21, further comprising: removing part of the initial first stop layer on the surface of the initial first flat layer after forming the initial first stop layer so as to form a first stop layer; after the first stop layer is formed, forming a mask side wall on the surface of the side wall of the first stop layer; removing the first stop layer after forming the mask side wall; and after the first stop layer is removed, etching the initial first flat layer by taking the mask side wall as a mask until the surface of the layer to be etched is exposed, so as to form a first flat layer.

30. The method of forming a semiconductor structure of claim 29, further comprising: and etching the layer to be etched by taking the first flat layer as a mask.

31. The method of forming a semiconductor structure of claim 29, wherein the material of the initial first stop layer comprises amorphous silicon.

32. The method of forming a semiconductor structure of claim 29, wherein the method of forming the first stop layer comprises: removing part of the initial first mask layer on the surface of the initial first stop layer to form a first mask layer; forming a first side wall on the side wall surface of the first mask layer; after the first side wall is formed, removing the first mask layer; and after the first mask layer is removed, etching the initial first stop layer by taking the first side wall as a mask until the surface of the initial first flat layer is exposed.

33. The method of forming a semiconductor structure of claim 32, wherein the method of forming the first mask layer comprises: forming a second side wall on the side wall surface of the second mask layer after forming the second mask layer; removing the second mask layer after the second side wall is formed; and after the second mask layer is removed, etching the initial first mask layer by taking the second side wall as a mask until the surface of the initial first stop layer is exposed.

34. The method of forming a semiconductor structure of claim 29, wherein the method of forming the second mask layer comprises: forming a second mask material layer on the surface of the initial first mask layer; forming a photoresist pattern layer on the surface of the second mask material layer, wherein the photoresist pattern layer exposes part of the surface of the second mask material layer; forming a third side wall on the side wall of the photoresist pattern layer; removing the photoresist pattern layer after the third side wall is formed; and after the photoresist pattern layer is removed, etching the second mask material layer by taking the third side wall as a mask until the surface of the initial first mask layer is exposed.