CN113393790B

CN113393790B - Display panel driving method and device and display device

Info

Publication number: CN113393790B
Application number: CN202110555260.5A
Authority: CN
Inventors: 康志聪; 袁海江
Original assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2023-07-25
Anticipated expiration: 2041-05-20
Also published as: CN113393790A

Abstract

The invention discloses a driving method and device of a display panel and the display device, wherein the display panel comprises the following components: each pixel group comprises two rows of adjacent sub-pixel groups, and the storage capacitors of one sub-pixel in each sub-pixel group and two non-adjacent sub-pixels in the other sub-pixel group are respectively connected with a first common electrode line; the storage capacitor of one sub-pixel in each sub-pixel group and the storage capacitor of two adjacent sub-pixels in the other sub-pixel group are connected with the other first common electrode line; each sub-pixel group is connected with a data line with the sub-pixel groups of adjacent rows of adjacent columns; wherein the polarities of the voltages on the first common electrode lines of two adjacent lines are opposite; the driving method of the display panel comprises the following steps: controlling the data voltage on each data line to switch positive and negative polarities by taking two frames as a driving period; the common electrode voltage on each first common electrode line is controlled to maintain the same polarity as the common electrode voltage of the previous frame.

Description

Display panel driving method and device and display device

Technical Field

The present invention relates to the field of display devices, and in particular, to a driving method and apparatus for a display panel, and a display device.

Background

Currently, large-sized display panels require a larger viewing angle for display, and in the pixel driving process, the brightness of the large viewing angle is saturated rapidly with voltage, so that the quality of viewing angle image contrast and color cast are seriously deteriorated compared with that of front view image. The common way to solve the problem of view bias is to divide each sub-pixel of the display panel into main/sub-pixels and apply different driving voltages to the main/sub-pixels, and the design often requires to redesign metal wirings or TFT elements to drive the sub-pixels, which results in sacrificing the light-permeable opening area, affecting the panel transmittance, and directly resulting in the improvement of backlight cost.

Disclosure of Invention

The invention provides a driving method and device of a display panel and a display device, and aims to improve the problem of image quality color cast caused by visual angle deviation.

In order to achieve the above object, the present invention provides a driving method of a display panel, the display panel including:

each pixel group comprises two rows of adjacent sub-pixel groups, the two rows of adjacent sub-pixel groups are respectively connected with one scanning line, each sub-pixel group comprises two sub-pixels, and the two sub-pixels are connected with the same scanning line;

in the two sub-pixel groups of the adjacent rows, the storage capacitors of the two adjacent sub-pixels are connected with the same first common electrode line, and the storage capacitors of the two non-adjacent sub-pixels are respectively connected with the other two first common electrode lines in a one-to-one correspondence manner;

Two data lines connected with two adjacent sub-pixel groups in the same row are adjacent, and two data lines connected with two adjacent sub-pixel groups in the adjacent row are adjacent;

the polarities of voltages on two adjacent first public electrode lines are opposite; the driving method of the display panel comprises the following steps:

controlling the data voltage on each data line to switch positive and negative polarities by taking two frames as a driving period;

and controlling the common electrode voltage on each first common electrode line to maintain the same polarity as the common electrode voltage of the previous frame.

Optionally, the scanning signal on each scanning line in each frame comprises an on phase and an off phase;

when the scanning signal of each scanning line is in an opening stage, controlling the common electrode voltage on the first common electrode line to perform high-low level switching;

and when the scanning signal of each scanning line is in a closing stage, controlling the common electrode voltage on the first common electrode line to perform secondary high-low level switching.

Optionally, when the scan signal of each scan line is in the off phase, the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level flip switching includes:

The two rows of sub-pixels in the same group are the nth row sub-pixels and the n+1th row sub-pixels respectively;

when the data voltages of the n-th row of sub-pixels and the n+1-th row of sub-pixels are positive, the common electrode voltage of the n-th row of sub-pixels is controlled to be switched from a low level to a high level, and the common electrode voltage of the n+1-th row of sub-pixels is controlled to be switched from the high level to the low level;

when the data voltages of the sub-pixels in the nth row and the sub-pixels in the n+1th row are controlled to be negative, the common electrode voltage of the sub-pixels in the nth row is controlled to be switched from a low level to a high level, and the common electrode voltage of the sub-pixels in the n+1th row is controlled to be switched from the high level to the low level.

Optionally, when the scan signal of each scan line is in the off phase, the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level flip switching specifically includes:

when the data voltages of the sub-pixels in the nth row and the sub-pixels in the n+1th row are controlled to be positive, the common electrode voltage of the sub-pixels in the nth row is controlled to be switched from a high level to a low level, and the common electrode voltage of the sub-pixels in the n+1th row is controlled to be switched from the low level to the high level;

When the data voltages of the sub-pixels in the nth row and the sub-pixels in the n+1th row are controlled to be negative, the common electrode voltage of the sub-pixels in the nth row is controlled to be switched from a high level to a low level, and the common electrode voltage of the sub-pixels in the n+1th row is controlled to be switched from the low level to the high level.

Optionally, the driving method of the display panel further includes:

and in the same frame, controlling the data voltages on the data lines of two adjacent groups of sub-pixels to switch the positive polarity and the negative polarity.

Optionally, the data voltages on adjacent columns of data lines are of opposite polarity.

Optionally, the driving method of the display panel further includes:

and performing column inversion driving on each sub-pixel.

The present invention also provides a driving apparatus of a display panel, the display panel including:

the polarities of the voltages on the adjacent two first public electrode lines are opposite, and the polarities of the data voltages on the data lines of the sub-pixels in each group in the same column are the same; the driving device of the display panel includes:

the source electrode driving circuit is configured to output data voltages with positive and negative polarities switched to each data line by taking two frames as a driving period;

the output end of the common electrode voltage circuit and each first common electrode line are configured to take two frames as a driving period, and output the common electrode voltage with the same maintaining polarity as the common electrode voltage of the previous frame to each first common electrode line;

the driving device of the display panel is further provided with a processor, a memory and a driving program of the display panel stored on the memory and capable of running on the processor, wherein the driving program of the display panel is configured to realize the steps of the driving method of the display panel.

Optionally, the driving device of the display panel further includes a gate driving circuit, and the gate driving circuit is connected to the gate of each subpixel; the grid driving circuit is configured to output grid driving signals to the sub-pixels of each row, so that corresponding voltages are applied to the second common electrode and the data line, and the sub-pixel capacitance of the corresponding row is charged.

Optionally, the driving device of the display panel further includes a timing controller, and the timing controller is connected to the gate driving circuit and the source driving circuit respectively; the timing controller is configured to output a timing control signal to the gate driving circuit and the source driving circuit.

The invention also provides a display device which comprises a display panel and the driving device of the display panel, wherein the driving device of the display panel is connected with each sub-pixel of the display panel.

In the driving method of the display panel, in each sub-pixel group in a frame, the same column data voltage in the same sub-pixel group has the same polarity, and the common electrode voltage on the first common electrode is different, so that the brightness of the display of the two sub-pixels is in a brightness difference. And in the driving period of two frames, the data voltages on the data lines are controlled to be switched in positive and negative polarities by taking the two frames as one driving period, and then the data voltages on the data lines are controlled to be switched in positive and negative polarities by taking the two frames as one driving period. The arrangement is such that in the same group, the display brightness of two sub-pixels in the same column is switched between brighter and darker in the same group, the display brightness of two sub-pixels in adjacent columns in a frame is switched between brighter and darker, and the brightness of two adjacent sub-pixels changes, and for a complete row, the whole is changed alternately. When the whole display panel presents the difference of brightness and darkness, the display panel is displayed with relatively uniform brightness, so that the problem of image quality color cast caused by visual angle deviation is solved; in addition, the invention basically reduces half of the scanning lines and the common electrode lines by sharing the scanning lines and the first common electrode lines, thereby increasing the effective aperture ratio of the display panel, improving the penetration rate and reducing the cost.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic circuit diagram of an embodiment of a display panel with multiple sub-pixel groups according to the present invention;

FIG. 2 is a flow chart of an embodiment of a driving method of a display panel according to the present invention;

FIG. 3 is a schematic diagram showing a display effect of the display panel in the first frame1 and the second frame2 of the current driving period;

FIG. 4 is a schematic diagram showing a driving timing relationship corresponding to an nth row scan line of an mth column according to the present invention;

FIG. 5 is a schematic diagram showing a driving timing relationship corresponding to an n+1th row scanning line in an mth row of the present invention;

FIG. 6 is a schematic diagram showing another display effect of the display panel in the first frame1 and the second frame2 of the current driving period;

FIG. 7 is a schematic diagram showing another driving timing relationship corresponding to an nth row scan line of an mth column according to the present invention;

FIG. 8 is a schematic diagram of another driving timing relationship corresponding to the n+1th row scan line of the mth column of the present invention;

FIG. 9 is a schematic circuit diagram of an embodiment of a driving device of a display panel according to the present invention;

fig. 10 is a schematic structural diagram of an embodiment of a display panel of the present invention.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				10	Time sequence controller	101	Sub-pixel group
20	Source electrode driving circuit	110	First substrate
				30	Gate driving circuit	120	Second substrate
40	Power management integrated circuit	130	Liquid crystal layer
				50	Common electrode voltage circuit	140	Pixel array
100	Display panel	150	Frame glue

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present invention, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.

In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The invention provides a driving method of a display panel, which is suitable for a display device provided with the display panel.

Currently, most of large-size lcd panels adopt negative VA (Vertical Alignment vertical alignment) liquid crystal or IPS (In-Plane Switching) liquid crystal technology, which has advantages of higher production efficiency and lower manufacturing cost compared with IPS liquid crystal technology, but has obvious optical defects compared with IPS liquid crystal technology In optical properties, especially large-size panels need larger viewing angle for commercial application, and VA driving causes serious viewing angle image quality contrast and color cast compared with front-view image quality degradation due to rapid saturation of large viewing angle brightness along with voltage. The VA-mode liquid crystal technology solves the problem of visual character bias by dividing each sub-pixel of RGB into main/sub pixels, so that the overall large-view-angle brightness is close to front view along with voltage change.

In order to solve the problem of color cast without sacrificing the aperture ratio of pixel design, the invention realizes adjacent arrangement of high and low voltages in space through adjustment of the driving signals, maintains the original brightness signal, can achieve the optical effect that the brightness of a large viewing angle is close to that of a positive viewing angle, improves the problem of color cast of the large viewing angle, and further achieves the improvement of visual character cast while maintaining the panel characteristic of higher transmittance. And the switching between the general display (without performing the high-low voltage adjacent driving) and the use environment (performing the high-low voltage adjacent driving) needing to pay attention to the visual character bias can be realized on the original display without the need of pixel design change only by the difference of driving signals.

Referring to fig. 1, in an embodiment of the present invention, the display panel includes:

a plurality of pixel groups 101, each of the pixel groups including two rows of adjacent sub-pixel groups (101 n, 101n ', 101n+1'), the two rows of adjacent sub-pixel groups (101 n, 101n '), (101n+1, 101n+1') each being connected to one scanning line (Gn, gn+1), each of the sub-pixel groups including two sub-pixels, the two sub-pixels being connected to the same scanning line;

in the two sub-pixel groups of the adjacent rows, the storage capacitors of the two adjacent sub-pixels are connected with the same first common electrode line, and the storage capacitors of the non-adjacent two sub-pixels are connected with the other two first common electrode lines in a one-to-one correspondence manner;

two data lines connected with two adjacent sub-pixel groups in the same row are adjacent, and two data lines connected with two adjacent sub-pixel groups in the adjacent row are adjacent; the polarities of voltages on two adjacent first public electrode lines are opposite. The polarities of the data voltages on the data lines (Dm-1, dm, dm+1) of two sub-pixels positioned in the same column in each group are the same, and the polarities of the voltages on the data lines (Dm-1, dm, dm+1) of two adjacent columns of the sub-pixels in the same row are opposite.

In this embodiment, a pixel array (not shown), scan lines (Gn, gn+1), data lines (Dm-1, dm, dm+1), a first common electrode line Vst1 and a second common electrode line Vcom are disposed on the display panel, and the pixel array includes a plurality of sub-pixels. Each sub-pixel comprises an active switch (thin film transistor), a pixel capacitor Clc and a storage capacitor Cst, wherein a grid electrode of the active switch is electrically connected with a scanning line (Gn, gn+1) corresponding to the sub-pixel, a source electrode of the active switch is electrically connected with a data line (Dm-1, dm, dm+1) corresponding to the sub-pixel, a drain electrode of the active switch is electrically connected with the pixel capacitor Clc and one end of the storage capacitor Cst of the sub-pixel through the data line (Dm-1, dm, dm+1), and the other end of each pixel capacitor Clc is electrically connected with a second common electrode line Vcom. In this embodiment, two rows of sub-pixels are defined as a group of sub-pixel groups 101, and the other ends of the storage capacitors Cst of the two sub-pixel groups 101 are respectively connected to a first common electrode line Vst1. Wherein, each sub-pixel is divided into three sub-pixels of red, green and blue. Three sub-pixels per red, green and blue constitute one pixel. The plurality of thin film transistors constitute the thin film transistor array of the present embodiment. It should be noted that the number of the scan lines and the data lines may be set according to the size, resolution, etc. of the display panel, and the embodiments shown in the present invention are described by taking two rows of scan lines (Gn, gn+1) and two columns of data lines (Dm-1, dm, dm+1) as examples, and the pixel driving of other rows may refer to the embodiments of the present invention, which will not be described in detail herein.

Referring to FIG. 1, in FIG. 1, gn, gn+1 are illustrated as two adjacent rows of scan lines, dm-1, dm, dm+1 are illustrated as three adjacent columns of data lines, n ^st Vst1、(n+1) ^st Vst2、(n+2) ^st Three adjacent first common electrode lines Vst1, clc1 and Clc2 represent pixel capacitances connected to the same scanning line in the same group, and Cst1 and Cst2 represent storage capacitances respectively connected to different first common electrode lines in the same group.

Referring to fig. 2, the driving apparatus of the display panel includes a timing controller 10, a source driving circuit 20, a gate driving circuit 30, a power management integrated circuit 40, and a common electrode voltage circuit 50, wherein the thin film transistors in the same column are connected to the source driving circuit 20 through a data line (Dm-1, dm, dm+1), and the thin film transistors in each group in two rows are connected to the gate driving circuit 30 through a scan line (Gn, gn+1), so as to form a thin film transistor array. These thin film transistors may be a-Si (amorphous Silicon) thin film transistors or Poly-Si (polycrystalline Silicon) thin film transistors, wherein the Poly-Si thin film transistors may be formed using LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline Silicon) or the like. The other end of the storage capacitor Cst is connected to the common electrode voltage circuit 50 through a second common electrode line Vcom.

The timing controller 10 receives data signals, control signals, and timing signals output from an external control circuit, such as a control system SOC of a television, and converts the data signals, control signals, and timing signals into data signals, control signals, and timing signals suitable for each of the gate driving circuit 30 and the source driving circuit 20, and the gate driving circuit 30 outputs gate-on signals and gate-off signals according to the timing signals to scan each row of sub-pixels line by line, and when the thin film transistors in the sub-pixels of the corresponding row are turned on, the source driving circuit 20 outputs the data signals to the corresponding sub-pixels through the data lines (Dm-1, dm, dm+1) to realize image display of the display panel. The number of the source driving circuits 20 is plural, and specifically, the number may be set according to the size of the display panel, and this embodiment will be described by taking two as an example. The power management integrated circuit 40, the output end of the power management integrated circuit 40 is connected with the grid driving circuit 30 and the source driving circuit 20; the power management integrated circuit 40 integrates a plurality of dc-dc conversion circuits of different circuit functions, each of which outputs a different voltage value. The voltage input to the input terminal of the power management integrated circuit 40 is typically 5V or 12V, and the output voltage includes the operating voltage DVDD supplied to the timing controller 10 and the operating voltage supplied to the gate driving circuit 30.

Referring to fig. 2, the driving method of the display panel based on the display panel and the driving device of the display panel includes the steps of:

step S100, controlling the data voltage on each data line to switch positive and negative polarities by taking two frames as a driving period;

it can be understood that, in the case where the potential of the second common electrode is kept unchanged, the ac driving of the liquid crystal molecules is achieved, which is equivalent to the constant potential of the connection between the pixel capacitor and the second common electrode line, and the potential of the other electrode connected to the drain electrode is changed at a high level with respect to the common electrode reference voltage Vcom on the second common electrode. That is, the polarity of the data voltage outputted from the source driver is determined by the voltage value of the data voltage and the common electrode reference voltage Vcom in the present embodiment, which is increased or decreased with respect to the common electrode reference voltage Vcom: the positive polarity of the data voltage is that the voltage value of the data voltage loaded on the data line is greater than the common electrode reference voltage Vcom on the second common electrode line; the negative polarity driving is that the voltage value of the data voltage applied to the data line is smaller than the voltage value of the common electrode reference voltage Vcom on the second common electrode line. When the voltage difference between the two is greater than 0, the polarity is positive, and is generally indicated by a "+" sign; when the voltage difference between the two is less than 0, the polarity is negative, generally indicated by a "-" sign. Therefore, in this embodiment, controlling the data voltages on the data lines to switch between positive and negative polarities with two frames as one driving period can be understood as follows: when the voltage on the data line is positive in the first frame, the voltage is switched to negative in the second frame. In the driving process using two frames as a driving period, the data voltage of each sub-pixel is controlled to be alternately changed in height, so that the same sub-pixel can not always maintain high voltage or low voltage, and the problems of easy particle feeling and reduced resolution in the image quality caused by maintaining high voltage or low voltage signals at the same sub-pixel position in space are avoided.

The two frames are taken as driving periods, and it can be understood that the pixel driving process of the current frame is completed, the next frame of pixel driving can be switched, and the next frame of pixel driving process is also sequentially switched as the driving process of the current frame until the pixel driving of all frames is completed.

Step S200, controlling the common electrode voltage on each first common electrode line to maintain the same polarity as the common electrode voltage of the previous frame.

In this embodiment, one end of the storage capacitor is connected to the thin film transistor through the pixel electrode, and the other end is connected to a first common electrode line, that is, the storage capacitor is formed by overlapping the pixel electrode and the second common electrode line. The voltage on the first common electrode line can realize high-low level switching, and can be controlled by a common electrode voltage circuit, wherein a memory, a digital-to-analog converter, a signal amplifier and the like are usually integrated in the common electrode voltage circuit. The voltage required to switch the high level and the low level in each frame in this embodiment may be stored in the memory, and in particular may be connected to the upper computer through the communication interface and the communication circuit in a communication manner, and store the public voltage output by the upper computer. When the display device works, the digital-to-analog converter converts the digital common voltage into the analog common voltage, and outputs the analog common voltage to the corresponding first common electrode wire after being amplified by the signal amplifier, so that the high-level common electrode voltage or the low-level common electrode voltage is applied to the common electrode wire.

It will be appreciated that the storage capacitance and the pixel capacitance are electrically connected by the pixel electrode and that there may also be parasitic capacitance, e.g. pixel parasitic capacitance, on each sub-pixel. Therefore, when the common electrode voltage applied to the first common electrode connected to the storage capacitor is changed, the voltage across the storage capacitor is changed. The voltage is coupled among the pixel capacitor, the storage capacitor and the parasitic capacitor, so that the voltage on the pixel electrode connected with the pixel capacitor is changed, and under the condition that the common voltage on the second common electrode line is unchanged, the voltage on the pixel electrode is changed, so that the voltage on two ends of the pixel capacitor is changed, and the brightness of the sub-pixel corresponding to the pixel capacitor is changed. In this embodiment, the common electrode voltage applied to the first common electrode is unchanged between frames, for example, when the common electrode voltage on one first common electrode of a current frame is at a low level, the common electrode voltage on the first common electrode remains at a low level when scanning to a next frame. When the common voltage applied to the adjacent other first common electrode is at a high level, the next frame is scanned, and the voltage on the first common electrode is still at a high level.

In an embodiment, the scanning signal on each scanning line in each frame comprises an on phase and an off phase;

when the scanning signal of each scanning line is in an opening stage, controlling the common electrode voltage on the first common electrode line to perform high-low level turnover switching or low-high level turnover switching;

and when the scanning signal of each scanning line is in a closing stage, controlling the common electrode voltage on the first common electrode line to perform secondary low-high level switching or secondary high-low level switching.

In this embodiment, in the same frame in which two frames are driving periods, the scanning signal of each scanning line includes an on phase and an off phase, in the on phase, the sub-pixels of the corresponding row are driven to charge, and after the charging is completed, the gate driving circuit 30 outputs a gate off signal, so that the sub-pixels are driven to stop charging. In the present embodiment, in the on phase, that is, in charging the sub-pixels of the corresponding row, the voltage on one of the two adjacent first common electrode lines is controlled to be switched from the low level to the high level, and in the off phase, the voltage on the first common electrode line is switched from the high level to the low level, so as to realize the secondary inversion of the level. The voltage of the other one of the two adjacent first common electrode lines is controlled to be switched from a high level to a low level in an opening stage, and the voltage of the first common electrode line is switched from the low level to the high level in a closing stage, so that the secondary inversion of the level is realized.

In an embodiment, when the scan signal of each scan line is in the off phase, controlling the common electrode voltage on the first common electrode line to perform a second low-high level flip switching, or the second high-low level flip switching includes:

Or when the data voltages of the sub-pixels in the nth row and the sub-pixels in the n+1th row are controlled to be positive, the common electrode voltage of the sub-pixels in the nth row is controlled to be switched from a high level to a low level, and the common electrode voltage of the sub-pixels in the n+1th row is controlled to be switched from the low level to the high level;

With reference to fig. 1, for convenience of understanding, the principle thereof is described in detail in connection with the above-described embodiments. In order to describe the voltage level variation and pixel brightness variation of the present embodiment in more detail, the present embodiment uses the mth column data line Dm, the mth column data linen rows of scan lines (G) _n 、G _n+1 ) Three first common electrode lines (n ^st Vst1、(n+1) ^st Vst2、(n+2) ^st The sub-pixel corresponding to Vst 1) is described as an example, and the pixel driving of the entire display panel is referred to in this embodiment, which is not described herein in detail.

Referring to fig. 3 and 5, in the first frame1 of the current driving period, the nth row scan line G is scanned to the nth row _n Start to work with the scanning line G _n Data voltage Data of Data lines of connected sub-pixels _m-n The polarity of (1) is positive, namely the Data voltage Data _m-n >A common electrode reference voltage Vcom and the scan line G _m-n After the pixel capacitance of two adjacent rows of sub-pixels is charged, the scanning line G _n Is turned off; the pixel holding voltage Vp on the sub-pixel connected to the nth row scanning line Gn of the mth column data line Dm is described with reference to the current frame pixel frame1 driving timing _{m-n_1} : at this time, a first common electrode line n connected to the sub-pixel ^st The loaded common electrode voltage Vst of Vst1 _n The pixel holding voltage Vpm-n_1 of the sub-pixel is changed from a relatively low level to a high level due to parasitic capacitance of the pixel, coupling effect among parasitic capacitance, storage capacitance and pixel capacitance, and the common electrode voltage Vst applied by the first common electrode line _n The voltage is boosted upward by DeltaV, i.e., the pixel hold voltage Vp, from a relatively low level to a high level _{m-n_1} The voltage difference with the common electrode reference voltage Vcom of the second common electrode line side is changed from x to x+Δv, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 3 and 6, in association with the scan line G _n Pixel holding voltage Vp of another row of connected subpixels _{m-n_2} A first common electrode line (n+1) connected to the sub-pixels ^st Voltage signal Vst applied to Vst2 _n+1 With adjacent first common electrode line n ^st Voltage signal Vst applied to Vst1 _n The polarity of the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively high level to a low level, at this time, the pixel holding voltage Vp of the sub-pixel is maintained due to coupling effects between the parasitic capacitance, the storage capacitance, and the pixel capacitance due to the parasitic capacitance of the pixel _{m-n_2} Will be due to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively high level to a low level reduces DeltaV, i.e., the pixel hold voltage Vp _{m-n_2} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δv, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 3 and 7, at the time of progressive scanning to the n+1th row, the n+1th row scanning line G _n+1 Start to work with the scanning line G _n+1 Data line Data of connected sub-pixels _m-n+1 The polarity of (1) is positive, namely the Data voltage Data _m-n+1 >A common electrode reference voltage Vcom and the scan line G _n+1 And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are turned off. Description will be made of the (n+1) th row scan line G with reference to the current frame pixel frame1 driving timing with the mth column data line Dm _n+1 Pixel holding voltage Vp of connected sub-pixels _{m-n+1_1} : at this time, the first common electrode line (n+1) connected to the sub-pixel ^st The applied voltage signal Vstn+1 of Vst2 _{_1} And the last adjacent sub-pixel Vp _{m-n_2} A first common electrode line is shared. The first common electrode voltage Vstn+1 is switched from a relatively high level to a low level, and the pixel holding voltage Vp of the sub-pixel is maintained due to parasitic capacitance of the pixel and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance _{m-n+1_1} Will be due to the voltage signal Vst applied by the common electrode line _n+1 Switching from a relatively high level to a low level reduces DeltaV, i.e. Vp _{m-n+1_1} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δv, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 3 and 8, in association with the scan line G _n+1 Pixel holding voltage Vp of another row of connected subpixels _{m-n+1_2} A first common electrode line (n+2) connected to the sub-pixels ^st Voltage signal Vst applied to Vst1 _n+2 Adjacent to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 The polarity of the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 Switching from a relatively low level to a high level, the pixel holding voltage Vp of the sub-pixel is maintained due to coupling effect among parasitic capacitance, storage capacitance, and pixel capacitance due to parasitic capacitance of the pixel _{m-n+1_2} Will be due to the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 By switching from a relatively low level to a high level to increase ΔV, i.e. Vp _m-n+2 The voltage difference with the common electrode reference voltage Vcom of the second common electrode line side is changed from x to x+Δv, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 4 and 5, in the second frame2 of the current driving period, the nth row scan line G is scanned to the nth row _n Start to work with the scanning line G _n Data line Data of connected sub-pixels _m-n The polarity of (a) is negative, namely the Data voltage Data _m-n <A common electrode reference voltage Vcom and the scan line G _m-n After the pixel capacitance of two adjacent rows of sub-pixels is charged, the scanning line G _n Is turned off. The pixel holding voltage Vp on the sub-pixel connected to the nth row scanning line of the mth column data line is described with reference to the current frame pixel frame2 driving timing _{m-n_1} : at this time, the common electrode voltage on the first common electrode line of the current frame is the same as the common electrode voltage of the previous frame in polarity, and therefore, on the scanning line G _m A first common electrode line n connected to the sub-pixel when the scan signal of the pixel is turned off ^st The loaded common electrode voltage Vst of Vst1 _n Switching from a relatively low level to a high level. Because the pixel has parasitic capacitance, and the parasitic capacitance, the storage capacitance and the pixel capacitance are coupled, the pixel holding voltage Vp of the sub-pixel _{m-n_1} Will be due to the first common electrode line n ^st Vst1 loaded common electrode voltageVstn is switched from relatively low to high to increase ΔV, i.e., the pixel hold voltage Vp _{m-n_1} The voltage difference between the common electrode reference voltage Vcom and the second common electrode line side is changed from-x to-x+Δv, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 4 and 6, the scanning line G is shown _n Pixel holding voltage Vp of another row of connected subpixels _{m-n_2} A first common electrode line (n+1) connected to the sub-pixels ^st Voltage signal Vst applied to Vst2 _{m-n_2} With adjacent first common electrode line n ^st Voltage signal Vst applied to Vst1 _n And the common electrode voltage on the first common electrode line of the current frame is the same polarity as the common electrode voltage of the previous frame, so the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively low level to a high level. At this time, the pixel holding voltage Vp of the sub-pixel is also due to parasitic capacitance of the pixel, and coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance _{m-n_2} Will be due to the voltage signal Vst applied by the second common electrode line _n+1 Switching from a relatively high level to a low level reduces DeltaV, i.e. Vp _{m-n_2} The voltage difference with the common electrode reference voltage Vcom of the second common electrode line side is changed from-x to-x- Δv, and the increase of the negative polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 4 and 7, at the time of progressive scanning to the n+1th row, the n+1th row scanning line G _n+1 Start to work with the scanning line G _n+1 Data line Data of connected sub-pixels _m-n+1 The polarity of (a) is negative, namely the Data voltage Data _m-n+1 <A common electrode reference voltage Vcom and the scan line G _n+1 After the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are turned off, and the (n+1) th row scanning line G of the mth row data line Dm is described with reference to the driving time sequence of the pixel frame2 of the current frame _n+1 Pixel holding voltage Vp of connected sub-pixels _{m-n+1_1} The sub-pixel shares a first common electrode line (n+1) with the last adjacent sub-pixel ^st Vst2. First common electrode voltage Vst _{n+1_1} Switching from a relatively high level to a low level, the pixel holding voltage Vp of the sub-pixel is due to parasitic capacitance of the sub-pixel and coupling effect among parasitic capacitance, storage capacitance and pixel capacitance _{m-n+1_1} Will be due to the voltage signal Vst applied by the common electrode line _n+1 Switching from a relatively low level to a high level reduces DeltaV, i.e. Vp _{m-n+1_1} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δv, and the decrease in the negative polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 4 and 8, in association with the scan line G _n+1 Pixel holding voltage Vp of another row of connected subpixels _{m-n+1_2} A first common electrode line (n+2) connected to the sub-pixels ^st Voltage signal Vst applied to Vst1 _n+2 Adjacent to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 The polarity of the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 Switching from a relatively high level to a low level, the pixel maintains the voltage Vp of the sub-pixel due to parasitic capacitance of the pixel, and coupling effect between parasitic capacitance, storage capacitance, and pixel capacitance _{m-n+1_2} Will be due to the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 By switching from a relatively high level to a low level to increase ΔV, i.e. Vp _{m-n+1_2} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x+Δv, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

In one embodiment, the data voltages on adjacent columns of data lines are opposite in polarity.

In this embodiment, the arrangement of the positive and negative polarities of the sub-pixels in the adjacent columns can be realized, and two sub-pixels in the same column in each pixel group are matched with two sub-pixels in the adjacent columns in the adjacent groups to connect a data line, so that the polarities of the two groups of sub-pixels in the same column are different, and the polarities of the two adjacent sub-pixels in the same row are also different. By the arrangement, the spatial resolution display of the display panel is increased, and the defect of visual character deviation of the display panel is overcome. The invention adopts the design of the common scanning line and the common electrode line, reduces half of scanning driving electrodes and common electrode driving electrodes, increases the effective aperture ratio of the display panel and improves the penetration rate.

In an embodiment, the driving method of the display panel further includes:

In this embodiment, it can be understood that the scanning manner of the gate driving circuit on the display panel is usually progressive scanning, so as to complete the pixel scanning of the sub-pixels of all rows, and when scanning to the sub-pixels of the current row, the pixel capacitor of each sub-pixel is charged. The polarity of the data voltage of the current group of two rows of sub-pixels is opposite to that of the data voltage of the next group of two rows of sub-pixels. For example, when the polarities of the data voltages of the two rows of the subpixels of the front group are positive (or negative), the data voltages of the two rows of the subpixels of the next group are switched to negative (or positive) when scanning to the two rows of the subpixels of the next group.

With reference to fig. 1, for convenience of understanding, the principle thereof is described in detail in connection with the above-described embodiments. In order to describe the voltage level change and pixel brightness change of the present embodiment in more detail, the present embodiment uses the mth column data line Dm, the nth row and the (n+1) th row scan lines (G _n 、G _n+1 ) Three first common electrode lines (n ^st Vst1、(n+1) ^st Vst2、(n+2) ^st The sub-pixel corresponding to Vst 1) is described as an example, and the pixel driving of the entire display panel is referred to in this embodiment, which is not described herein in detail.

Referring to fig. 3 and 5, in the first frame1 of the current driving period, the nth row scan line G is scanned to the nth row _n Start to work with the scanning line G _n Data line Data of connected sub-pixels _m-n The polarity of (1) is positive, namely the Data voltage Data _m-n >Common electrodeA reference voltage Vcom and the scan line G _m-n After the pixel capacitance of two adjacent rows of sub-pixels is charged, the scanning line G _n Is turned off; the pixel holding voltage Vp on the sub-pixel connected to the nth row scanning line Gn of the mth column data line Dm is described with reference to the current frame pixel frame1 driving timing _{m-n_1} : at this time, a first common electrode line n connected to the sub-pixel ^st The loaded common electrode voltage Vst of Vst1 _n The pixel holding voltage Vpm-n_1 of the sub-pixel is boosted by ΔV from the relatively low level to the high level due to the parasitic capacitance of the pixel, the parasitic capacitance, the storage capacitance, and the coupling effect _{m-n_1} The voltage difference with the common electrode reference voltage Vcom of the second common electrode line side is changed from x to x+Δv, and the increase of the positive polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 3 and 6, in association with the scan line G _n Pixel holding voltage Vp of another row of connected subpixels _{m-n_2} A first common electrode line (n+1) connected to the sub-pixels ^st Voltage signal Vst applied to Vst2 _n+1 With adjacent first common electrode line n ^st Voltage signal Vst applied to Vst1 _n The polarity of the voltage signal Vst applied to the first common electrode line Vst2 is opposite _n+1 At this time, the pixel is switched from a relatively high level to a low level, and the pixel holding voltage Vp of the sub-pixel is maintained due to coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance due to the existence of the parasitic capacitance of the pixel _{m-n_2} Will be due to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively high level to a low level reduces DeltaV, i.e., the pixel hold voltage Vp _{m-n_2} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x- Δv, and the decrease of the positive polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 3 and 7, in progressive scanning to the n+1th row At the time, the n+1th row scan line G _n+1 Starting to work, the scanning line is connected with a group of sub-pixel groups, and the polarities of the data voltages of the sub-pixel groups of the previous group and the sub-pixel group are switched to enable the data voltages to be connected with the scanning line G _n+1 Data line Data of connected sub-pixels _m-n+1 The polarity of (a) is negative, namely the Data voltage Data _m-n+1 <A common electrode reference voltage Vcom and the scan line G _n+1 And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are turned off. Description will be made of the (n+1) th row scan line G with reference to the current frame pixel frame1 driving timing with the mth column data line Dm _n+1 Pixel holding voltage Vp of connected sub-pixels _{m-n+1_1} : at this time, the sub-pixel and the last adjacent sub-pixel share a first common electrode line (n+1) ^st Vst2. First common electrode voltage Vst _n+1 Switching from a relatively high level to a low level, the pixel maintains the voltage Vp of the sub-pixel due to parasitic capacitance of the pixel and coupling effect between parasitic capacitance, storage capacitance and pixel capacitance _{m-n+1_1} Will be due to the voltage signal Vst applied by the common electrode line _{m-n+1_1} Switching from a relatively high level to a low level reduces DeltaV, i.e. Vp _{m-n+1_1} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from-x to-x- Δv, and the decrease in the negative polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 3 and 8, in association with the scan line G _n+1 Pixel holding voltage Vp of another row of connected subpixels _{m-n+1_2} A first common electrode line (n+2) connected to the sub-pixels ^st Voltage signal Vst applied to Vst1 _n+2 Adjacent to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 The polarity of the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 Switching from a relatively low level to a high level. At this time, due to the existence of parasitic capacitance in the pixel, the parasitic capacitance, the storage capacitance and the pixel capacitance are coupled to each other to maintain the pixel voltage Vp of the sub-pixel _{m-n+1_2} Will be due to the voltage signal Vst applied by the common electrode line _n+2 By switching from a relatively low level to a high level to increase ΔV, i.e. Vp _{m-n+1_2} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to-x+Δv, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 4 and 5, in the second frame2 of the current driving period, the nth row scan line G is scanned to the nth row _n Start to work with the scanning line G _n Data line Data of connected sub-pixels _m-n The polarity of (a) is negative, namely the Data voltage Data _m-n <A common electrode reference voltage Vcom and the scan line G _m-n After the pixel capacitance of two adjacent rows of sub-pixels is charged, the scanning line G _n Is turned off; description is made of the nth row scan line G with reference to the current frame pixel frame1 driving timing with the mth column data line Dm _n Pixel holding voltage Vp on connected sub-pixels _{m-n_1} : at this time, a first common electrode line n connected to the sub-pixel ^st Common electrode voltage Vst applied by Vst1 _n Switching from a relatively low level to a high level. Because of the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel _{m-n_1} Will be due to the first common electrode line n ^st Common electrode voltage Vst applied by Vst1 _n By switching from a relatively low level to a high level to increase ΔV, i.e. the pixel holding voltage Vp _{m-n_1} The voltage difference between the common electrode reference voltage Vcom and the second common electrode line side is changed from-x to-x+Δv, and the increase of the negative polarity voltage decreases the luminance of the sub-pixel.

Referring to fig. 4 and 6, the scanning line G is shown _m-n Pixel holding voltage Vp of another row of connected subpixels _{m-n_2} A first common electrode line (n+1) connected to the sub-pixels ^st Voltage signal Vst applied to Vst2 _n+1 With adjacent first common electrode line n ^st Voltage signal Vst applied to Vst1 _n And the common electrode voltage on each first common electrode line of the current frame is opposite to the first common electrode of the previous frameThe polarity of the polar voltages is the same, so the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively low level to a high level. Due to the existence of parasitic capacitance of the pixel and coupling effect among parasitic capacitance, storage capacitance and pixel capacitance, the pixel holding voltage Vp of the sub-pixel _{m-n_2} Will be due to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively high level to a low level reduces DeltaV, i.e. Vp _{m-n_2} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x+Δv, and the increase of the negative polarity voltage increases the luminance of the sub-pixel.

Referring to fig. 4 and 7, at the time of progressive scanning to the n+1th row, the n+1th row scanning line G _n+1 Starting to work, the scanning line is connected with a group of sub-pixel groups, and the polarities of the data voltages of the sub-pixel groups of the previous group and the sub-pixel group are switched to enable the data voltages to be connected with the scanning line G _n+1 Data line Data of connected sub-pixels _m-n+1 The polarity of (1) is positive, namely the Data voltage Data _m-n+1 >The common electrode reference voltage Vcom. Description will be made of the (n+1) -th row scan line G with reference to the current frame pixel frame2 driving timing and the mth column data line Dm _n+1 Pixel holding voltage Vp of connected sub-pixels _{m-n+1_1} At the scanning line G _n+1 And after the pixel capacitors of the two rows of connected sub-pixels are charged, the scanning signals are turned off. The sub-pixel and the last adjacent sub-pixel share a first common electrode line (n+1) ^st Vst2, the common electrode voltage on the first common electrode line of the current frame is the same as the common electrode voltage of the previous frame in polarity, the first common electrode voltage Vst _{m-n+1_1} Switching from a relatively high level to a low level. Because of the parasitic capacitance of the pixel and the coupling effect among the parasitic capacitance, the storage capacitance and the pixel capacitance, the pixel holding voltage Vp of the sub-pixel _{m-n+1_1} Will be due to the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _{m-n+1_1} Switching from relatively high to low reduces DeltaV, i.e. Vp _{m-n+1_1} Common electrode reference to the second common electrode line sideThe voltage difference between the voltages Vcom changes from x to x-DeltaV, and the decrease in positive polarity voltage decreases the brightness of the subpixel.

Referring to fig. 4 and 8, in association with the scan line G _n+1 Pixel holding voltage Vp of another row of connected subpixels _{m-n+1_2} A first common electrode line (n+2) connected to the sub-pixels ^st Voltage signal Vst applied to Vst1 _n+2 Adjacent to the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 The polarity of the first common electrode line (n+1) ^st Voltage signal Vst applied to Vst2 _n+1 Switching from a relatively low level to a high level, the pixel holding voltage Vp of the sub-pixel is then maintained due to parasitic capacitance of the pixel, and coupling effects between parasitic capacitance, storage capacitance, and pixel capacitance _{m-n+1_2} Will be due to the first common electrode line (n+2) ^st Voltage signal Vst applied to Vst1 _n+2 By switching from a relatively high level to a low level to increase ΔV, i.e. Vp _{m-n+1_2} The voltage difference with the common electrode reference voltage Vcom on the second common electrode line side is changed from x to x+Δv, and increasing the polarity voltage increases the luminance of the sub-pixel.

In an embodiment, the driving method of the display panel further includes:

and performing column inversion driving on each sub-pixel.

In this embodiment, each sub-pixel group includes two rows of sub-pixels, the two rows of sub-pixels are connected to a scan line, the storage capacitors of the two rows of sub-pixels are respectively connected to a driving architecture of a first common electrode line Vstn and vstn+1, and the data signals are matched with a column inversion mode, so that compared with dot inversion driving, the problem that positive and negative polarities of data voltages on the same data line need to be switched when the data voltages are scanned line by line, the distortion phenomenon of the data voltage signals is reduced due to the existence of parasitic capacitors of the pixels, and the problem that the data voltages of a source driver need to be continuously switched between positive polarity and negative polarity when the data voltages are scanned line by line is solved, and the display device generates larger power consumption due to higher voltage switching frequency, and possibly damages a driving chip due to overhigh temperature is avoided.

In an embodiment, the specific step of controlling the common electrode voltage level on the first common electrode line to switch between high and low after the pixel capacitors of the sub-pixels in the corresponding row are charged includes:

setting the first common electrode voltage to be a first level common electrode voltage after the pixel capacitance of the sub-pixel of the corresponding row is charged in a first frame of the current driving period; the common voltage is set to a second level common electrode electrical voltage in a second frame of the current driving period.

The first level common electrode voltage is a high level common electrode voltage, and the second level common electrode voltage is a low level common electrode voltage; or, the first level common electrode voltage is a low level common electrode voltage, and the second level common electrode voltage is a high level common electrode voltage.

In one embodiment, the voltages of two adjacent columns of data lines are opposite in polarity.

In this embodiment, the sub-pixels in the adjacent columns may implement arrangement of positive and negative polarities, and two sub-pixels in the same column in each pixel group are connected to one data line with two sub-pixels in the adjacent columns in the adjacent groups, so that polarities of two groups of sub-pixels in the same column are different, and polarities of two adjacent sub-pixels in the same row are also different. By the arrangement, the spatial resolution display of the display panel is increased, and the defect of visual character deviation of the display panel is overcome. The invention adopts the design of the common scanning line and the common electrode line, reduces half of scanning driving electrodes and common electrode driving electrodes, increases the effective aperture ratio of the display panel and improves the penetration rate.

In an embodiment, the driving method of the display panel further includes:

and performing column inversion driving on each sub-pixel.

In this embodiment, each sub-pixel group includes two rows of sub-pixels, the two rows of sub-pixels are connected to a scan line, and the storage capacitors of the two rows of sub-pixels are respectively connected to a driving architecture of a first common electrode line Vstn and vstn+1, and the data signal Datam is matched with a column inversion mode, so that compared with a dot inversion driving mode, the problem that the data voltage on the same data line needs to be switched in positive and negative polarities during progressive scanning, so that the distortion phenomenon of the data voltage signal is reduced due to the existence of parasitic capacitance of the pixel, and the problem that the data voltage of a source driver needs to be continuously switched between positive polarity and negative polarity during progressive scanning is solved, and the problem that the display device generates larger power consumption and possibly damages a driving chip due to overhigh temperature due to larger voltage switching frequency is solved.

two data lines connected with two adjacent sub-pixel groups in the same row are adjacent, and two data lines connected with two adjacent sub-pixel groups in the adjacent row are adjacent; the polarities of voltages on two adjacent first public electrode lines are opposite.

Wherein the polarities of voltages on the first common electrode lines (Vst 1, vst 2) respectively connected with the storage capacitors (Cst 1, cst 2) of the two rows of the sub-pixels are opposite; the polarities of the data voltages on the data lines (Dm-1, dm, dm+1) of two sub-pixels positioned in the same column in each group are the same, and the polarities of the voltages on the data lines (Dm-1, dm, dm+1) of two adjacent columns of the sub-pixels in the same row are opposite.

In this embodiment, a pixel array (not shown), scan lines (Gn, gn+1), data lines (Dm-1, dm, dm+1), a first common electrode line Vst1 and a second common electrode line Vcom are disposed on the display panel, and the pixel array includes a plurality of sub-pixels. Each sub-pixel comprises an active switch (thin film transistor), a pixel capacitor Clc and a storage capacitor Cst, wherein the grid electrode of the active switch is electrically connected with the scanning lines (Gn, gn+1) corresponding to the sub-pixel, the source electrode of the active switch is electrically connected with the data line D corresponding to the sub-pixel, the drain electrode of the active switch is electrically connected with the pixel capacitor Clc and one end of the storage capacitor Cst of the sub-pixel through the data line D, and the other end of each pixel capacitor Clc is electrically connected with the second common electrode line Vcom. In this embodiment, two rows of sub-pixels are defined as a group of sub-pixel groups 10, and the other ends of the storage capacitors Cst of the two sub-pixel groups 10 are respectively connected to a first common electrode line Vst1. Wherein each sub-pixel is divided into three sub-pixel groups 10 of red, green and blue. Three sub-pixels per red, green and blue constitute one pixel. The plurality of thin film transistors constitute the thin film transistor array of the present embodiment.

Referring to FIG. 1, in FIG. 1, gn, gn+1 are illustrated as two adjacent rows of scan lines, dm-1, dm, dm+1 are illustrated as three adjacent columns of data lines, n ^st Vst1、(n+1) ^st Vst2、(n+2) ^st Three adjacent first common electrode lines Vst1, clc1 and Clc2 represent pixel capacitances connected to the same scanning line in the same group, and Cst1 and Cst2 represent storage capacitances respectively connected to different first common motor lines in the same group.

The driving device of the display panel further includes:

a source driving circuit 20, wherein a plurality of output terminals of the source driving circuit 20 are connected to the data lines, and the source driving circuit 20 is configured to output a data voltage with positive and negative polarity switching to the data lines in a driving period of two frames;

a common electrode voltage circuit 50, wherein an output end of the common electrode voltage circuit 50 and each of the first common electrode lines, the common electrode voltage circuit 50 is configured to output a common electrode voltage having the same maintaining polarity as a common electrode voltage of a previous frame onto each of the first common electrode lines;

the driving apparatus of the display panel is further provided with a processor, a memory (not shown), and a driving program of the display panel stored on the memory and operable on the processor, the driving program of the display panel being configured to implement the steps of the driving method of the display panel as described above.

In this embodiment, the processor may be a timing controller 10, the timing controller 10 is connected to the source driving circuit 20 and the gate driving circuit 30 respectively to provide timing control signals for the source driving circuit 20 and the gate driving circuit 30, in this embodiment, the timing signals for controlling the data voltages on the data lines to switch between positive and negative polarities in a driving period of two frames are stored in the timing controller 10, in driving of each frame, the timing controller 10 receives the image data of the frame to be displayed sent by the front end, and the timing controller 10 converts the image data and the control signals received by the front end into data signals, control signals and clock signals suitable for the source driver 20 and the gate driver 30. The source driver 20 converts the received digital signals into corresponding gray scale voltage signals, and when the gate driver 30 scans the pixel row by row, all column data signal lines transmit data signals to the pixel row, charge each sub-pixel capacitor in the pixel row, so as to write and hold the signal voltage of the pixel, and the liquid crystal molecules of the sub-pixels rotate under the voltage, so that the transmittance of the incident light passing through the liquid crystal molecules is changed, namely, the light valve effect on the incident light is realized, the change of the brightness of the projection light is realized, and finally, the image display of the display panel 100 is realized. The signals Output to the gate driver include a frame Start Signal (STV), a scan clock signal (Clock Pulse Vertical, CPV), an Enable signal (OE), and the like.

The common electrode voltage circuit 50 is connected to a first common electrode line (n ^st Vst1、(n+1) ^st Vst2、(n+2) ^st Vst 1) is connected to the second common electrode line Vcom to supply the second common electrode line Vcom with a common electrode reference voltage, a common electrode voltageThe circuit 50 is also a first two adjacent common electrode lines (n ^st Vst1、(n+1) ^st Vst2、(n+2) ^st Vst 1) provides a common electrode voltage of opposite polarity, and the common electrode voltage circuit 50 also controls the common electrode voltages on adjacent two first common electrode lines to perform polarity inversion with two frames as a driving period.

Referring to fig. 2, in some embodiments, the memory may be implemented using EEPROM (Electrically Erasable Programmable read only memory, erasable memory) or Flash memory Flash. The memory, the timing controller 10, the common electrode circuit 50 may be disposed on a timing control (Timing Controller, TCON) PCB, and the memory may store control signals for driving the gate driver 20 and the source driver 30 to operate, and be communicatively connected with the timing controller 10 through a serial communication bus, and when the display device is powered on, the timing controller 10 reads the control signals in the memory and performs initial setting with other setting data to generate corresponding timing control signals, so as to drive the display panel 100 in the display device to operate, that is, the data stored in the memory is initialization data of the display panel 100.

In an embodiment, the driving device of the display panel further includes a gate driving circuit 30, and the gate driving circuit 30 is connected to the gate of each sub-pixel; the gate driving circuit 30 is configured to output a gate driving signal to each row of sub-pixels, so that the second common electrode and the data line are applied with corresponding voltages, and the sub-pixel capacitance of the corresponding row is charged.

Referring to fig. 2, in an embodiment, the driving circuit of the display panel further includes a gamma circuit 60 configured to generate multiple paths of gamma voltages and output the multiple paths of gamma voltages to the source driver 30, and the source driver 30 charges corresponding pixels according to the timing control signals and the gamma voltages output by the timing controller 10, so that the source driver 30 outputs data signals to the corresponding pixels to display a to-be-displayed image. The gamma circuit 60 may be implemented by a programmable gamma chip or by a resistor string, a memory, or other discrete components, and may generate a set of gamma voltages (vγ1 to vγ14) that may each be used as a pixel gray scale reference voltage.

Referring to fig. 5, in an embodiment, the display panel 100 further includes:

the first substrate 110 has a display area AA and a peripheral area, i.e. a non-display area BB; the pixel array 140 is disposed on the first substrate 110 and located in the display area AA; the N cascade-arranged array substrate row driving circuits 10 and auxiliary circuits 20 are disposed on the first substrate 110 and located in the peripheral area;

A second substrate 120 disposed opposite to the first substrate 110;

the liquid crystal layer 130 is disposed between the first substrate 110 and the second substrate, the liquid crystal layer 130 includes a plurality of liquid crystal molecules, and the pixel array 140 is configured to control the actions of the plurality of liquid crystal molecules.

In this embodiment, the first substrate 110 and the second substrate are both generally transparent substrates such as glass substrates or plastic substrates. The second substrate is disposed opposite to the first substrate 110, and a corresponding circuit may be disposed between the first substrate 110 and the second substrate. The first substrate 110 is an array substrate, the second substrate is a color film substrate, and the first substrate 110 and the second substrate may be flexible transparent substrates. The pixel array 140 is disposed on the first substrate 110 and located in the display area AA.

It can be understood that in the above embodiment, the display panel 100 further includes a sealant 150 disposed in the display area BB between the first substrate 110 and the second substrate 120 and surrounding the liquid crystal layer 130, and the array substrate row driving circuit 10 is disposed between the sealant 150 and the display area AA. The sealant 150 may be coated on the first substrate 110 or the second substrate 120 using a sealant to connect the first substrate 110 and the second substrate 120, thereby implementing an assembly process of the display panel 100.

The display panel is classified into an SOC (System on chip) type and a GOA (Gate driver on array, gate driver on array substrate, or array substrate row driving circuit) type by Gate driver design (gate driver design). GOA replaces a process technology of a driving chip made of an external silicon wafer because it directly makes a Gate driving circuit 30 (Gate driver IC) on an Array (Array) substrate of a display device. The application of the technology can reduce the production process program, reduce the product process cost and improve the integration level of the display panel. With the development of the display screen of the liquid crystal television and the computer towards the oversized and high-resolution directions, more and more liquid crystal display panels adopt narrow frame designs so as to increase the display area of the display screen.

The GOA is generally disposed at a side frame of the display panel, and a gate line scanning driving signal circuit is fabricated on an array substrate of the display panel by using a thin film transistor (Thin Film Transistor, TFT) liquid crystal display array process, so as to realize a progressive scanning driving mode for the gate, and has the advantages of reducing production cost and realizing a narrow frame design of the panel, and is used for various displays. In an exemplary architecture of the GOA-type display panel, LC (Liquid Crystal) molecules are filled between upper and lower glass substrates and the periphery is sealed with a sealing material; among them, liquid crystal is a polymer material, and is widely used in light and thin display technology because of its special physical, chemical and optical properties. According to the different sizes of the display panels, the GOA circuits can be arranged on one side of the display panels, can also be arranged on two side edges of the display panels, and can drive one row of sub-pixels to be conducted simultaneously or alternatively control each row of sub-pixels to be conducted when the GOA circuits are arranged on the two side edges of the display panels.

The invention also comprises a display device which comprises a display panel and the driving device of the display panel, wherein the driving device of the display panel is connected with each sub-pixel of the display panel. The detailed structure of the driving device of the display panel can refer to the above embodiments, and will not be described herein again; it can be understood that, since the driving device of the display panel is used in the display device of the present invention, the embodiments of the display device of the present invention include all the technical schemes of all the embodiments of the driving device of the display panel, and the achieved technical effects are identical, and are not repeated herein.

In the above embodiments, the display panel includes, but is not limited to, a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, a curved panel, and the liquid crystal panel includes a thin film transistor liquid crystal display panel, a TN panel, a VA panel, an IPS panel, and the like.

The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the invention.

Claims

1. A driving method of a display panel, the display panel comprising:

and controlling the common electrode voltage on each first common electrode line to be in the same polarity with the common electrode voltage of the previous frame.

2. The method of driving a display panel according to claim 1, wherein the scanning signal on each of the scanning lines in each frame includes an on-period and an off-period;

3. The method of driving a display panel according to claim 2, wherein the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level inversion switching when the scan signal of each of the scan lines is in the off-state comprises:

4. The method of driving a display panel according to claim 2, wherein the step of controlling the common electrode voltage on the first common electrode line to perform the second high-low level inversion switching when the scanning signal of each of the scanning lines is in the off-state comprises:

5. The display panel driving method according to claim 2, wherein the display panel driving method further comprises:

6. The method of driving a display panel according to claim 1, wherein the polarities of the data voltages on two adjacent columns of data lines are opposite.

7. The driving method of a display panel according to any one of claims 1 to 5, further comprising:

and driving the same polarity on the same data line, and forming dot inversion driving for each group of sub-pixels of the display panel.

8. A driving device of a display panel, the display panel comprising:

the polarities of the voltages on the adjacent two first public electrode lines are opposite, and the polarities of the data voltages on the data lines of the sub-pixels in each group on the same data line are the same; the driving device of the display panel includes:

the driving device of the display panel is further provided with a processor, a memory and a driving program of the display panel stored on the memory and operable on the processor, the driving program of the display panel being configured to implement the steps of the driving method of the display panel as claimed in any one of claims 1 to 7.

9. The driving device of the display panel according to claim 8, further comprising a gate driving circuit connected to the gate of each of the sub-pixels; the grid driving circuit is configured to output grid driving signals to the sub-pixels in each row, so that corresponding voltages are applied to the second common electrode and the data line, and the sub-pixel capacitors in the corresponding row are charged;

the driving device of the display panel further comprises a time sequence controller which is respectively connected with the grid driving circuit and the source driving circuit; the timing controller is configured to output a timing control signal to the gate driving circuit and the source driving circuit.

10. A display device comprising a display panel and a drive device for the display panel according to any one of claims 8 or 9, the drive device for the display panel being connected to each sub-pixel of the display panel.