CN113299561B - Preparation method of cavity bottom glue overflow preventing structure - Google Patents
Preparation method of cavity bottom glue overflow preventing structure Download PDFInfo
- Publication number
- CN113299561B CN113299561B CN202110557075.XA CN202110557075A CN113299561B CN 113299561 B CN113299561 B CN 113299561B CN 202110557075 A CN202110557075 A CN 202110557075A CN 113299561 B CN113299561 B CN 113299561B
- Authority
- CN
- China
- Prior art keywords
- cavity
- glue
- silicon wafer
- chip
- tsv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003292 glue Substances 0.000 title claims abstract description 61
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 68
- 239000010703 silicon Substances 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000011049 filling Methods 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 26
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 239000000084 colloidal system Substances 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims abstract description 7
- 230000009471 action Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000000945 filler Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 229910052716 thallium Inorganic materials 0.000 claims description 2
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 description 24
- 230000001070 adhesive effect Effects 0.000 description 24
- 238000010586 diagram Methods 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011135 tin Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4817—Conductive parts for containers, e.g. caps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a cavity bottom glue overflow preventing structure, which comprises the following steps: manufacturing a TSV metal column on the surface of the silicon wafer, temporarily bonding one surface of an opening of the TSV metal column, and thinning the back surface of the silicon wafer; manufacturing a passivation layer on the surface of a silicon wafer, and forming a cavity with a step structure, wherein TSV metal columns are exposed from the bottom of the cavity; coating insulating filling glue on the edge of the cavity, and filling conductive glue on the bottom of the cavity; and heating the bottom of the silicon wafer, mounting the chip after the colloid is softened and tightly combined at the bottom of the cavity, and applying pressure to the chip to overflow the colloid and fill the gap between the chip and the cavity, thereby completing the embedding action of the chip. The invention forms a cavity with a ladder structure at the bottom of the cavity just like forming a fence, conductive glue is used in the fence, insulating filling glue is used at the outer ring of the fence, a chip is embedded and extruded to uniformly fill the conductive glue at the bottom, and overflowed glue is blocked by the insulating filling glue and distributed around the chip, so that the overflow of the glue is avoided.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a cavity bottom glue overflow preventing structure.
Background
Currently, millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, is widely applied to the fields of high-speed data communication, automobile radar, airborne missile tracking systems, space spectrum detection, imaging and the like, and is expected to reach 11 hundred million dollars in 2018 market, so that the millimeter wave radio frequency technology becomes an emerging industry. New applications place new demands on the electrical performance, compact structure and system reliability of the product, and for wireless transmitting and receiving systems, it is not currently possible to integrate them on the same chip (SOC), so that it is necessary to integrate different chips, including radio frequency units, filters, power amplifiers, etc., into a single system to realize the functions of transmitting and receiving signals.
However, the rf module needs to use bottom interconnection and grounding, so that a cavity needs to be made on the surface of the interposer, and the bottom of the cavity is provided with an interconnection and grounding TSV structure, so that the bottom of the chip is communicated with the outside, and the bottom of the chip is solidified by solder paste or conductive adhesive. In actual operation, the sizes of the chips are different, and if the glue applied to the bottoms of the chips is too small, bottom cavities can appear, which is not beneficial to subsequent processes and large-area grounding and interconnection of the chips. If the glue is more, the glue overflows, and if the glue overflows to the side wall of the chip, the problem of short circuit can occur.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a preparation method of a cavity bottom glue overflow preventing structure. According to the preparation method, the fence is arranged at the bottom of the cavity, the conductive adhesive is used in the fence, the insulating filling adhesive is used for the outer ring of the fence, the chip is embedded in the bottom of the cavity and extruded to uniformly fill the conductive adhesive in the bottom of the cavity, and overflowed adhesive is blocked by the insulating filling adhesive and distributed around the chip, so that the problem of adhesive overflow can be avoided.
In order to solve the defects in the prior art, the invention adopts the following technical scheme: a preparation method of a cavity bottom glue overflow preventing structure comprises the following steps:
s1, manufacturing a TSV metal column on the surface of a silicon wafer, temporarily bonding the surface of an opening of the TSV metal column, and thinning the back surface of the silicon wafer;
s2, manufacturing a passivation layer on the surface of the silicon wafer, and forming a cavity with a step structure on the back surface of the silicon wafer by adopting an etching process, so that the TSV metal column is exposed from the bottom of the cavity;
step S3, coating insulating filling glue on the edge of the cavity, and filling conductive glue on the bottom of the cavity;
and S4, heating the bottom of the silicon wafer, attaching a chip at the bottom of the cavity after the colloid is softened and tightly combined with the bottom of the cavity, and applying pressure to the chip to overflow the colloid and fill the gap between the chip and the cavity until the gap is filled, thereby completing the embedding action of the chip.
Further, the forming of the TSV metal column comprises the following steps:
A. manufacturing TSV blind holes on the surface of the silicon wafer through photoetching or/and etching technology, wherein the diameter of each hole is 1-1000 mu m, and the depth is 10-1000 mu m;
B. forming a passivation layer above the silicon wafer, wherein the thickness of the passivation layer is 10 nm-100 mu m;
C. manufacturing a seed layer above the passivation layer through physical sputtering, magnetron sputtering or evaporation process;
D. electroplating to fill the TSV blind holes with metal, densifying the metal at 200-500 ℃ to densify the metal, and removing the metal on the surface of the silicon wafer, so that only filler metal, namely TSV metal columns, remains on the surface of the silicon wafer.
Further, the seed layer is one or more layers, the thickness is 1-nm-100 μm, and the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel.
Further, the thickness of the back of the silicon wafer is 10-700 mu m.
Further, the cavity with the step structure is formed by adopting the following method:
A. etching a cavity on the back of the silicon wafer, wherein the depth of the cavity is 10-700 mu m;
B. and continuously manufacturing a groove at the bottom of the cavity to expose the bottom of the TSV metal column in the cavity, wherein the depth of the groove is 10-100 mu m.
Further, the insulating filling glue is photoresist or epoxy resin glue, and the thickness of the glue is 10-50 mu m.
Further, the conductive adhesive is nano silver paste or soldering tin material, and the thickness of the adhesive is 10-50 mu m.
Compared with the prior art, the invention has the following advantages:
according to the preparation method, the grooves are formed in the bottom of the cavity, the grooves and the cavity are provided with the fences as if the depth is different, the conductive adhesive is filled in the inner grooves, namely the fences, the outer ring grooves, namely the outer rings of the fences, are coated with the insulating filling adhesive, the chips are embedded in the bottom of the cavity and extruded to uniformly fill the conductive adhesive in the bottom of the cavity, and overflowed conductive adhesive is blocked by the insulating filling adhesive and distributed around the chips, so that the problem of colloid overflow can be avoided.
Drawings
Fig. 1a is a schematic diagram of a structure for forming TSV blind holes on a surface of a silicon wafer in embodiment 1 of the present invention.
FIG. 1b is a schematic diagram of the structure of a seed layer formed on the surface of a silicon wafer in example 1 of the present invention.
Fig. 1c is a schematic diagram of a structure of a TSV metal pillar formed on a silicon wafer surface in embodiment 1 of the present invention.
FIG. 1d is a schematic diagram of the structure for removing the seed layer on the surface of the silicon wafer in example 1 of the present invention.
Fig. 1e is a schematic view of the structure of the cavity with the stepped structure formed in embodiment 1 of the present invention.
Fig. 1f is a schematic structural diagram of the cavity of embodiment 1 of the present invention after the insulating filling glue and the conductive glue are coated.
FIG. 1g is a schematic diagram of the structure of the embodiment 1 of the present invention in which the gel is tightly bonded to the bottom of the cavity after heating.
Fig. 1h is a schematic diagram of a structure of a cavity bottom mounted chip in embodiment 1 of the present invention.
FIG. 1i is a schematic diagram of the structure of the chip according to embodiment 1 of the present invention after applying pressure.
Fig. 1j is a schematic diagram of the structure of the chip after being embedded in embodiment 1 of the present invention.
Reference numerals illustrate: 101-a silicon wafer; 102-TSV blind holes; 103-seed layer; 104-TSV metal columns; 105-cavity; 106-conductive adhesive; 107-insulating filling glue; 108-chip; 109-grooves.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
Furthermore, repeated reference numerals or designations may be used in the various embodiments. These repetition are for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Reference numerals referring to steps in the various embodiments of the invention are merely for convenience of description and do not substantially follow a sequential order. Different steps in each specific embodiment can be combined in different sequences, so that the aim of the invention is fulfilled.
Example 1
A preparation method of a cavity bottom glue overflow preventing structure comprises the following steps:
step S1, manufacturing a TSV metal column 104 on the surface of a silicon wafer 101, temporarily bonding one surface of an opening of the TSV metal column 104, and then thinning the back surface of the silicon wafer 101;
as shown in fig. 1a, a TSV blind hole 102 is manufactured on the surface of a silicon wafer 101 through photoetching and etching processes, wherein the diameter of the TSV blind hole 102 is 10 μm, and the depth is 50 μm;
forming a passivation layer above the silicon wafer 101, wherein the passivation layer is formed by adopting a direct thermal oxidation method, and the thickness of the passivation layer is 100 nm;
as shown in fig. 1b, a seed layer 103 is fabricated by physical sputtering over the passivation layer, the seed layer 103 having a thickness of 100 a nm a layer of copper;
as shown in fig. 1c, copper is electroplated to fill TSV blind via 102 with copper metal and densified to make copper denser at 300 ℃;
as shown in fig. 1d, a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP for short) is adopted to remove copper on the surface of the silicon wafer, so that only copper filling is left on the surface of the silicon wafer, and thus the TSV metal column 104 is formed;
performing temporary bonding on one surface of the opening of the TSV metal column 104, and then thinning the back surface of the silicon wafer 101 to 600 mu m;
step S2, manufacturing a passivation layer on the surface of the silicon wafer 101, and forming a cavity 105 with a step structure on the back surface of the silicon wafer 101 by adopting an etching process, so that the TSV metal column 104 is exposed from the bottom of the cavity 105;
as shown in fig. 1e, a silicon oxide insulating layer is manufactured on the surface of a silicon wafer, and then a cavity 105 is etched on the back surface of the silicon wafer 101 by using photoetching and dry etching processes, wherein the depth of the cavity 105 is 100 μm;
continuing to manufacture a pattern groove 109 at the bottom of the cavity 105 by using photoetching and dry etching processes, so that the bottom of the TSV metal column 104 in the cavity is exposed, and the depth of the groove 109 is 10 mu m;
step S3, coating insulating filling glue 107 on the edge of the cavity 105, and filling conductive glue 106 on the bottom of the cavity;
as shown in fig. 1f, insulating filling glue 107 is coated on the edge of the cavity 105, the thickness of the glue is 20 μm, and the glue is photoresist;
filling conductive adhesive 106 at the bottom of the cavity, wherein the thickness of the adhesive is 20 mu m, and the adhesive is nano silver paste;
and S4, heating the bottom of the silicon wafer 101, attaching a chip 108 to the bottom of the cavity 105 after the colloid is softened and tightly combined with the bottom of the cavity 105, and applying pressure to the chip 108 to overflow the colloid and fill the gap between the chip 108 and the cavity 105 until the gap is filled, thereby completing the embedding action of the chip 108.
As shown in FIG. 1g, the bottom of the silicon wafer 101 is heated to soften the gel and tightly bond to the bottom of the cavity 105;
as shown in fig. 1h, a chip 108 is mounted on the bottom of the cavity 105;
as shown in fig. 1i and 1j, pressure is applied to the chip 108, so that the glue overflows and fills the gap between the chip 108 and the cavity 105 until the gap is filled, and the embedding operation of the chip 108 is completed.
Example 2
A preparation method of a cavity bottom glue overflow preventing structure comprises the following steps:
step S1, manufacturing a TSV metal column 104 on the surface of a silicon wafer 101, temporarily bonding one surface of an opening of the TSV metal column 104, and then thinning the back surface of the silicon wafer 101;
manufacturing TSV blind holes 102 on the surface of a silicon wafer 101 through photoetching and etching processes, wherein the diameter of each TSV blind hole 102 is 100 mu m, and the depth is 300 mu m;
depositing silicon oxide above the silicon wafer 101 to form a passivation layer, wherein the thickness of the passivation layer is 10 mu m;
manufacturing a seed layer 103 above the passivation layer by a magnetron sputtering process, wherein the thickness of the seed layer 103 is 10 mu m, and the seed layer is a layer of aluminum;
electroplating copper to fill the TSV blind via 102 with copper metal and densifying the copper at 400 ℃ to make the copper denser;
removing copper on the surface of the silicon wafer by adopting a CMP process, so that only copper filling is left on the surface of the silicon wafer, and forming a TSV metal column 104;
performing temporary bonding on one surface of the opening of the TSV metal column 104, and then thinning the back surface of the silicon wafer 101 to 400 mu m;
step S2, manufacturing a passivation layer on the surface of the silicon wafer 101, and forming a cavity 105 with a step structure on the back surface of the silicon wafer 101 by adopting an etching process, so that the TSV metal column 104 is exposed from the bottom of the cavity 105;
manufacturing a silicon oxide insulating layer on the surface of a silicon wafer, and etching a cavity 105 on the back surface of the silicon wafer 101 by using photoetching and dry etching processes, wherein the depth of the cavity 105 is 400 mu m;
continuing to manufacture a pattern groove 109 at the bottom of the cavity 105 by using photoetching and dry etching processes, so that the bottom of the TSV metal column 104 in the cavity is exposed; the depth of the groove 109 is 50 μm;
step S3, coating insulating filling glue 107 on the edge of the cavity 105, and filling conductive glue 106 on the bottom of the cavity;
coating insulating filling glue 107 at the edge of the cavity 105, wherein the thickness of the glue is 30 mu m, and the glue is epoxy resin glue;
the bottom of the cavity 105 is filled with conductive adhesive 106, the thickness of the adhesive is 30 mu m, and the adhesive is solder;
and S4, heating the bottom of the silicon wafer 101, attaching a chip 108 to the bottom of the cavity 105 after the colloid is softened and tightly combined with the bottom of the cavity 105, and applying pressure to the chip 108 to overflow the colloid and fill the gap between the chip 108 and the cavity 105 until the gap is filled, thereby completing the embedding action of the chip 108.
Example 3
A preparation method of a cavity bottom glue overflow preventing structure comprises the following steps:
step S1, manufacturing a TSV metal column 104 on the surface of a silicon wafer 101, temporarily bonding one surface of an opening of the TSV metal column 104, and then thinning the back surface of the silicon wafer 101;
manufacturing TSV blind holes 102 on the surface of a silicon wafer 101 through photoetching and etching processes, wherein the diameter of each TSV blind hole 102 is 800 mu m, and the depth is 1000 mu m;
depositing silicon nitride above the silicon wafer 101 to form a passivation layer, wherein the thickness of the passivation layer is 80 mu m;
the seed layer 103 is manufactured above the insulating layer through an evaporation process, the thickness range of the seed layer 103 is 90 mu m, the seed layer can be three layers, and the metal materials from top to bottom are respectively copper, tin and nickel, and the thicknesses of the layers are the same;
electroplating copper to enable copper metal to be filled in the TSV blind holes 102, and enabling copper to be more compact through densification at 450 ℃;
removing copper on the surface of the silicon wafer by adopting a CMP process, so that only copper filling is left on the surface of the silicon wafer, and forming a TSV metal column 104;
performing temporary bonding on one surface of the opening of the TSV metal column 104, and then thinning the back surface of the silicon wafer 101 to 100 mu m;
step S2, manufacturing a passivation layer on the surface of the silicon wafer 101, and forming a cavity 105 with a step structure on the back surface of the silicon wafer 101 by adopting an etching process, so that the TSV metal column 104 is exposed from the bottom of the cavity 105;
manufacturing a silicon oxide insulating layer on the surface of a silicon wafer, and etching a cavity 105 on the back surface of the silicon wafer 101 by using photoetching and dry etching processes, wherein the depth of the cavity 105 is 600 mu m;
continuing to manufacture a pattern groove 109 at the bottom of the cavity 105 by using photoetching and dry etching processes, so that the bottom of the TSV metal column 104 in the cavity is exposed; the depth of the groove 109 is 80 μm;
step S3, coating insulating filling glue 107 on the edge of the cavity 105, and filling conductive glue 106 on the bottom of the cavity;
coating insulating filling glue 107 on the edge of the cavity 105, wherein the thickness of the glue is 50 mu m, and the glue is epoxy resin glue;
filling conductive adhesive 106 at the bottom of the cavity 105, wherein the thickness of the adhesive is 50 mu m, and the adhesive is nano silver paste;
and S4, heating the bottom of the silicon wafer 101, attaching a chip 108 to the bottom of the cavity 105 after the colloid is softened and tightly combined with the bottom of the cavity 105, and applying pressure to the chip 108 to overflow the colloid and fill the gap between the chip 108 and the cavity 105 until the gap is filled, thereby completing the embedding action of the chip 108.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (7)
1. The preparation method of the cavity bottom glue overflow preventing structure is characterized by comprising the following steps of:
step S1, manufacturing a TSV metal column (104) on the surface of a silicon wafer (101), temporarily bonding the surface of an opening of the TSV metal column (104), and then thinning the back surface of the silicon wafer (101);
s2, manufacturing a passivation layer on the surface of the silicon wafer (101), and forming a cavity (105) with a stepped structure on the back of the silicon wafer (101) by adopting an etching process, so that the TSV metal column (104) is exposed from the bottom of the cavity (105);
step S3, coating insulating filling glue (107) on the edge of the cavity (105), and filling conductive glue (106) on the bottom of the cavity (105);
and S4, heating the bottom of the silicon wafer (101), after the colloid is softened and tightly combined at the bottom of the cavity (105), attaching a chip (108) at the bottom of the cavity (105), applying pressure to the chip (108), overflowing the colloid, filling a gap between the chip (108) and the cavity (105) until the gap is filled, and completing the embedding action of the chip (108).
2. The method for preparing the cavity bottom glue overflow preventing structure according to claim 1, wherein the forming of the TSV metal column (104) comprises the steps of:
A. manufacturing TSV blind holes (102) on the surface of the silicon wafer (101) through photoetching or/and etching technology, wherein the diameter of each hole is 1-1000 mu m, and the depth is 10-1000 mu m;
B. forming a passivation layer over the silicon wafer (101), wherein the thickness of the passivation layer is 10 nm-100 mu m;
C. manufacturing a seed layer (103) above the passivation layer through physical sputtering, magnetron sputtering or evaporation process;
D. electroplating to fill the TSV blind holes (102) with metal, densifying the metal at 200-500 ℃ to densify the metal, and removing the metal on the surface of the silicon wafer (101) so that only filler metal, namely TSV metal columns (104), remains on the surface of the silicon wafer (101).
3. The method for preparing the cavity bottom glue overflow preventing structure according to claim 2, wherein the seed layer (103) is one or more layers, the thickness is 1-nm-100 μm, and the material is one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel.
4. The method for preparing the cavity bottom glue overflow preventing structure according to claim 1, wherein the thickness of the back surface of the silicon wafer (101) is 10-700 μm.
5. The method for preparing the cavity bottom glue overflow preventing structure according to claim 1, wherein the cavity (105) with the step structure is formed by adopting the following method:
A. etching a cavity (105) on the back surface of the silicon wafer (101), wherein the depth of the cavity (105) is 10-700 mu m;
B. and continuously manufacturing a groove (109) at the bottom of the cavity (105) to expose the bottom of the TSV metal column (104) in the cavity (105), wherein the depth of the groove (109) is 10-100 mu m.
6. The method for preparing the cavity bottom anti-overflow glue structure according to claim 1, wherein the insulating filling glue (107) is photoresist or epoxy resin glue, and the glue thickness is 10-50 μm.
7. The method for preparing the cavity bottom glue overflow preventing structure according to claim 1, wherein the conductive glue (106) is nano silver paste or soldering tin material, and the thickness of the glue is 10-50 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110557075.XA CN113299561B (en) | 2021-05-21 | 2021-05-21 | Preparation method of cavity bottom glue overflow preventing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110557075.XA CN113299561B (en) | 2021-05-21 | 2021-05-21 | Preparation method of cavity bottom glue overflow preventing structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113299561A CN113299561A (en) | 2021-08-24 |
| CN113299561B true CN113299561B (en) | 2023-06-27 |
Family
ID=77323570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110557075.XA Active CN113299561B (en) | 2021-05-21 | 2021-05-21 | Preparation method of cavity bottom glue overflow preventing structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113299561B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114361052A (en) * | 2021-11-30 | 2022-04-15 | 航天科工微系统技术有限公司 | Sintering process of nano-silver conductive adhesive with low voidage and high thermal conductivity |
| CN114388366B (en) * | 2022-03-22 | 2022-05-31 | 湖北江城芯片中试服务有限公司 | Preparation method of packaging shell and preparation method of packaging chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999030362A1 (en) * | 1997-12-08 | 1999-06-17 | Minnesota Mining And Manufacturing Company | Method and apparatuses for making z-axis electrical connections |
| FR2786317A1 (en) * | 1998-11-24 | 2000-05-26 | Gemplus Card Int | Flush contact chip card production comprises etching connection terminal contact pads in a continuous metallic strip on which the chip is mounted |
| FR2905494A1 (en) * | 2006-09-05 | 2008-03-07 | Oberthur Card Syst Sa | ELECTRONIC DEVICE WITH INTEGRATED CIRCUIT MODULE AND ANTENNA CONNECTED BY CAPACITIVE ELECTRICAL CONNECTIONS |
| WO2008146487A1 (en) * | 2007-05-29 | 2008-12-04 | Panasonic Corporation | Circuit board and method for manufacturing the same |
| CN107112290A (en) * | 2014-08-06 | 2017-08-29 | 伊文萨思公司 | Apparatus and method for for the underfill may that localizes |
-
2021
- 2021-05-21 CN CN202110557075.XA patent/CN113299561B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999030362A1 (en) * | 1997-12-08 | 1999-06-17 | Minnesota Mining And Manufacturing Company | Method and apparatuses for making z-axis electrical connections |
| FR2786317A1 (en) * | 1998-11-24 | 2000-05-26 | Gemplus Card Int | Flush contact chip card production comprises etching connection terminal contact pads in a continuous metallic strip on which the chip is mounted |
| FR2905494A1 (en) * | 2006-09-05 | 2008-03-07 | Oberthur Card Syst Sa | ELECTRONIC DEVICE WITH INTEGRATED CIRCUIT MODULE AND ANTENNA CONNECTED BY CAPACITIVE ELECTRICAL CONNECTIONS |
| WO2008146487A1 (en) * | 2007-05-29 | 2008-12-04 | Panasonic Corporation | Circuit board and method for manufacturing the same |
| CN107112290A (en) * | 2014-08-06 | 2017-08-29 | 伊文萨思公司 | Apparatus and method for for the underfill may that localizes |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113299561A (en) | 2021-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111312697B (en) | Three-dimensional stacking integrated structure, multi-chip integrated structure and preparation method thereof | |
| CN111293078B (en) | Method for embedding chip into cavities on front surface and back surface of adapter plate | |
| CN110010548B (en) | Manufacturing method of cavity structure with bonding pad at bottom | |
| US20160118705A1 (en) | Packaged integrated circuit waveguide interface and methods thereof | |
| TW202038423A (en) | Fan-out antenna package and packaging method for the same | |
| CN101656244A (en) | Multilayer interconnection packaging structure of silica-based embedded microwave multi chip module and manufacturing method | |
| CN113299561B (en) | Preparation method of cavity bottom glue overflow preventing structure | |
| CN112820721B (en) | Integrated packaging antenna and packaging method thereof | |
| CN111968943B (en) | Ultra-thin stacking method for radio frequency modules | |
| CN111799188B (en) | Thinning wafer packaging technology utilizing TSV and TGV | |
| CN111243970A (en) | Chip embedding process in cavity | |
| CN111968941B (en) | Wafer-level patch interconnection mode | |
| CN110010504B (en) | Manufacturing process of radio frequency module with electromagnetic shielding function | |
| CN110010480B (en) | Wafer-level radio frequency chip electromagnetic shielding packaging process | |
| CN111341668A (en) | Method for embedding radio frequency chip in silicon cavity | |
| CN110648962A (en) | Elbow interconnecting metal filling method | |
| CN111370316A (en) | Six-surface surrounding embedded packaging method | |
| CN113161306B (en) | Efficient heat dissipation structure of chip and preparation process thereof | |
| CN111370317B (en) | Chip embedding method using silicon cavity as carrier plate | |
| CN110010499B (en) | Radio frequency chip system-in-package process with electromagnetic shielding function | |
| CN113990763A (en) | Chip packaging structure based on electroforming technology and packaging method thereof | |
| CN112992851A (en) | Adapter plate and preparation method thereof | |
| CN113629019A (en) | Millimeter wave packaging structure and preparation method thereof | |
| US11862584B2 (en) | High dielectric constant carrier based packaging with enhanced WG matching for 5G and 6G applications | |
| CN114446867A (en) | Copper electrode structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |