CN113261103A - Thin film transistor, manufacturing method thereof, driving circuit and display screen - Google Patents
Thin film transistor, manufacturing method thereof, driving circuit and display screen Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 33
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
A thin film transistor (10), a method of manufacturing the same, a driving circuit (100), and a display panel (1000). The thin film transistor (10) comprises a substrate (11), a first annular grid electrode (12) formed on the substrate (11), a buffer layer (13) covering the substrate (11) and the first grid electrode (12), an active layer (14) formed on the buffer layer (13), an annular grid electrode insulating layer (15) formed on the active layer (14), an annular second grid electrode (16) formed on the grid electrode insulating layer (15), an interlayer dielectric (17) covering the active layer (14) and the second grid electrode (16), and a drain electrode (18) and a source electrode (19) formed on the interlayer dielectric (17). The interlayer dielectric (17) is formed with a first opening (172) and a second opening (174). The drain electrode (18) is connected to the active layer (14) through the first opening (172). The source electrode (19) is connected to the active layer (14) through the second opening (174).
Description
The present invention relates to electronic technologies, and in particular, to a thin film transistor, a method for manufacturing the thin film transistor, a driving circuit of a display panel, and a display panel.
Thin Film Transistor (TFT) is widely used in driving circuit of Active-matrix organic light-emitting diode (AMOLED) display panelIn the way. However, TFTs have drain-source current (I)DS) The AMOLED display screen has the problems of low brightness and nonuniform brightness due to the problems of low drain-source current fluctuation.
Disclosure of Invention
The embodiment of the invention provides a thin film transistor, a manufacturing method of the thin film transistor, a driving circuit of a display screen and the display screen.
A thin film transistor according to an embodiment of the present invention includes a substrate, a first gate electrode formed on the substrate, a buffer layer covering the substrate and the first gate electrode, an active layer formed on the buffer layer, a gate insulating layer formed on the active layer, a second gate electrode formed on the gate insulating layer, an interlayer dielectric covering the active layer and the second gate electrode, a drain electrode formed on the interlayer dielectric, and a source electrode formed on the interlayer dielectric. The first grid is annular. The gate insulating layer is annular. The second grid is annular. The interlayer dielectric is formed with a first opening and a second opening. The drain is connected to the active layer through the first opening. The source electrode is connected with the active layer through the second opening.
The driving circuit of the display screen comprises the thin film transistor, the thin film transistor is used as a driving thin film transistor of the driving circuit, the driving circuit further comprises a switch thin film transistor, the switch thin film transistor is used for controlling the switch of the driving thin film transistor, and the driving thin film transistor is used for driving a light emitting diode of the display screen to emit light.
The display screen of the embodiment of the invention comprises the light emitting diode and the driving circuit.
The method for manufacturing a thin film transistor according to the embodiment of the present invention includes: providing a substrate; forming a first grid electrode on the substrate, wherein the first grid electrode is annular; forming a buffer layer covering the substrate and the first gate electrode; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer, the gate insulating layer being annular; forming a second grid electrode on the grid electrode insulating layer, wherein the second grid electrode is annular; forming an interlayer dielectric on the active layer and the second grid electrode, and opening a first opening and a second opening on the interlayer dielectric; forming a drain electrode on the interlayer dielectric, the drain electrode being connected to the active layer through the first opening; forming a source electrode on the interlayer dielectric, the source electrode being connected to the active layer through the second opening.
The embodiment of the invention provides a thin film transistor, a manufacturing method of the thin film transistor, a driving circuit of a display screen and the display screen. Because the thin film transistor of the embodiment of the invention has two grid electrodes (equivalent to two single-grid thin film transistors which are connected in parallel), the drain-source current of the thin film transistor can be enhanced when the thin film transistor works, so that the influence of RC delay and IR drop is effectively reduced, and the fluctuation of the drain-source current is smaller. In addition, the first grid electrode and the second grid electrode are both annular, so that the drain-source current of the thin film transistor can be enhanced, the influence of RC delay and IR drop is effectively reduced, and the drain-source current is more stable. Further, since the second gate electrode is formed on the active layer (i.e., the thin film transistor has a top gate structure), the overlap of the second gate electrode and the source electrode is small, and thus the parasitic capacitance of the thin film transistor is small.
Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the invention.
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a thin film transistor according to some embodiments of the present invention;
FIG. 2 is a schematic cross-sectional view of the thin film transistor of FIG. 1 taken along line A-A;
FIG. 3 is a schematic diagram of a circuit configuration of a display screen in accordance with certain embodiments of the present invention;
fig. 4 is a flow chart illustrating a method of fabricating a thin film transistor according to some embodiments of the present invention.
Description of the drawings with the main elements symbols:
the display panel 1000, the driving circuit 100, the thin film transistor (driving thin film transistor) 10, the substrate 11, the first gate electrode 12, the buffer layer 13, the active layer 14, the gate insulating layer 15, the second gate electrode 16, the interlayer dielectric 17, the first opening 172, the second opening 174, the drain electrode 18, the source electrode 19, the protective layer 10a, the planarization layer 10b, the via hole 10c, the anode electrode layer 10d, the switching thin film transistor 30, the switching gate electrode 32, the blocking gate electrode 34, and the light emitting diode 200.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
Referring to fig. 1 and 2, a thin film transistor 10 according to an embodiment of the present invention includes a substrate 11, a first gate electrode 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a second gate electrode 16, an interlayer dielectric 17, a drain electrode 18, and a source electrode 19. The first gate 12 is formed on the substrate 11, and the first gate 12 has a ring shape. The buffer layer 13 covers the substrate 11 and the first gate electrode 12. The active layer 14 is formed on the buffer layer 13. The gate insulating layer 15 is formed on the active layer 14, and the gate insulating layer 15 has a ring shape. The second gate electrode 16 is formed on the gate insulating layer 15, and the second gate electrode 16 has a ring shape. An interlayer dielectric 17 covers the active layer 14 and the second gate electrode 16, and the interlayer dielectric 17 is formed with a first opening 172 and a second opening 174. The drain electrode 18 is formed on the interlayer dielectric 17, and the drain electrode 18 is connected to the active layer 14 through the first opening 172. A source electrode 19 is formed on the interlayer dielectric 17, and the source electrode 19 is connected to the active layer 14 through the second opening 174.
The thin film transistor 10 according to the embodiment of the present invention has two gates (equivalent to two single-gate thin film transistors connected in parallel), so that the drain-source current of the thin film transistor 10 can be increased when the thin film transistor 10 is in operation, thereby effectively reducing the influence of RC delay and IR drop, and reducing the fluctuation of the drain-source current. In addition, since the first gate 12 and the second gate 16 are both annular, the drain-source current of the thin film transistor 10 can be enhanced, and the influence of RC delay and IR drop is effectively reduced, so that the drain-source current is more stable. Further, since the second gate electrode 16 is formed on the active layer 14 (i.e., the thin film transistor 10 has a top-gate structure), the overlap of the second gate electrode 16 and the source electrode 19 is small, and thus the parasitic capacitance of the thin film transistor 10 is small.
In some embodiments, the substrate 11 may be a flexible substrate or a rigid substrate. The material of the flexible substrate includes, for example, at least one of polyimide, polyethylene naphthalate, polycarbonate, and the like. The material of the rigid substrate includes, for example, a glass substrate. The material used for the substrate 11 may be determined as needed, and is not particularly limited herein.
In some embodiments, the material of the first gate electrode 12 and the second gate electrode 16 may be a conductive material, for example, including at least one of Au, Ag, Cu, Al, and the like. The materials of the first gate 12 and the second gate 16 may be determined as needed, and are not particularly limited herein. The first grid 12 and the second grid 16 may be both annular. The annular first gate 12 and the annular second gate 16 facilitate the transport of carriers, and can increase the mobility rate of carriers, thereby enhancing the drain-source current of the thin film transistor 10 when the thin film transistor 10 operates, and further effectively reducing RC delay and IR drop in a circuit including the thin film transistor 10. Of course, the first grid 12 and the second grid 16 may also be in a square ring shape, a track shape, etc., and are not limited in this regard.
In the embodiment of the invention, the first gate electrode 12 has a bottom gate structure. It should be noted that the first gate 12 of the bottom gate structure needs to be connected to other elements through a connector (not shown), so that the overlap between the first gate 12 and the source 19 is relatively large. Of course, the first gate 12 may also be designed as a top gate structure, and is not limited herein. Since at least one top gate structure (the second gate electrode 16 is a top gate structure) is present in the embodiment of the present invention, the parasitic capacitance of the thin film transistor 10 can be made smaller than that of two bottom gate structures.
The material of the buffer layer 13 and the gate insulating layer 15 may be an insulating material, and for example, includes at least one of silicon oxide, silicon nitride, aluminum oxide, and the like. The buffer layer 13 may have one or more layers (two or more layers), and the gate insulating layer 15 may have one or more layers (two or more layers), which are not particularly limited herein. The gate insulating layer 15 has a ring shape such that the drain electrode 18 or the source electrode 19 is connected to the middle region of the active layer 14. The gate insulating layer 15 may be circular, square, or racetrack, and is not limited in this respect.
The material of the active layer 14 may be at least one of single crystal silicon, polycrystalline silicon, an oxide semiconductor material, and the like. In the embodiment of the present invention, the material of the active layer 14 is an oxide semiconductor, and the oxide semiconductor includes, for example, IGZO, indium tin oxide, ZnO, and the like. The active layer 14 may have other shapes such as a circular shape or a rectangular shape, and is not particularly limited herein. The circular active layer 14 may also facilitate the transport of carriers, thereby increasing the mobility rate of carriers.
The material of the interlayer dielectric 17 may be an insulating material, for example, an inorganic insulating material including silicon oxide and/or silicon nitride. Of course, the material of the interlayer dielectric 17 may be an organic insulating material, and is not particularly limited herein.
The material of the drain electrode 18 and the source electrode 19 may be a conductive material, for example, a metal or a conductive metal oxide including Au, Ag, Cu, Al, ITO, or the like.
In the embodiment of the present invention, the projection of the first opening 172 on the active layer 14 is located outside the projection of the second gate 16 on the active layer 14, and the projection of the second opening 174 on the active layer 14 is located inside the projection of the second gate 16 on the active layer 14. The drain electrode 18 is connected to an edge region of the active layer 14 through the first opening 172, and the source electrode 19 is connected to a middle region of the active layer 14 through the second opening 174. The first gate 12 and the second gate 16 are located between the drain 18 and the source 19. In this case, the drain 18 may have a ring shape, for example, a circular ring shape, a square ring shape, or the like, and the source 19 may have a circular shape, a square shape, or the like.
In some embodiments, the projection of the first opening 172 on the active layer 14 is located within the projection of the second gate 16 on the active layer 14, and the projection of the second opening 174 on the active layer 14 is located outside the projection of the second gate 16 on the active layer 14. The drain electrode 18 is connected to the middle region of the active layer 14 through the first opening 172, and the source electrode 19 is connected to the edge region of the active layer 14 through the second opening 174. The first gate 12 and the second gate 16 are located between the drain 18 and the source 19. In this case, the drain 18 may have a circular shape, a square shape, or the like, and the source 19 may have a ring shape, for example, a circular ring shape, a square ring shape, or the like.
Referring to fig. 2, in some embodiments, the thin film transistor 10 further includes a protective layer 10a formed on the interlayer dielectric 17, the drain electrode 18, and the source electrode 19. The protective layer 10a is used to protect the thin film transistor 10, and the protective layer 10a may be made of an insulating material such as silicon oxide and/or silicon nitride.
In some embodiments, the thin film transistor 10 further includes a planarization layer 10b formed on the protective layer 10 a. The planarization layer 10b serves to further protect the thin film transistor 10 and planarize the protection layer 10 a. The planarization layer 10b may be formed using an organic material such as acrylic and/or an inorganic material such as silicon oxide.
In some embodiments, the protective layer 10a and the planarization layer 10b are opened with a through hole 10c communicating with each other, and the thin film transistor 10 further includes an anode electrode layer 10d formed on the planarization layer 10b, wherein the anode electrode layer 10d is connected to the source electrode 19 through the through hole 10 c. The anode electrode layer 10d may be made of a conductive material, for example, at least one of Au, Ag, Cu, Al, and the like. The anode electrode layer 10d can enlarge the contact area between the source electrode 19 and other elements, thereby facilitating the electrical connection between the source electrode 19 and other elements, for example, the source electrode 19 can be connected to a light emitting diode through the anode electrode layer 10 d.
Referring to fig. 3, the driving circuit 100 according to the embodiment of the invention can be applied to a display panel 1000. The driving circuit 100 includes the thin film transistor 10 according to any of the above embodiments, the thin film transistor 10 is used as the driving thin film transistor 10 of the driving circuit 100, and both the first gate 12 and the second gate 16 of the driving thin film transistor 10 are connected to the circuit. The driving circuit 100 further includes a switching thin film transistor 30, and the switching thin film transistor 30 is used to control the switching of the driving thin film transistor 10. The driving thin film transistor 10 is used to drive the light emitting diode 200 of the display panel 1000 to emit light. When the switching thin film transistor 30 is turned on, the operating state of the driving thin film transistor 10 can be controlled by Vdata to control the light emitting brightness of the light emitting diode.
In some embodiments, the switching thin film transistor 30 has a double gate structure, the switching thin film transistor 30 includes a switching gate 32 and a blocking gate 34, the switching gate 32 is used for controlling the operation state of the switching thin film transistor 30 according to Vgate, and the blocking gate 34 is disposed between the first gate 12 and the substrate of the switching thin film transistor 30 to block the diffusion of the external impurities into the switching thin film transistor 30. When the switching thin film transistor 30 of the double-gate structure is operated, the switching gate electrode 32 is connected into the circuit, and the blocking gate electrode 34 is not connected into the circuit.
Of course, in other embodiments, the switching thin film transistor 30 may also have a single-gate structure, and is not limited herein.
Referring to fig. 3, a display panel 1000 according to an embodiment of the invention includes a light emitting diode 200 and a driving circuit 100 according to any of the above embodiments.
Referring to fig. 4, the manufacturing method according to the embodiment of the invention may be used to manufacture the thin film transistor 10 according to any of the above embodiments. The manufacturing method comprises the following steps:
01: providing a substrate 11;
02: forming a first gate 12 on a substrate 11, the first gate 12 being annular;
03: forming a buffer layer 13, the buffer layer 13 covering the substrate 11 and the first gate electrode 12;
04: forming an active layer 14 on the buffer layer 13;
05: forming a gate insulating layer 15 on the active layer 14, the gate insulating layer 15 having a ring shape;
06: forming a second gate electrode 16 on the gate insulating layer 15, the second gate electrode 16 having a ring shape;
07: forming an interlayer dielectric 17 on the active layer 14 and the second gate electrode 16, and opening a first opening 172 and a second opening 174 on the interlayer dielectric 17;
08: forming a drain electrode 18 on the interlayer dielectric 17, the drain electrode 18 being connected to the active layer 14 through the first opening 172;
09: a source electrode 19 is formed on the interlayer dielectric 17, and the source electrode 19 is connected to the active layer 14 through the second opening 174.
In some embodiments, the first gate electrode 12 may be formed on the substrate 11 by film formation, exposure, and etching; forming a buffer layer 13 on the substrate 11 and the first gate electrode 12 by film formation; forming an active layer 14 on the buffer layer 13 by film formation, exposure, etching, and annealing; forming a gate insulating layer 15 on the active layer 14 by film formation, exposure, and etching, and forming a second gate electrode 16 on the gate insulating layer 15; forming an interlayer dielectric 17 on the active layer 14 and the second gate 16 by film forming, exposure and etching, and opening a first opening 172 and a second opening 174 in the interlayer dielectric 17; a drain electrode is formed on the interlayer dielectric 17 by film formation, exposure, and etching, a source electrode is formed on the interlayer dielectric 17, the drain electrode 18 is connected to the active layer 14 through the first opening 172, and the source electrode 19 is connected to the active layer 14 through the second opening 174.
In some embodiments, a protective layer 10a may be formed on the interlayer dielectric 17, the drain electrode 18, and the source electrode 19, a planarization layer 10b may be formed on the protective layer 10a, a through hole 10c communicating the protective layer 10a and the planarization layer 10b may be opened, and an anode electrode layer 10d may be formed on the planarization layer 10b, and the anode electrode layer 10d may be connected to the source electrode 19 through the through hole 10 c.
When the thin film transistor 10 is manufactured by the manufacturing method, the thin film transistor 10 according to the above embodiment can be referred to for materials, shapes, and the like of each layer, and will not be described again.
In the description herein, references to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Claims (11)
- A thin film transistor, comprising:a substrate;a first gate formed on the substrate, the first gate having a ring shape;a buffer layer covering the substrate and the first gate electrode;an active layer formed on the buffer layer;a gate insulating layer formed on the active layer, the gate insulating layer having a ring shape;a second gate formed on the gate insulating layer, the second gate having a ring shape;an interlayer dielectric covering the active layer and the second gate electrode, the interlayer dielectric being formed with a first opening and a second opening;a drain electrode formed on the interlayer dielectric, the drain electrode being connected to the active layer through the first opening;a source formed on the interlayer dielectric, the source being connected to the active layer through the second opening.
- The thin film transistor according to claim 1, wherein the first gate electrode and the second gate electrode are each annular.
- The thin film transistor of claim 1, wherein a projection of the first opening on the active layer is outside a projection of the second gate electrode on the active layer, and a projection of the second opening on the active layer is inside a projection of the second gate electrode on the active layer;or the projection of the first opening on the active layer is positioned in the projection of the second grid electrode on the active layer, and the projection of the second opening on the active layer is positioned out of the projection of the second grid electrode on the active layer.
- The thin film transistor according to claim 1, wherein a material of the active layer is an oxide semiconductor.
- The thin film transistor according to claim 1, further comprising a protective layer formed on the interlayer dielectric, the drain electrode, and the source electrode.
- The thin film transistor according to claim 5, further comprising a planarization layer formed on the protective layer.
- The thin film transistor according to claim 6, wherein the protective layer and the planarization layer have through holes formed therein, and the thin film transistor further comprises an anode electrode layer formed on the planarization layer, the anode electrode layer being connected to the source electrode through the through holes.
- A driving circuit of a display panel, wherein the driving circuit comprises the thin film transistor of any one of claims 1 to 7 as a driving thin film transistor of the driving circuit, and further comprises a switching thin film transistor for controlling the switching of the driving thin film transistor, and the driving thin film transistor is used for driving the light emitting diode of the display panel to emit light.
- The driving circuit according to claim 8, wherein the switching thin film transistor comprises a switching gate and a blocking gate, the switching gate is used for controlling the operation state of the switching thin film transistor, and the blocking gate is disposed between the first gate and the substrate of the switching thin film transistor to block the diffusion of the external impurities into the switching thin film transistor.
- A display screen, characterized in that the display screen comprises a light emitting diode and a driver circuit as claimed in claim 8 or 9.
- A method of manufacturing a thin film transistor, the method comprising:providing a substrate;forming a first grid electrode on the substrate, wherein the first grid electrode is annular;forming a buffer layer covering the substrate and the first gate electrode;forming an active layer on the buffer layer;forming a gate insulating layer on the active layer, the gate insulating layer being annular;forming a second grid electrode on the grid electrode insulating layer, wherein the second grid electrode is annular;forming an interlayer dielectric on the active layer and the second grid electrode, and opening a first opening and a second opening on the interlayer dielectric;forming a drain electrode on the interlayer dielectric, the drain electrode being connected to the active layer through the first opening;forming a source electrode on the interlayer dielectric, the source electrode being connected to the active layer through the second opening.
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| PCT/CN2019/074446 WO2020155107A1 (en) | 2019-02-01 | 2019-02-01 | Thin film transistor and manufacturing method therefor, driver circuit, and display screen |
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| CN104465788A (en) * | 2015-01-04 | 2015-03-25 | 京东方科技集团股份有限公司 | Thin film transistor, preparing method of thin film transistor, array substrate, preparing method of array substrate and display device |
| CN106910748A (en) * | 2017-04-10 | 2017-06-30 | 深圳市华星光电技术有限公司 | A kind of array base palte, display device and preparation method thereof |
| CN107134474B (en) * | 2017-06-12 | 2020-07-24 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor, manufacturing method thereof and organic electroluminescent display |
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2019
- 2019-02-01 CN CN201980073529.7A patent/CN113261103A/en active Pending
- 2019-02-01 WO PCT/CN2019/074446 patent/WO2020155107A1/en active Application Filing
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| CN104461161A (en) * | 2014-12-29 | 2015-03-25 | 京东方科技集团股份有限公司 | Touch substrate and touch device |
| CN104779272A (en) * | 2015-04-10 | 2015-07-15 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, production methods of thin film transistor and array substrate as well as display device |
| CN104952885A (en) * | 2015-05-18 | 2015-09-30 | 京东方科技集团股份有限公司 | Display baseplate, manufacturing method thereof and display device |
| US20160365404A1 (en) * | 2015-06-11 | 2016-12-15 | Samsung Display Co., Ltd. | Thin film transistor substrate and organic light-emitting diode display including the same |
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