CN113257879B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN113257879B CN113257879B CN202110570947.6A CN202110570947A CN113257879B CN 113257879 B CN113257879 B CN 113257879B CN 202110570947 A CN202110570947 A CN 202110570947A CN 113257879 B CN113257879 B CN 113257879B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The invention provides an array substrate and a display panel, comprising: a substrate base plate; the planarization layer is positioned on the substrate and comprises hollow-out areas which extend along a first direction; the interlayer insulating layer is positioned between the substrate base plate and the planarization layer, a plurality of fan-out wires are arranged in the interlayer insulating layer, and at least one signal wire is arranged between the fan-out wires and the planarization layer; at least one side edge of the signal line in the first direction and at least one edge line of the hollow area in the second direction are provided with an edge overlapping area; on the orthographic projection of the substrate base plate, the fan-out routing extends to penetrate through the hollow area, and the fan-out routing is not overlapped with at least one edge overlapping area. On the orthographic projection of the substrate base plate, the fan-out wiring and at least one edge overlapping area are not overlapped, so that the fan-out wiring can avoid the edge overlapping area which is easy to corrode by water vapor, the condition that the fan-out wiring is corroded by water vapor is improved, and the reliability of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
With the development of display technology, liquid crystal display panels, organic light emitting display panels, and the like have advantages such as high image quality, power saving, and thin body, and thus are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of display devices. One of the important components of the display panel is an array substrate, wherein the array substrate comprises a display area and a frame area, and related wiring is arranged in the display area to control pixels to be lightened so as to realize the display of images; the non-display area is provided with a driving chip and a fan-out wire connected with the driving chip, and the driving chip transmits a driving signal to related wiring of the display area through the fan-out wire. The existing part of fan-out wiring is easy to be corroded by water vapor, so that the effect of the fan-out wiring for transmitting a driving signal is poor.
Disclosure of Invention
In view of this, the present invention provides an array substrate and a display panel, which effectively solve the technical problems in the prior art, improve the corrosion of fan-out traces by water vapor, and improve the reliability of the display panel.
In order to realize the purpose, the technical scheme provided by the invention is as follows:
an array substrate, comprising:
a base substrate;
the planarization layer is positioned on the substrate and comprises hollow-out areas extending along a first direction;
the interlayer insulating layer is positioned between the substrate base plate and the planarization layer, and a plurality of fan-out wires and at least one signal wire which is positioned between the fan-out wires and the planarization layer are arranged in the interlayer insulating layer;
at least one side edge of the signal line in the first direction and at least one edge line of the hollow area in the second direction have an edge overlapping area; on the orthographic projection of the substrate base plate, the fan-out routing extends to penetrate through the hollowed-out area, the fan-out routing is not overlapped with at least one edge overlapping area, and the first direction is intersected with the second direction.
Optionally, the array substrate includes a display area and a frame area, the hollow area is located in the frame area, and the first direction is the same as an extending direction of an edge line of the hollow area close to the display area;
at least one side edge of the signal line in the first direction, and an edge line deviating from the display area with the hollow area has an edge overlapping area which is a bottom edge overlapping area; on the orthographic projection of the substrate base plate, the fan-out routing lines are not overlapped with the bottom edge overlapping area.
Optionally, the array substrate further includes: the dummy fan-out wires extend through the hollowed-out area in the orthographic projection of the substrate base plate, and the dummy fan-out wires are overlapped with the edge overlapping area.
Optionally, the dummy fan-out line is parallel to an extending direction of the fan-out line.
Optionally, the array substrate further includes: a plurality of floating dummy fan-out routing line segments, wherein the dummy fan-out routing line segments overlap the edge overlap region in an orthographic projection of the substrate base plate.
Optionally, in the second direction, the plurality of fan-out traces include a first partial fan-out trace and a second partial fan-out trace that are adjacent to each other, and each of the first partial fan-out trace and the second partial fan-out trace includes at least one fan-out trace; at least one dummy fan-out line segment is arranged between the first part of fan-out lines and the second part of fan-out lines and defined as a middle dummy fan-out line segment;
in the first partial fan-out routing and/or the second partial fan-out routing, the fan-out routing comprises at least one section of connecting line segment; wherein, on a plane perpendicular to the extending direction of the middle dummy fan-out wire segment, the orthographic projection of at least one middle dummy fan-out wire segment is overlapped with the orthographic projection of the connecting wire segment close to the middle dummy fan-out wire segment.
Optionally, in the first part of fan-out traces and/or the second part of fan-out traces, the fan-out traces include a first fan-out trace line segment, a section of the connection line segment, and a second fan-out trace line segment, and the first fan-out trace line segment and the second fan-out trace line segment are connected through the connection line segment; the extending directions of the first fan-out wiring line segment, the second fan-out wiring line segment and the middle nominal fan-out wiring line segment are all parallel.
Optionally, in the first partial fan-out trace and/or the second partial fan-out trace, the fan-out trace includes a third fan-out trace line segment, a fourth fan-out trace line segment, a fifth fan-out trace line segment, and two segments of the connection line segment defined as a first connection line segment and a second connection line segment, the third fan-out trace line segment and the fourth fan-out trace line segment are connected through the first connection line segment, the fourth fan-out trace line segment and the fifth fan-out trace line segment are connected through the second connection line segment, and the third fan-out trace line segment and the fifth fan-out trace line segment are both located on one side of the fourth fan-out trace line segment facing the middle dummy fan-out trace line segment; the extending directions of the third fan-out wiring line segment, the fourth fan-out wiring line segment, the fifth fan-out wiring line segment and the middle nominal fan-out wiring line segment are all parallel.
Optionally, the at least one signal line includes a first signal line and a second signal line, and the first signal line and the second signal line penetrate through the hollow area on the orthographic projection of the substrate base plate.
Optionally, the first signal line is a PVDD signal line, and the second signal line is a PVEE signal line.
Optionally, the array substrate includes:
the first metal layer is positioned on one side, facing the planarization layer, of the substrate base plate;
the first insulating layer is positioned on one side, away from the substrate, of the first metal layer;
the capacitor metal layer is positioned on one side, away from the substrate, of the first insulating layer;
the second insulating layer is positioned on one side, away from the substrate, of the capacitor metal layer;
the second metal layer is positioned on one side, away from the substrate, of the second insulating layer;
the third insulating layer is positioned on one side, away from the substrate, of the second metal layer;
the third metal layer is positioned on one side, away from the substrate, of the third insulating layer;
the third metal layer is positioned on the first insulating layer, and the third metal layer is positioned on the second insulating layer;
the fan-out routing is located on the first metal layer or the capacitor metal layer, and the signal line is located on the second metal layer or the third metal layer.
Correspondingly, the invention further provides a display panel which comprises the array substrate.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides an array substrate and a display panel, comprising: a base substrate; the planarization layer is positioned on the substrate and comprises hollow-out areas extending along a first direction; the interlayer insulating layer is positioned between the substrate base plate and the planarization layer, and a plurality of fan-out wires and at least one signal wire which is positioned between the fan-out wires and the planarization layer are arranged in the interlayer insulating layer; at least one side edge of the signal line in the first direction and at least one edge line of the hollow area in the second direction have an edge overlapping area; on the orthographic projection of the substrate base plate, the fan-out routing wire extends to penetrate through the hollowed-out area, the fan-out routing wire is not overlapped with at least one edge overlapping area, and the first direction is intersected with the second direction.
According to the array substrate provided by the invention, the fan-out wiring and at least one edge overlapping area are not overlapped on the orthographic projection of the substrate, so that the fan-out wiring can avoid the edge overlapping area which is easily corroded by water vapor, the condition that the fan-out wiring is corroded by the water vapor is improved, and the reliability of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along the direction AA' in FIG. 1;
FIG. 3 is a cut-away view in the direction of BB' in FIG. 1;
fig. 4 is a schematic structural view of another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a fan-out trace and a dummy fan-out trace segment according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another fan-out trace and a dummy fan-out trace segment according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another fan-out trace and a dummy fan-out trace segment according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the array substrate includes a display area and a frame area, and related wirings are provided in the display area to control pixels to be lit, so as to display an image; the non-display area is provided with a driving chip and a fan-out wire connected with the driving chip, and the driving chip transmits a driving signal to related wires of the display area through the fan-out wire. The existing partial fan-out wiring is easy to be corroded by water vapor, so that the fan-out wiring has poor effect of transmitting a driving signal.
Based on this, the embodiment of the invention provides an array substrate and a display panel, which effectively solve the technical problems in the prior art, improve the condition that fan-out wires are corroded by water vapor, and improve the reliability of the display panel.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 12.
Referring to fig. 1 to 3, fig. 1 is a schematic structural view of an array substrate according to an embodiment of the present invention, fig. 2 is a sectional view taken along an AA 'direction in fig. 1, and fig. 3 is a sectional view taken along a BB' direction in fig. 1. The array substrate provided by the embodiment of the invention comprises:
a base substrate 100.
The planarization layer 200 is located on the substrate 100, and the planarization layer 200 includes a hollow-out region 210 extending along a first direction X.
The interlayer insulating layer 300 is disposed between the substrate 100 and the planarization layer 200, a plurality of fan-out traces 410 are disposed in the interlayer insulating layer 300, and at least one signal line 500 is disposed between the plurality of fan-out traces 410 and the planarization layer 200.
At least one side of the signal line 500 in the first direction X and at least one edge line of the hollow area 210 in the second direction Y have an edge overlapping area 600; in an orthographic projection of the substrate 100, the fan-out trace 410 extends through the hollow area 210, and the fan-out trace 410 does not overlap with at least one of the edge overlapping regions 600, and the first direction X intersects with the second direction Y.
In an embodiment of the invention, the array substrate includes a display area AA and a frame area NA located outside the display area AA; the frame area NA includes a chip bonding area 10 and a fan-out area (not labeled) located between the chip bonding area 10 and the display area AA; the fan-out area is provided with a plurality of fan-out wires 410, and the chip bonding area 100 is bonded with a driving chip. After the planarization layer 200 is formed, the hollowed-out area 210 is required to be formed on the planarization layer 200 at the frame area NA and corresponding to the fan-out area, that is, the planarization layer 200 is hollowed at the frame area NA and corresponding to the fan-out area to form the empty area extending along the first direction X. However, as the planarizing layer 200 is hollowed to form the hollow-out region 210, when the hollow-out region 210 overlaps with the signal line 500, at least one side edge of the signal line 500 in the first direction X may have a crack Fs in a portion of the interlayer insulating layer 300 corresponding to an edge overlapping region of at least one edge line of the hollow-out region 210 in the second direction Y, so as to form a water vapor erosion channel, and finally, a situation that a line is corroded by water vapor may easily occur in the edge overlapping region. Therefore, in the array substrate provided by the embodiment of the invention, on the orthographic projection of the substrate 100, the fan-out routing 410 is not overlapped with at least one edge overlapping area 600, so that the fan-out routing 410 can avoid the edge overlapping area 600 which is easily corroded by water vapor, the corrosion condition of the fan-out routing 410 by water vapor is improved, and the reliability of the display panel is improved.
It should be noted that the hollow-out area 210 shown in fig. 1 provided in the embodiment of the present invention is only a local area of the clearance area on the array substrate, and the clearance area provided in the embodiment of the present invention may be disposed around the display area AA, which is not particularly limited to this, and needs to be specifically designed according to practical applications.
As shown in fig. 4, a schematic structural diagram of another array substrate according to an embodiment of the present invention is provided, where the array substrate according to the embodiment of the present invention includes a display area AA and a frame area NA, the hollow-out area 210 is located in the frame area NA, and the first direction X is the same as an extending direction of an edge line of the hollow-out area 210 close to the display area AA.
At least one side of the signal line 500 in the first direction X has an edge overlapping area with an edge line of the hollow area 210 away from the display area AA, which is a bottom edge overlapping area 610; on the orthographic projection of the substrate base plate 100, the fan-out routing 410 is not overlapped with the bottom edge overlapping area 610.
It can be understood that one side of the hollow-out area, which is far away from the display area, provided by the embodiment of the invention is close to the boundary where the array substrate is in contact with the outside, and thus the structure of one side of the hollow-out area, which is far away from the display area, is more easily corroded by water vapor. Therefore, the fan-out routing provided by the embodiment of the invention is only set to be non-overlapped with the bottom edge overlapping area, and whether the overlapping condition exists in the edge overlapping area of the edge line of the hollowed-out area close to one side of the display area and the signal line and the position relation of the fan-out line is not considered, so that the wiring difficulty of the fan-out area is further reduced. Therefore, the invention is not particularly limited, and the fan-out routing provided by the embodiment of the invention can be arranged without overlapping with all the edge overlapping areas, and needs to be specifically designed according to practical application.
As shown in fig. 5, a schematic structural diagram of another array substrate provided in an embodiment of the present invention is shown, where the array substrate provided in the embodiment of the present invention further includes: a plurality of floating dummy fan-out traces 420, wherein in the orthographic projection of the substrate base plate, the dummy fan-out traces 420 extend through the hollow area 210, and the dummy fan-out traces 420 are overlapped with the edge overlapping area 600.
It can be understood that the array substrate provided by the embodiment of the invention is provided with the dummy fan-out lines, wherein the dummy fan-out lines are physical lines and do not have a function of transmitting a driving signal, and further, through the floating dummy fan-out lines, gap areas which are vacated by the fan-out lines due to no overlapping arrangement with edge overlapping areas are supplemented, so that the line consistency of the fan-out areas is ensured. Optionally, the dummy fan-out trace provided in the embodiment of the present invention is parallel to the extending direction of the fan-out trace. The dummy fan-out lines and the fan-out lines can have the same line extending shape, and the distances between two adjacent fan-out lines, two adjacent dummy fan-out lines and between the adjacent fan-out lines and the dummy fan-out lines provided by the embodiment of the invention can be the same, so that the invention is not particularly limited.
In an embodiment of the invention, the dummy fan-out line provided by the invention can be a dummy fan-out line having the same shape as the fan-out line, and can also be a segment of a line which is only overlapped with the edge overlapping area. As shown in fig. 6, which is a schematic structural diagram of another array substrate according to an embodiment of the present invention, the array substrate further includes: a plurality of floating dummy fan-out routing line segments 430, the dummy fan-out routing line segments 430 overlapping the edge overlap region 600 in an orthographic projection of the substrate base plate.
In order to ensure that lines in the fan-out area are uniformly arranged, the fan-out traces provided in the embodiment of the present invention may be arranged in a zigzag shape, which is specifically described in detail according to schematic diagrams of structures of the fan-out traces and the dummy fan-out traces shown in fig. 7 to 9.
As shown in fig. 7, a schematic structural diagram of a fan-out trace and a dummy fan-out trace provided by an embodiment of the present invention, where in the second direction Y, the plurality of fan-out traces include a first partial fan-out trace 401 and a second partial fan-out trace 402 that are adjacent to each other, and each of the first partial fan-out trace 401 and the second partial fan-out trace 402 includes at least one fan-out trace 410; the first partial fan-out trace 401 and the second partial fan-out trace 402 include at least one dummy fan-out trace line segment therebetween, defined as an intermediate dummy fan-out trace line segment 431.
In the first partial fan-out trace 401 and/or the second partial fan-out trace 402, the fan-out trace 410 includes at least one connecting line segment 411; on a plane perpendicular to the extending direction of the middle dummy fan-out wiring line segment 431, the orthographic projection of at least one middle dummy fan-out wiring line segment 431 is overlapped with the orthographic projection of the connecting line segment 411 close to the middle dummy fan-out wiring line segment 431.
It can be understood that, in the first part of fan-out traces and/or the second part of fan-out traces, the fan-out traces are manufactured to include at least one section of connecting line segment, so that the fan-out traces can be formed into a broken line structure, the interval between the broken fan-out traces and the fan-out traces in the other part of fan-out traces can be optimized, the adjacent two fan-out traces, the adjacent two dummy fan-out line segments and the interval between the adjacent fan-out traces and the dummy fan-out line segments are set to be the same through optimization, and the invention is not particularly limited.
The fan-out routing provided by the embodiment of the invention can only comprise a section of connecting line segment, namely in the first part of fan-out routing and/or the second part of fan-out routing, the fan-out routing comprises a first fan-out routing line segment, a section of the connecting line segment and a second fan-out routing line segment, and the first fan-out routing line segment and the second fan-out routing line segment are connected through the connecting line segment; the extending directions of the first fan-out wiring line segment, the second fan-out wiring line segment and the middle nominal fan-out wiring line segment are all parallel. As shown in fig. 7, in the fan-out traces provided by the embodiment of the present invention, the fan-out trace 410 in one of the first partial fan-out trace 401 and the second partial fan-out trace 402 may be arranged as a zigzag. If the fan-out trace 410 in the second partial fan-out trace 401 is arranged as a broken line, in the second partial fan-out trace 402, the fan-out trace 410 includes a first fan-out trace line segment 412, a section of the connection line segment 411 and a second fan-out trace line segment 413, and the first fan-out trace line segment 412 and the second fan-out trace line segment 413 are connected by the connection line segment 411; the extension directions of the first fan-out trace line segment 412, the second fan-out trace line segment 413 and the intermediate dummy fan-out trace line segment 431 are all parallel.
Alternatively, as shown in fig. 8, which is a schematic structural diagram of another fan-out trace and a dummy fan-out trace segment provided in the embodiment of the present invention, in the fan-out trace provided in the embodiment of the present invention, the fan-out trace 410 in both the first part of the fan-out trace 401 and the second part of the fan-out trace 402 may be set to be a broken line shape. In the first partial fan-out trace 401 and the second partial fan-out trace 402, the fan-out trace 410 includes a first fan-out trace line segment 412, a segment of the connection line segment 411, and a second fan-out trace line segment 413, and the first fan-out trace line segment 412 and the second fan-out trace line segment 413 are connected by the connection line segment 411; the extension directions of the first fan-out trace line segment 412, the second fan-out trace line segment 413 and the intermediate dummy fan-out trace line segment 431 are all parallel.
In an embodiment of the present invention, the fan-out trace provided in the embodiment of the present invention may only include two connecting line segments. As shown in fig. 9, a schematic structural diagram of a fan-out trace and a dummy fan-out trace segment provided in the embodiment of the present invention is shown, in the first partial fan-out trace 401 and/or the second partial fan-out trace 402, the fan-out routing 410 includes a third fan-out routing line segment 414, a fourth fan-out routing line segment 415, and a fifth fan-out routing line segment 416, and two segments of the connecting line segment defined as a first connecting line segment 4111 and a second connecting line segment 4112, the third fan-out trace segment 414 and the fourth fan-out trace segment 415 are connected by the first connecting segment 4111, the fourth fan-out trace segment 415 and the fifth fan-out trace segment 416 are connected by the second connecting segment 4112, the third fan-out trace segment 414 and the fifth fan-out trace segment 416 are both located on a side of the fourth fan-out trace segment 415 facing the intermediate dummy fan-out trace segment 431; the extending directions of the third fan-out wiring line segment 414, the fourth fan-out wiring line segment 415, the fifth fan-out wiring line segment 416 and the middle dummy fan-out wiring line segment 431 are all parallel.
It should be noted that the wiring structure of the fan-out trace and the dummy fan-out trace segment provided in the embodiment of the present invention is not limited to the wirings shown in fig. 7 to 9, and may be other wiring structures, which is not limited in particular.
Fig. 10 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. The at least one signal line provided by the embodiment of the present invention includes a first signal line 510 and a second signal line 520, and the first signal line 510 and the second signal line 520 penetrate through the hollow area 210 on the orthographic projection of the substrate 100.
In an embodiment of the present invention, the first signal line 510 provided in the embodiment of the present invention may be a PVDD signal line, and the second signal line 520 may be a PVEE signal line, which is not limited in particular.
In an embodiment of the invention, the fan-out traces and the signal lines provided by the invention can be located on a metal layer of the array substrate. Fig. 11 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, where the array substrate includes:
a first metal layer 101 on a side of the substrate 100 facing the planarization layer 200.
And the first insulating layer 102 is positioned on one side of the first metal layer 101, which faces away from the substrate base plate 100.
And the capacitor metal layer 103 is positioned on one side of the first insulating layer 102, which faces away from the substrate base plate 100.
And the second insulating layer 104 is positioned on one side of the capacitance metal layer 103, which is far away from the substrate 100.
A second metal layer 105 on a side of the second insulating layer 104 facing away from the substrate base plate 100.
And a third insulating layer 106 positioned on the side of the second metal layer 105 facing away from the substrate base plate 100.
A third metal layer 107 on a side of the third insulating layer 106 facing away from the substrate 100.
A fourth insulating layer 108 located on a side of the third metal layer 107 facing away from the substrate 100, and the planarization layer 200 located on a side of the fourth insulating layer 108 facing away from the substrate 100, where the interlayer insulating layer includes the first insulating layer 102, the second insulating layer 104, the third insulating layer 106, and the fourth insulating layer 108; the interlayer insulating layer provided by the embodiment of the invention is made of an inorganic material, and the planarization layer can be made of an organic material. The fan-out routing is located on the first metal layer or the capacitor metal layer, and the signal line is located on the second metal layer or the third metal layer.
It should be noted that the array substrate provided in the embodiment of the present invention further includes a semiconductor layer 109 located between the first metal layer 101 and the substrate 100, and a dielectric insulating layer 1091 is located between the semiconductor layer 109 and the adjacent first metal layer 101. The semiconductor layer provided in the embodiment of the present invention may also be located on a side of the first metal layer away from the substrate, and the semiconductor layer may specifically be located on a side of the capacitor metal layer facing the substrate, or the semiconductor layer is located on a side of the capacitor metal layer away from the substrate, which is not limited in particular. Therefore, the gate electrode included in the first metal layer, the source electrode and the drain electrode included in the second metal layer, and the active region included in the semiconductor layer form a transistor of the array substrate, and the electrode plate of the capacitor metal layer and the electrode plate of the first metal layer or the second metal layer form a capacitor of the array substrate.
Correspondingly, the embodiment of the invention also provides a display panel, and the display panel comprises the array substrate provided by any one of the embodiments.
Referring to fig. 12, which is a schematic structural diagram of a display panel according to an embodiment of the present invention, the display panel according to the embodiment of the present invention may be a mobile terminal 1000, and the mobile terminal includes the array substrate according to any one of the embodiments.
It should be noted that the display panel provided in the embodiment of the present invention may also be a notebook, a tablet, a computer, a wearable device, and the like, and the present invention is not limited in particular.
The embodiment of the invention provides an array substrate and a display panel, comprising: a substrate base plate; the planarization layer is positioned on the substrate and comprises hollow-out areas extending along a first direction; the interlayer insulating layer is positioned between the substrate base plate and the planarization layer, a plurality of fan-out wires and at least one signal wire are arranged between the fan-out wires and the planarization layer; at least one side edge of the signal line in the first direction and at least one edge line of the hollow area in the second direction have an edge overlapping area; on the orthographic projection of the substrate base plate, the fan-out routing extends to penetrate through the hollowed-out area, the fan-out routing is not overlapped with at least one edge overlapping area, and the first direction is intersected with the second direction.
As can be seen from the above, in the array substrate provided in the embodiment of the present invention, on the orthographic projection of the substrate, the fan-out trace and at least one edge overlapping region are not overlapped, so that the fan-out trace can avoid the edge overlapping region that is easily corroded by water vapor, the corrosion of the fan-out trace by water vapor is improved, and the reliability of the display panel is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. An array substrate, comprising:
a substrate base plate;
the planarization layer is positioned on the substrate and comprises hollow-out areas extending along a first direction;
the interlayer insulating layer is positioned between the substrate base plate and the planarization layer, and a plurality of fan-out wires and at least one signal wire which is positioned between the fan-out wires and the planarization layer are arranged in the interlayer insulating layer;
at least one side edge of the signal line in the first direction and at least one edge line of the hollow area in the second direction have an edge overlapping area; on the orthographic projection of the substrate base plate, the fan-out routing extends to penetrate through the hollowed-out area, the fan-out routing is not overlapped with at least one edge overlapping area, and the first direction is intersected with the second direction.
2. The array substrate of claim 1, wherein the array substrate comprises a display area and a frame area, the hollow area is located in the frame area, and the first direction is the same as an extending direction of an edge line of the hollow area adjacent to the display area;
at least one side edge of the signal line in the first direction has an edge overlapping area which is a bottom edge overlapping area with an edge line of the hollow area deviating from the display area; on the orthographic projection of the substrate base plate, the fan-out routing lines are not overlapped with the bottom edge overlapping area.
3. The array substrate of claim 1, wherein the array substrate further comprises: the dummy fan-out wires extend through the hollowed-out area in the orthographic projection of the substrate base plate, and the dummy fan-out wires are overlapped with the edge overlapping area.
4. The array substrate of claim 3, wherein the dummy fan-out trace is parallel to a direction in which the fan-out trace extends.
5. The array substrate of claim 1, wherein the array substrate further comprises: a plurality of floating dummy fan-out routing line segments overlapping the edge overlap region on an orthographic projection of the substrate base plate.
6. The array substrate of claim 5, wherein in the second direction the plurality of fan-out traces includes a first portion of fan-out traces and a second portion of fan-out traces that are adjacent, the first portion of fan-out traces and the second portion of fan-out traces each including at least one of the fan-out traces; at least one dummy fan-out line segment is arranged between the first part of fan-out lines and the second part of fan-out lines and defined as a middle dummy fan-out line segment;
in the first partial fan-out routing and/or the second partial fan-out routing, the fan-out routing comprises at least one section of connecting line segment; and on a plane perpendicular to the extending direction of the middle dummy fan-out wiring line segment, the orthographic projection of at least one middle dummy fan-out wiring line segment is overlapped with the orthographic projection of the connecting line segment close to the middle dummy fan-out wiring line segment.
7. The array substrate of claim 6, wherein in the first partial fan-out trace and/or the second partial fan-out trace, the fan-out trace comprises a first fan-out trace line segment, a section of the connection line segment, and a second fan-out trace line segment, and the first fan-out trace line segment and the second fan-out trace line segment are connected by the connection line segment; the extending directions of the first fan-out wiring line segment, the second fan-out wiring line segment and the middle nominal fan-out wiring line segment are all parallel.
8. The array substrate of claim 6, wherein in the first partial fan-out trace and/or the second partial fan-out trace, the fan-out trace includes a third fan-out trace segment, a fourth fan-out trace segment, and a fifth fan-out trace segment, and two segments of the connection trace defined as a first connection segment and a second connection segment, the third fan-out trace segment and the fourth fan-out trace segment are connected by the first connection segment, the fourth fan-out trace segment and the fifth fan-out trace segment are connected by the second connection segment, and the third fan-out trace segment and the fifth fan-out trace segment are both located on a side of the fourth fan-out trace segment facing the intermediate fan-out trace segment; the extending directions of the third fan-out wiring line segment, the fourth fan-out wiring line segment, the fifth fan-out wiring line segment and the middle nominal fan-out wiring line segment are all parallel.
9. The array substrate of claim 1, wherein the at least one signal line comprises a first signal line and a second signal line, and the first signal line and the second signal line penetrate through the hollowed-out area in an orthographic projection of the substrate.
10. The array substrate of claim 9, wherein the first signal line is a PVDD signal line and the second signal line is a PVEE signal line.
11. The array substrate of claim 1, wherein the array substrate comprises:
the first metal layer is positioned on one side, facing the planarization layer, of the substrate base plate;
the first insulating layer is positioned on one side, away from the substrate, of the first metal layer;
the capacitor metal layer is positioned on one side, away from the substrate, of the first insulating layer;
the second insulating layer is positioned on one side, away from the substrate, of the capacitor metal layer;
the second metal layer is positioned on one side, away from the substrate, of the second insulating layer;
the third insulating layer is positioned on one side, away from the substrate, of the second metal layer;
the third metal layer is positioned on one side, away from the substrate, of the third insulating layer;
the third metal layer is positioned on the first insulating layer, and the second metal layer is positioned on the second insulating layer;
the fan-out routing is located on the first metal layer or the capacitor metal layer, and the signal line is located on the second metal layer or the third metal layer.
12. A display panel comprising the array substrate according to any one of claims 1 to 11.
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| WO2018076285A1 (en) * | 2016-10-28 | 2018-05-03 | 深圳市柔宇科技有限公司 | Array substrate and method for manufacturing same |
| CN109061970A (en) * | 2018-09-03 | 2018-12-21 | 重庆惠科金渝光电科技有限公司 | Array substrate, display panel and display device |
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| US9659973B2 (en) * | 2014-03-14 | 2017-05-23 | Innolux Corporation | Display device |
| TWI537656B (en) * | 2014-03-14 | 2016-06-11 | 群創光電股份有限公司 | Display device |
| US20210098341A1 (en) * | 2019-09-30 | 2021-04-01 | Paradromics Inc. | Microelectrode array and methods of fabricating same |
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| CN106796949A (en) * | 2014-09-30 | 2017-05-31 | 乐金显示有限公司 | Flexible display apparatus |
| WO2018076285A1 (en) * | 2016-10-28 | 2018-05-03 | 深圳市柔宇科技有限公司 | Array substrate and method for manufacturing same |
| CN109061970A (en) * | 2018-09-03 | 2018-12-21 | 重庆惠科金渝光电科技有限公司 | Array substrate, display panel and display device |
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