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CN113257801A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN113257801A
CN113257801A CN202110162589.5A CN202110162589A CN113257801A CN 113257801 A CN113257801 A CN 113257801A CN 202110162589 A CN202110162589 A CN 202110162589A CN 113257801 A CN113257801 A CN 113257801A
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China
Prior art keywords
semiconductor device
circuit pattern
buffer circuit
resistor
substrate
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CN202110162589.5A
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CN113257801B (zh
Inventor
后藤亮
大月高实
清水康贵
富冈真吾
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • G01—MEASURING; TESTING
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    • G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
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    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/348—Passive dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

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Abstract

本发明的目的在于提供能够在设置了缓冲电路后确认缓冲电路的耐压的半导体装置及半导体装置的制造方法。本发明涉及的半导体装置具有：绝缘基板(1)；电路图案(6、7、8)，其设置于绝缘基板(1)之上；缓冲电路用基板(14)，其在绝缘基板(1)之上与电路图案(6、7、8)分离地设置；电阻(15)，其设置于电路图案(6、7、8)及缓冲电路用基板(14)中的一者；电容器(16)，其设置于电路图案(6、7、8)及缓冲电路用基板(14)中的另一者；以及半导体元件(9)，其与电阻(15)及电容器(16)电连接。

Description

半导体装置及半导体装置的制造方法
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
半导体装置用于发电及送电中的有效的能量利用及再生等各种场景。当前，公开了对在构成半导体装置的开关元件执行通断动作时产生的阻尼振荡进行抑制的技术(例如，参照专利文献1)。
专利文献1：国际公开第2018/194153号
在专利文献1中公开了与如下模块结构相关的技术，即，该模块结构是在设置于基座绝缘基板的导电图案之上具有电容器及电阻体串联连接的缓冲电路。但是，该缓冲电路设置于与P电极及N电极相同电位的导电图案之上，因此存在在设置了缓冲电路后无法确认缓冲电路本身的耐压这样的问题。
另外，在专利文献1中公开了作为在陶瓷板之上形成了电阻膜的部件单体构成缓冲电路的技术。但是，由于陶瓷板设置于与P电极或N电极的任意者相同电位的导电图案之上，因此存在无法确认缓冲电路本身的耐压这样的问题。
发明内容
本发明就是为了解决上述问题而提出的，其目的在于，提供能够在设置了缓冲电路后确认缓冲电路的耐压的半导体装置及半导体装置的制造方法。
为了解决上述课题，本发明涉及的半导体装置具有：绝缘基板；电路图案，其设置于绝缘基板之上；缓冲电路用基板，其在绝缘基板之上与电路图案分离地设置；电阻，其设置于电路图案及缓冲电路用基板中的一者；电容器，其设置于电路图案及缓冲电路用基板中的另一者；以及半导体元件，其与电阻及电容器电连接。
发明的效果
根据本发明，半导体装置具有：电路图案，其设置于绝缘基板之上；缓冲电路用基板，其在绝缘基板之上与电路图案分离地设置；电阻，其设置于电路图案及缓冲电路用基板中的一者；以及电容器，其设置于电路图案及缓冲电路用基板中的另一者，因此能够在设置了缓冲电路后确认缓冲电路的耐压。
附图说明
图1是表示实施方式1涉及的半导体装置的结构的一个例子的剖视图。
图2是表示实施方式1涉及的半导体装置的实施绝缘耐压试验的电路的一个例子的图。
图3是表示关联半导体装置的结构的剖视图。
图4是表示实施方式2涉及的半导体装置的结构的一个例子的剖视图。
图5是图4所示的半导体装置的俯视图。
图6是表示实施方式3涉及的构成半导体装置的电路的一个例子的图。
图7是图6所示的半导体装置的俯视图。
具体实施方式
下面，基于附图对本发明的实施方式进行说明。
<实施方式1>
图1是表示本实施方式1涉及的半导体装置的结构的一个例子的剖视图。
如图1所示，半导体装置具有绝缘基板1、基座板5、P侧电路图案6、N侧电路图案7、电路图案8、半导体元件9、缓冲电路用基板14、电阻15、电容器16。此外，将P侧电路图案6、N侧电路图案7及电路图案8统称为电路图案。
半导体装置也可以还具有包围上述各结构要素的壳体，也可以还具有填充于该壳体的树脂。
绝缘基板1包含绝缘层2及金属图案3。绝缘层2例如也可以是陶瓷。金属图案3设置于绝缘层2的下表面。
基座板5经由接合材料4与金属图案3接合。接合材料4例如由焊料等构成。基座板5例如由铜等构成。
在绝缘基板1的绝缘层2之上，彼此分离地设置有P侧电路图案6、N侧电路图案7及电路图案8。半导体元件9设置于P侧电路图案6之上。电容器16的一端经由接合材料17与N侧电路图案7电连接，另一端经由接合材料18与电路图案8电连接。
在绝缘基板1的绝缘层2之上经由接合材料10接合有缓冲电路用基板14。接合材料10例如由硅类的材料构成，包含硅。缓冲电路用基板14是与P侧电路图案6、N侧电路图案7及电路图案8各自分离地设置的。
缓冲电路用基板14包含绝缘层11及缓冲电路图案12、13。绝缘层11例如也可以是陶瓷。缓冲电路图案12、13设置于绝缘层11之上。电阻15的一端与缓冲电路图案12电连接，另一端与缓冲电路图案13电连接。
配线19将P侧电路图案6和缓冲电路图案12电连接。配线20将电路图案8和缓冲电路图案13电连接。
就图1所示的半导体装置而言，电阻15及电容器16构成缓冲电路。此外，缓冲电路实质上包含电阻体及电容器即可，并不限于图1所示的结构。例如，也可以将电阻15及电容器16设置于与图1所示的结构相反的位置。在该情况下，电阻15的一端经由接合材料17与N侧电路图案7电连接，另一端经由接合材料18与电路图案8电连接。另外，电容器16的一端与缓冲电路图案12电连接，另一端与缓冲电路图案13电连接。
如上所述，半导体元件9与缓冲电路电连接。因此，在半导体元件9进行通断时产生的噪声能够通过缓冲电路去除。半导体元件9例如是MOSFET(Metal Oxide SemiconductorField Effect Transistor)、IGBT(Insulated Gate Bipolar Transistor)、SBD(SchottkyBarrier Diode)、PN二极管中的至少1个。另外，半导体元件9可以是这些元件中的任意1个，也可以是组合了这些元件的电路。下面，作为一个例子，将半导体元件9设为具有上桥臂及下桥臂的逆变器而进行说明。
此外，半导体元件9设置于P侧电路图案6之上，但并不限于此。例如，半导体元件9也可以设置于N侧电路图案7之上等。另外，在图1的例子中，半导体元件9经由P侧电路图案6及配线19与缓冲电路电连接，但也可以经由P侧电路图案6及配线19之外的结构要素与缓冲电路电连接。
图2是表示本实施方式1涉及的半导体装置的实施绝缘耐压试验的电路的一个例子的图。具体而言，绝缘耐压试验是具有本实施方式1涉及的半导体装置的半导体模块的对地间的绝缘耐压试验，更具体而言是对缓冲电路的耐压进行检查的试验。在实施该试验时，P极及N极为相同电位，P侧电路图案6及N侧电路图案7也为相同电位。
这里，对与本实施方式1涉及的半导体装置相关联的半导体装置(下面，设为“关联半导体装置”)进行说明。
图3是表示关联半导体装置的结构的剖视图。对图3所示的关联半导体装置的结构要素中的与本实施方式1涉及的半导体装置的结构要素相同或类似的结构要素标注相同参照标号，主要对不同的结构要素进行说明。
如图3所示，就关联半导体装置而言，P侧电路图案6在平面方向延伸，缓冲电路用基板14通过焊料等接合材料10与该延伸部分接合。另外，交流电源25的一端与P侧电路图案6及N侧电路图案7连接，另一端与基座板5连接。
如果在缓冲电路用基板14的绝缘层11没有产生图3所示那样的裂缝26的情况下进行绝缘耐压试验，则对P侧电路图案6及N侧电路图案7与基座板5之间的电气特性进行检测。另一方面，在缓冲电路用基板14的绝缘层11产生图3所示那样的裂缝26，缓冲电路与P侧电路图案6短路的情况下，由于缓冲电路相对于P侧电路图案6位于与基座板5相反侧，因此，如果进行绝缘耐压试验，则也对P侧电路图案6及N侧电路图案7与基座板5之间的电气特性进行检测。这样，就图3所示的关联半导体装置而言，通过绝缘耐压试验检测的电气特性不会与缓冲电路用基板14的绝缘层11中的裂缝26的产生对应地变化。因此，就图3所示的关联半导体装置而言，在设置了缓冲电路后无法对缓冲电路用基板14的绝缘层11中的裂缝26的产生进行检测，而且无法对缓冲电路用基板14的耐压进行检测。
相对于此，就本实施方式1涉及的图1所示的半导体装置而言，在绝缘基板1的绝缘层2之上，彼此分离地设置有缓冲电路用基板14、P侧电路图案6、N侧电路图案7及电路图案8。如果针对这样的结构进行绝缘耐压试验，则对P侧电路图案6、N侧电路图案7及缓冲电路用基板14与基座板5之间的电气特性进行检测。而且，所检测的电气特性与缓冲电路用基板14的绝缘层11中的裂缝的产生对应地变化。因此，根据本实施方式1涉及的图1所示的半导体装置，能够在设置了缓冲电路后对缓冲电路用基板14的绝缘层11中的裂缝的产生进行检测，而且能够对缓冲电路用基板14的耐压进行检测。由此，能够对构成电阻15及电容器16的缓冲电路的耐压进行检测，因此能够防止半导体装置的不合格品外流，期待半导体装置的品质提高。
另外，如图1所示，分别将电阻15设置于缓冲电路用基板14，将电容器16设置于N侧电路图案7及电路图案8。由此，构成缓冲电路的布局的自由度提高，能够在维持半导体装置的小型化或半导体装置的尺寸的状态下实现大容量化。
此外，半导体元件9也可以包含碳化硅(SiC)。半导体元件9包含碳化硅的半导体装置与半导体元件9包含硅(Si)的半导体装置相比，能够进一步在高温环境下进行动作。半导体元件9包含碳化硅的半导体装置存在在进行通断动作时显著产生阻尼振荡这样的问题。相对于此，根据本实施方式1涉及的半导体装置，能够通过缓冲电路降低阻尼振荡的产生。
在半导体装置的制造工序中，也可以实施下述步骤1～3。此外，在步骤1～3中，也可以替代电阻而为电容器。
在步骤1中，对设置了电阻的缓冲电路用基板14单体实施绝缘耐压试验。接着，在步骤2中，将缓冲电路用基板14设置于绝缘基板1之上，通过配线19将缓冲电路用基板14和P侧电路图案6电连接，通过配线20将缓冲电路用基板14和电路图案8电连接。接着，在步骤3中，在完成半导体装置后，对缓冲电路实施绝缘耐压试验。
通过实施上述步骤1～3，能够进一步提高缓冲电路的绝缘耐量的检查精度，期待半导体装置的品质提高。
<实施方式2>
图4是表示本实施方式2涉及的半导体装置的结构的一个例子的剖视图。图5是图4所示的半导体装置的俯视图。
如图4、5所示，本实施方式2涉及的半导体装置的特征在于，与在N侧电路图案7及电路图案8之上设置的电容器16并联地设置配线27。由于其它结构与图1所示的实施方式1涉及的半导体装置相同，因此这里省略详细的说明。
配线27的一端与N侧电路图案7连接，另一端与电路图案8连接。
通过设为图4、5所示的结构，从而在实施方式1中说明过的绝缘耐压试验时，对于与电容器16连接的电路图案8也能够施加与P侧电路图案6及N侧电路图案7相同的电位，能够更可靠地对缓冲电路的耐压进行确认。由此，能够期待半导体装置的进一步的品质提高。
此外，在实施了绝缘耐压试验后，配线27由于半导体元件9的通电时的通电电流而熔断。
在上面，对在N侧电路图案7及电路图案8之上设置电容器16，在缓冲电路用基板14设置电阻15的结构进行了说明，但并不限于此。例如，在N侧电路图案7及电路图案8之上设置电阻15，在缓冲电路用基板14设置电容器16的结构也得到与上述相同的效果。
<实施方式3>
图6是表示本实施方式3涉及的构成半导体装置的电路的一个例子的图。图7是图6所示的半导体装置的俯视图。
如图6、7所示，本实施方式3涉及的半导体装置的特征在于，缓冲电路并非是在P端子-N端子间而是在各桥臂构成的。由于其它结构与实施方式1相同，因此这里省略详细的说明。
如图6所示，在P端子-U端子间，半导体元件9a与缓冲电路28a并联连接。缓冲电路28a由电阻15a及电容器16a构成。另外，在U端子-N端子间，半导体元件9b与缓冲电路28b并联连接。缓冲电路28b由电阻15b及电容器16b构成。即，缓冲电路28a是在上桥臂构成的，缓冲电路28b是在下桥臂构成的。通过这样的结构，能够在更接近半导体元件9a、9b的位置设置缓冲电路28a、28b，因此能够实现更高的阻尼振荡的抑制效果。
如果想要在各桥臂构成缓冲电路，则在电路图案的构造上，构成缓冲电路的空间受到限制。但是，根据图7所示的本实施方式3涉及的半导体装置，由于构成缓冲电路28a、28b的电阻15a、15b设置于与绝缘基板1之上的P侧电路图案6、N侧电路图案7及电路图案8分离的位置，因此布局的自由度高，能够在狭窄的空间设置缓冲电路。在该情况下，构成缓冲电路的电容器16a、16b能够设置于已有的电路图案(P侧电路图案6、N侧电路图案7及电路图案8)之上。
此外，本发明可以在本发明的范围内将各实施方式自由地组合，对各实施方式适当进行变形、省略。
标号的说明
1绝缘基板，2绝缘层，3金属图案，4接合材料，5基座板，6P侧电路图案，7N侧电路图案，8电路图案，9半导体元件，10接合材料，11绝缘层，12、13缓冲电路图案，14缓冲电路用基板，15电阻，16电容器，17、18接合材料，19、20配线，21缓冲电路图案，22、23接合材料，24配线，25交流电源，26裂缝，27配线，28a、28b缓冲电路，29P侧电路图案，30U侧电路图案，31P侧电路图案。

Claims (7)

1.一种半导体装置，其具有：
绝缘基板；
电路图案，其设置于所述绝缘基板之上；
缓冲电路用基板，其在所述绝缘基板之上与所述电路图案分离地设置；
电阻，其设置于所述电路图案及所述缓冲电路用基板中的一者；
电容器，其设置于所述电路图案及所述缓冲电路用基板中的另一者；以及
半导体元件，其与所述电阻及所述电容器电连接。
2.根据权利要求1所述的半导体装置，其中，
所述电阻设置于所述缓冲电路用基板，
所述电容器设置于所述电路图案。
3.根据权利要求1或2所述的半导体装置，其中，
还具有在所述电路图案处与设置于该电路图案的所述电阻或所述电容器并联地设置的配线。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于，
所述半导体元件存在多个，
所述电阻及所述电容器与至少1个所述半导体元件连接。
5.根据权利要求1至4中任一项所述的半导体装置，其中，
所述半导体元件包含碳化硅。
6.根据权利要求1至5中任一项所述的半导体装置，其中，
所述缓冲电路用基板具有绝缘层、在该绝缘层之上设置的缓冲电路图案，
所述电阻或所述电容器设置于所述缓冲电路图案之上。
7.一种半导体装置的制造方法，所述半导体装置是权利要求1至6中任一项所述的半导体装置，
该半导体装置的制造方法具有如下工序：
工序(a)，对设置了所述电阻或所述电容器的所述缓冲电路用基板单体实施绝缘耐压试验；
工序(b)，在所述工序(a)后，将所述缓冲电路用基板设置于所述绝缘基板之上，将所述缓冲电路用基板和所述电路图案电连接；以及
工序(c)，在所述工序(b)后，对由所述电阻及所述电容器构成的缓冲电路实施绝缘耐压试验。
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