CN113192990B - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
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- CN113192990B CN113192990B CN202110621148.7A CN202110621148A CN113192990B CN 113192990 B CN113192990 B CN 113192990B CN 202110621148 A CN202110621148 A CN 202110621148A CN 113192990 B CN113192990 B CN 113192990B
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- 238000009413 insulation Methods 0.000 claims abstract description 17
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- 239000011229 interlayer Substances 0.000 claims description 63
- 239000000463 material Substances 0.000 claims description 26
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 19
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- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate includes: a substrate; a first gate insulating layer located at one side of the substrate; the second grid insulation layer is positioned on one side of the first grid insulation layer away from the substrate, the first semiconductor layer and the grid layer, the first semiconductor layer is positioned on one side of the first grid insulation layer close to the substrate, and the grid layer is positioned on one side of the second grid insulation layer away from the substrate; or, the first semiconductor layer is located at a side of the second gate insulating layer away from the substrate, the gate layer is located at a side of the first gate insulating layer close to the substrate, and the second semiconductor layer is located between the first gate insulating layer and the second gate insulating layer. According to the technical scheme provided by the embodiment of the invention, the distance between the first semiconductor layer and the second semiconductor layer can be greatly reduced by arranging the double-layer grid insulating layer, so that the number of mask processes can be saved in the process of forming the thin film transistor on the array substrate, and the production cost is reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
With the rapid development of display technology, display devices have been made to exhibit a trend of high integration and low cost.
The low-temperature poly Oxide (Low Temperature Poly-Oxide, LTPO) technology is an emerging thin film transistor technology in recent years, but the current LTPO technology is complex in technology, and the number of patterning technology is more, so that the production cost of the array substrate is not reduced.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a manufacturing method thereof and a display panel, which are used for simplifying the patterning process of the array substrate, so that the production cost of the array substrate is reduced.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
A substrate;
A first gate insulating layer located at one side of the substrate;
the second gate insulating layer is positioned on one side of the first gate insulating layer away from the substrate and is in contact with the first gate insulating layer;
a first semiconductor layer and a gate layer, wherein the first semiconductor layer is positioned on one side of the first gate insulating layer close to the substrate, the first gate insulating layer covers the first semiconductor layer, and the gate layer is positioned on one side of the second gate insulating layer far from the substrate and is in contact with the second gate insulating layer; or alternatively
The first semiconductor layer is positioned on one side of the second gate insulating layer away from the substrate, the gate layer is positioned on one side of the first gate insulating layer close to the substrate, and the first gate insulating layer covers the gate layer;
A second semiconductor layer located between the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer covers the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer are different in material.
Optionally, the material of the first semiconductor layer includes polysilicon, the material of the second semiconductor layer includes metal oxide, the first semiconductor layer includes a first active layer, the second semiconductor layer includes a second active layer, and there is no overlap between the orthographic projection of the first active layer on the substrate and the orthographic projection of the second active layer on the substrate.
Optionally, when the first semiconductor layer is located on a side of the first gate insulating layer close to the substrate, and the first gate insulating layer covers the first semiconductor layer, the gate layer is located on a side of the second gate insulating layer far from the substrate, and is in contact with the second gate insulating layer;
the array substrate further includes:
A first interlayer insulating layer; the grid electrode layer is positioned on one side of the substrate far away from the substrate and covers the grid electrode layer;
The source-drain electrode layer is positioned on one side, far away from the substrate, of the first interlayer insulating layer, and comprises a first source-drain electrode layer and a second source-drain electrode layer which are arranged in the same layer;
The first source/drain electrode layer is in contact with the first semiconductor layer through a first via hole penetrating through the first interlayer insulating layer; the second source/drain electrode layer is in contact with the second semiconductor layer through a second via hole penetrating through the first interlayer insulating layer.
Optionally, the gate layer includes a first gate layer and a second gate layer, the first gate layer and the second gate layer being disposed on the same layer; the orthographic projection of the first grid layer on the substrate falls into the orthographic projection of the first semiconductor layer on the substrate, and the orthographic projection of the second grid layer on the substrate falls into the orthographic projection of the second semiconductor layer on the substrate.
Optionally, the array substrate further includes a capacitor electrode layer, where the capacitor electrode layer includes a first electrode layer and a second electrode layer, the first electrode layer is shared with the second gate layer, and the second electrode layer is located on a side of the first interlayer insulating layer away from the substrate and is disposed on the same layer as the source drain layer.
Optionally, the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the second electrode layer on the substrate.
Optionally, the semiconductor device further comprises a second interlayer insulating layer, a third interlayer insulating layer, a planarization layer and a plurality of connection electrode layers;
The second interlayer insulating layer is positioned on one side of the source-drain electrode layer, which is far away from the substrate, the connecting electrode layer is positioned on one side of the second interlayer insulating layer, which is far away from the substrate, a plurality of connecting electrode layers are arranged on the same layer, and each connecting electrode layer is respectively contacted with the first source-drain electrode layer and the second source-drain electrode layer through a third via hole penetrating through the second interlayer insulating layer;
The third interlayer insulating layer and the flattening layer are sequentially stacked on one side, away from the substrate, of the connecting electrode layer.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes: providing a substrate;
forming a first semiconductor layer on one side of the substrate;
A first grid insulation layer and a second semiconductor layer are sequentially formed on one side, far away from the substrate, of the first semiconductor layer, and the first grid insulation layer covers the first semiconductor layer;
forming a second gate insulating layer on one side of the first gate insulating layer far away from the substrate, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
and forming a gate layer on one side of the second gate insulating layer away from the substrate, wherein the gate layer is in contact with the second gate insulating layer.
Optionally, the manufacturing method of the array substrate includes:
Providing a substrate;
Forming a gate layer on one side of the substrate;
a first gate insulating layer and a second semiconductor layer are sequentially formed on one side, far away from the substrate, of the gate layer, and the first gate insulating layer covers the gate layer;
forming a second gate insulating layer on one side of the first gate insulating layer far away from the substrate, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
And forming a first semiconductor layer on one side of the second gate insulating layer away from the substrate, wherein the first semiconductor layer is in contact with the second gate insulating layer.
In a third aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in any embodiment of the present invention.
According to the technical scheme provided by the embodiment of the invention, through the form of arranging the double-layer grid insulation layer, a protective layer is not required to be arranged between the first semiconductor layer and the second semiconductor layer, so that the second semiconductor layer is positioned between the first grid insulation layer and the second grid insulation layer, the first semiconductor layer and the second semiconductor layer share the second grid insulation layer, the first thin film transistor formed by the first semiconductor layer is of a double-layer grid insulation layer structure, the second thin film transistor formed by the second semiconductor layer is of a single-layer grid insulation layer structure, and the distance between the first semiconductor layer and the second semiconductor layer can be greatly reduced, namely the film thickness between the two thin film transistors is reduced. In the process of forming the thin film transistor on the array substrate, the number of masks can be saved, and the production cost is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of an array substrate according to the prior art;
fig. 2 is a schematic cross-sectional structure of an array substrate according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of another embodiment of an array substrate;
FIG. 4 is a schematic cross-sectional view of another embodiment of an array substrate;
FIG. 5 is a schematic cross-sectional view of another embodiment of an array substrate;
FIG. 6 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 7 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention;
Fig. 8-19 are schematic views of specific structures formed by corresponding method steps of the array substrate;
Fig. 20 is a schematic cross-sectional structure of another array substrate according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
As described in the background art, a plurality of thin film transistors are arranged on the array substrate in an array manner, the patterning process of the array substrate is complex, and the number of masks required for forming the array substrate is large, so that the production cost of the array substrate is high. Fig. 1 is a schematic cross-sectional structure of an array substrate according to the prior art, referring to fig. 1, the array substrate according to the prior art includes a substrate 10, a first semiconductor layer 22 and a first insulating layer 20 on the substrate, a first gate electrode 22 and a capacitor lower plate 41 are disposed on an upper surface of the first insulating layer 20, a first interlayer insulating layer 30 covers the first insulating layer 20, and a contact electrode and a capacitor upper plate 42 connected to the first semiconductor layer 22 are formed on a side of the first interlayer insulating layer 30 away from the substrate 10. The semiconductor device further comprises a protective layer 40 arranged on the first interlayer insulating layer 30, and a second semiconductor layer 31, a second insulating layer 32 and a second gate electrode 33 which are sequentially stacked on one side of the protective layer 40 away from the substrate 10, wherein the second gate electrode 33 is covered by the second interlayer insulating layer 50. The first semiconductor layer 21, the first insulating layer 20, and the first gate electrode 21 constitute a first transistor, and the second semiconductor layer 31, the second insulating layer 32, and the second gate electrode 33 constitute a second transistor. In the prior art, at least 7 patterning processes are required from the substrate 10 to the second interlayer insulating layer 50, and the processes are complex, which is not beneficial to reducing the production cost of the array substrate.
Based on the above-mentioned problems, the embodiment of the invention provides an array substrate to reduce the number of patterning processes. Fig. 2 is a schematic cross-sectional structure of an array substrate according to an embodiment of the present invention, and referring to fig. 2, the array substrate according to the embodiment of the present invention includes: a substrate 100; a first gate insulating layer 200 located at one side of the substrate 100; the second gate insulating layer 300 is located at a side of the first gate insulating layer 200 away from the substrate 100 and contacts the first gate insulating layer 200.
The first semiconductor layer 101 and the gate electrode layer 110, the first semiconductor layer 101 is located at a side of the first gate insulating layer 200 close to the substrate 100, the first gate insulating layer 200 covers the first semiconductor layer 101, and the gate electrode layer 110 is located at a side of the second gate insulating layer 300 far from the substrate 100 and is in contact with the second gate insulating layer 300; a second semiconductor layer 201 between the first gate insulating layer 200 and the second gate insulating layer 300, and the second gate insulating layer 300 covers the second semiconductor layer 201; wherein the materials of the first semiconductor layer 101 and the second semiconductor layer 201 are different.
In particular, the substrate 100 may be flexible, may be formed of any insulating material having flexibility, and the substrate 100 may be rigid, such as a glass substrate. The first semiconductor layer 101 is disposed on the substrate 100, a first gate insulating layer 200 is disposed on a side of the first semiconductor layer 101 away from the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101. A second semiconductor layer 201 is formed on a side of the first gate insulating layer 200 away from the substrate 100, and in this embodiment, since materials of the first semiconductor layer 101 and the second semiconductor layer 201 are different, the first semiconductor layer 101 and the second semiconductor layer 201 are formed in different etching steps, the first gate insulating layer 200 serves to insulate the first semiconductor layer 101 from the second semiconductor layer 201, and the second gate insulating layer 300 covers the second semiconductor layer 201. The gate layer 110 is disposed on a side of the second gate insulating layer 300 away from the substrate 100.
Doping the first semiconductor layer 101 and the second semiconductor layer 201 may form a source electrode and a drain electrode as thin film transistors, the first semiconductor layer 101 and the gate layer 110 together forming a first thin film transistor, and the second semiconductor layer 201 and the gate layer 110 together forming a second thin film transistor. Therefore, the process flow for forming the thin film transistor in this embodiment at least includes:
Process 1, a substrate 100 is formed.
Process 2, forming a first semiconductor layer 101.
Process 3, forming a first gate insulating layer 200 and a second semiconductor layer 201.
Process 4, forming a second gate insulating layer 300 and a gate layer 110.
It should be noted that, in the process of forming the film pattern and the process of punching the film, a mask process is required. Therefore, in the above process flow, a mask is required to be used in forming the first semiconductor layer 101, the second semiconductor layer 201 and the gate layer 110.
Referring to fig. 1, the process flow for forming a thin film transistor in the prior art at least includes:
Process 1, a substrate 10 is formed.
Process 2, forming a first semiconductor layer 21.
Process 3, forming a first insulating layer 20 and a first gate 22.
Process 4, forming a first interlayer insulating layer 30, and etching the via hole.
In process 5, the protective layer 40 and the second semiconductor layer 31 are formed.
Process 6, forming a second insulating layer 32 and a second gate 33.
In the prior art shown in fig. 1, masks are required to be used in forming the first semiconductor layer 21, the first gate 22, the first interlayer insulating layer, the second semiconductor layer 31 and the second gate 33, so that at least two mask processes can be saved in the process of forming the thin film transistor on the array substrate by using the technical scheme provided by the embodiment of the invention, and the number of masks is correspondingly reduced. And through setting up the form of bilayer gate insulating layer, need not to set up the protective layer between first semiconductor layer 101 and second semiconductor layer 201 for second semiconductor layer 201 is located between first gate insulating layer 200 and the second gate insulating layer 300, can make first semiconductor layer 101 and second semiconductor layer 201 share second gate insulating layer 300, with the first thin film transistor of first semiconductor layer 101 formation for bilayer gate insulating layer structure, with the second thin film transistor of second semiconductor layer 201 formation for monolayer gate insulating layer structure, can reduce the distance between first semiconductor layer 101 and the second semiconductor layer 201 greatly, namely reduced the rete thickness between two thin film transistors.
Fig. 3 is a schematic cross-sectional structure of another array substrate according to an embodiment of the present invention, which is different from the array substrate shown in fig. 2 in that the thin film transistor in the array substrate shown in fig. 3 is a bottom gate structure, and the thin film transistor in fig. 2 is a top gate structure. The film layer structures of the two are the same, and the adopted process is the same, so that the thin film transistor with the bottom gate structure is not described herein again.
With continued reference to fig. 2, the material of the first semiconductor layer 101 comprises polysilicon, the material of the second semiconductor layer 201 comprises a metal oxide, the first semiconductor layer 101 comprises a first active layer, the second semiconductor layer 201 comprises a second active layer, and there is no overlap between the orthographic projection of the first active layer on the substrate 100 and the orthographic projection of the second active layer on the substrate 100.
In general, the low-temperature polysilicon thin film transistor has high mobility and small size, and the metal oxide thin film transistor has low leakage current, so that low-frequency driving can be realized, and therefore, part of the thin film transistors in the pixel circuit of the display area adopt the metal oxide thin film transistors. The technical scheme provided by the embodiment of the invention can be applied to the scanning driving circuit in the non-display area, the pixel circuit in the display area, and the scanning driving circuit in the non-display area and the pixel circuit in the display area at the same time.
In this embodiment, the array substrate is formed by LTPO technology, the material of the first semiconductor layer 101 includes polysilicon, and the material of the second semiconductor layer 201 includes metal oxide. Because the materials of the first semiconductor layer 101 and the second semiconductor layer 201 are different, the excimer laser annealing process is required in the manufacturing process, and the excimer laser annealing process is not required in the second semiconductor layer 201, so the first semiconductor layer 101 and the second semiconductor layer 201 are not arranged on the same layer and are required to be formed in different process steps respectively. Wherein the first semiconductor layer 101 includes a first active layer, and the second semiconductor layer 201 includes a second active layer, which in the present embodiment can be understood as the first active layer is the first semiconductor layer 101, and the second active layer is the second semiconductor layer 201; in other embodiments, the first semiconductor layer 101 and the second semiconductor layer 201 may further include a conductive region formed by ion heavy doping to form a metal connection line. The front projection of the first active layer on the substrate 100 and the front projection of the second active layer on the substrate 100 are not overlapped, so that interference between the front projection and the front projection is prevented, and the display effect is not facilitated.
The embodiment of the invention is illustrated by taking a thin film transistor with a top gate structure as an example. Fig. 4 is a schematic cross-sectional structure of another array substrate according to the embodiment of the present invention, and referring to fig. 4, when the first semiconductor layer 101 is located on a side of the first gate insulating layer 200 close to the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101, the gate layer 110 is located on a side of the second gate insulating layer 300 far from the substrate 100 and contacts the second gate insulating layer 300, the array substrate further includes:
a first interlayer insulating layer 400; the gate layer 110 is located at a side of the gate layer 110 away from the substrate 100 and covers the gate layer 110.
The source-drain electrode layer is positioned on one side of the first interlayer insulating layer 400 far away from the substrate 100, and comprises a first source-drain electrode layer 310 and a second source-drain electrode layer 320, wherein the first source-drain electrode layer 310 and the second source-drain electrode layer 320 are arranged in the same layer; the first source/drain layer 310 contacts the first semiconductor layer 101 through a first via hole penetrating the first interlayer insulating layer 400; the second source/drain electrode layer 320 contacts the second semiconductor layer 201 through a second via hole penetrating the first interlayer insulating layer 400.
Specifically, the gate layer 110 includes a first gate layer 102 and a second gate layer 202, and the first gate layer 102 and the second gate layer 202 are arranged in the same layer; the front projection of the first gate layer 102 onto the substrate 100 falls into the front projection of the first semiconductor layer 101 onto the substrate 100, and the front projection of the second gate layer 202 onto the substrate 100 falls into the front projection of the second semiconductor layer 101 onto the substrate 100. The first interlayer insulating layer 400 covers the gate layer 110, and a first via hole and a second via hole are provided on the first interlayer insulating layer 400, and conductive materials are filled in the first via hole and the second via hole so as to lead out the source and drain electrodes on the first semiconductor layer 101 and the second semiconductor layer 201. The first source/drain layer 310 includes a source electrode 31 and a drain electrode 32 of the first thin film transistor, and the second source/drain layer 320 includes a source electrode 33 and a drain electrode 34 of the second thin film transistor.
With continued reference to fig. 4, the array substrate further includes a capacitor electrode layer, where the capacitor electrode layer includes a first electrode layer 203 and a second electrode layer 204, the first electrode layer 203 is shared with the second gate layer 202, and the second electrode layer 204 is located on a side of the first interlayer insulating layer 400 away from the substrate 100 and is disposed in the same layer as the source drain layer.
Specifically, the capacitor electrode layer has a first electrode layer 203 and a second electrode layer 204, the first electrode layer 203 and the second electrode layer 204, and a first interlayer insulating layer 400 interposed between the first electrode layer 203 and the second electrode layer 204 collectively form a storage capacitor for storing a gate voltage of a driving transistor in a pixel circuit, for example, a pixel circuit of a display region. The second electrode layer 204 is configured on a side of the first electrode layer 203 away from the substrate 100 (of course, in other embodiments, the second electrode layer 204 may also be configured on a side of the first electrode layer 203 close to the substrate 100), and the second electrode layer 204 is disposed on the same layer as the source/drain layer. By sharing the first electrode layer 203 of the capacitor electrode layer with the second gate layer 202, in other words, multiplexing the second gate layer 202 into the first electrode layer 203, the second gate layer 200 can be used as a gate of a thin film transistor or a plate of a storage capacitor, so that the film space on the array substrate can be greatly reduced, and more pixel regions can be arranged on the array substrate, which is beneficial to improving the resolution of the display panel. Meanwhile, the manufacturing process of the array substrate can be reduced, and the production cost is reduced.
Taking the array substrate shown in fig. 4 as an example, the formation of the thin film transistor and the storage capacitor on the substrate 100 at least includes the following process flows:
Process 1, a substrate 100 is formed.
Process 2, forming a first semiconductor layer 101.
Process 3, forming a first gate insulating layer 200 and a second semiconductor layer 201.
Process 4, forming a second gate insulating layer 300 and a gate layer 110.
Process 5, forming a first interlayer insulating layer 400.
And 6, forming a second electrode layer 204 of the source and drain electrode layers and the capacitor electrode layer.
As shown in fig. 1, the prior art for forming a thin film transistor and a storage capacitor on a substrate includes at least the following process flows:
Process 1, a substrate 10 is formed.
Process 2, forming a first semiconductor layer 21.
Process 3, forming a first insulating layer 20, a first gate 22, and a capacitor bottom plate 41.
Process 4, forming a first interlayer insulating layer 30, and etching the via hole.
Process 5, forming a capacitor top plate 42 and a first source drain layer.
In process 6, the protective layer 40 and the second semiconductor layer 31 are formed.
Process 7, forming a second insulating layer 32 and a second gate 33.
And 8, forming a second source/drain electrode layer.
Therefore, compared with the prior art, in the process of forming the thin film transistor and the storage capacitor on the substrate, the technical scheme provided by the embodiment at least can reduce two mask processes, and the film space on the array substrate can be greatly reduced by sharing the second gate layer 202 and the first electrode layer 203 of the capacitor electrode layer, so that more pixel areas can be arranged, and the resolution of the display panel can be improved.
In the present embodiment, the orthographic projection of the first electrode layer 203 on the substrate 100 covers the orthographic projection of the second electrode layer 204 on the substrate 100. Because the first electrode layer 203 and the second gate layer 202 are shared, the size of the first electrode layer 203 is similar to the size of the second electrode layer 204 along the thickness direction of the thin film transistor, so that the capacitance of the storage capacitor can be increased on the basis of ensuring that the second thin film transistor has good electrical property, and the storage capacity of the storage capacitor can be improved.
Fig. 5 is a schematic cross-sectional structure of another array substrate according to an embodiment of the present invention, and on the basis of the above technical solutions, referring to fig. 4 and 5, the array substrate further includes a second interlayer insulating layer 500, a third interlayer insulating layer 600, a planarization layer 700, and a plurality of connection electrode layers 401.
The second interlayer insulating layer 500 is located at a side of the source/drain electrode layer away from the substrate 100, the connection electrode layer 401 is located at a side of the second interlayer insulating layer 500 away from the substrate 100, the plurality of connection electrode layers 401 are arranged in the same layer, and each connection electrode layer 401 is respectively contacted with the first source/drain electrode layer 310 and the second source/drain electrode layer 320 through a third via hole penetrating through the second interlayer insulating layer 500; the third interlayer insulating layer 600 and the planarization layer 700 are sequentially stacked on the connection electrode layer 401 on the side away from the substrate 100.
In order to facilitate the wiring of the metal wiring, the first source/drain layer 310 and the second source/drain layer 320 may be led out to the upper surface of the second interlayer insulating layer 500 through the connection electrode layer 401, respectively. The metal wiring includes at least one of a data signal line, a scan signal line and a power signal line.
The embodiment of the invention also provides a method for manufacturing an array substrate, and fig. 6 is a flowchart of the method for manufacturing an array substrate provided by the embodiment of the invention, and referring to fig. 6, the method for manufacturing an array substrate includes:
S110, providing a substrate.
S120, forming a first semiconductor layer on one side of the substrate.
S130, a first gate insulating layer and a second semiconductor layer are sequentially formed on one side, far away from the substrate, of the first semiconductor layer, and the first gate insulating layer covers the first semiconductor layer.
And S140, forming a second gate insulating layer on one side of the first gate insulating layer far away from the substrate, wherein the second gate insulating layer is contacted with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer.
And S150, forming a gate layer on one side of the second gate insulating layer away from the substrate, wherein the gate layer is contacted with the second gate insulating layer.
Referring to fig. 2 and 3, the substrate 100 may be flexible, may be formed of any insulating material having flexibility, and the substrate 100 may be rigid, such as a glass substrate. The first semiconductor layer 101 is formed on the substrate 100, the first gate insulating layer 200 is formed on a side of the first semiconductor layer 101 remote from the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101. The second semiconductor layer 201 is formed on a side of the first gate insulating layer 200 away from the substrate 100, in this embodiment, since the materials of the first semiconductor layer 101 and the second semiconductor layer 201 are different, the first semiconductor layer 101 and the second semiconductor layer 201 are formed in different etching steps, the first gate insulating layer 200 is used to insulate the first semiconductor layer 101 from the second semiconductor layer 201, the second gate insulating layer 300 covers the second semiconductor layer 201, and the gate layer 110 is formed on a side of the second gate insulating layer 300 away from the substrate 100.
Doping the first semiconductor layer 101 and the second semiconductor layer 201 may form a source electrode and a drain electrode as thin film transistors, the first semiconductor layer 101 and the gate layer 110 together forming a first thin film transistor, and the second semiconductor layer 201 and the gate layer 110 together forming a second thin film transistor.
In this embodiment, the process flow of forming the gate layer 110 on the substrate 100 is as follows:
Process 1, a substrate 100 is formed.
In process 2, an amorphous silicon layer is deposited on the substrate 100, and the amorphous silicon is polycrystallized by Excimer laser annealing (specifier LASER ANNEAL, ELA) to form a polycrystalline silicon layer. The polysilicon layer is then patterned by a photolithographic process (a reticle is required), and in order to prevent shrinkage dislocation of the amorphous silicon layer due to exposure to high temperatures, the amorphous silicon layer is preferably annealed between the patterning. After forming the patterned polysilicon layer, ion implantation (e.g., phosphorus ion or boron ion) is performed on the polysilicon layer, and doping is performed to form the first semiconductor layer 101, wherein the region of the first semiconductor layer 101 into which ions are not implanted forms a first active layer, and the region into which ions are implanted forms a source/drain.
In process 3, a first gate insulating layer 200 is formed on the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101, and the material of the first gate insulating layer 200 may be silicon oxide and/or silicon nitride. The first gate insulating layer 200 is used as an insulating layer of the first semiconductor layer 101, and in order to improve film formation quality of the first gate insulating layer 200, the first gate insulating layer 200 may be subjected to annealing treatment for the purpose of dehydrogenation and film density improvement. Then, a metal oxide layer, such as indium gallium zinc oxide, is formed on a side of the first gate insulating layer 200 remote from the substrate 100, and the metal oxide layer may be formed by a sputtering method. After forming the metal oxide layer, patterning the metal oxide layer through a photolithography process (a mask is needed), performing ion implantation (such as phosphorus ion or boron ion) on the metal oxide layer after forming the patterned metal oxide layer, doping to form a second semiconductor layer 201, wherein a region in the second semiconductor layer 201, into which ions are not implanted, forms a second active layer, and the region into which ions are implanted forms a source drain.
In process 4, a second gate insulating layer 300 is formed on a side of the second semiconductor layer 201 away from the substrate 100, and the second gate insulating layer 300 covers the second semiconductor layer 201 and contacts the first gate insulating layer 200, and the material of the second gate insulating layer 300 may be silicon oxide and/or silicon nitride. The gate layer 110 is formed at a side of the second gate insulating layer 300 remote from the substrate 100, and the gate layer 110 may be formed using a sputtering method, wherein the material of the gate layer 110 may be Mo/Al/Mo, ti/Al/Ti, or the like.
In combination with the prior art of fig. 1, the technical solution provided in the embodiment of the present invention does not need to provide a protective layer between the first semiconductor layer 101 and the second semiconductor layer 201 by providing a double-layer gate insulating layer, so that the second semiconductor layer 201 is located between the first gate insulating layer 200 and the second gate insulating layer 300, the first semiconductor layer 101 and the second semiconductor layer 201 can share the second gate insulating layer 300, the first thin film transistor formed by the first semiconductor layer 101 is in a double-layer gate insulating layer structure, and the second thin film transistor formed by the second semiconductor layer 201 is in a single-layer gate insulating layer structure, so that the distance between the first semiconductor layer 101 and the second semiconductor layer 201 can be greatly reduced, that is, the thickness of a film layer between the two thin film transistors is reduced, and at least two mask processes can be saved in the process of forming the thin film transistors on the array substrate.
Fig. 7 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention, and referring to fig. 7, the method for manufacturing an array substrate includes:
s210, providing a substrate.
S220, forming a gate layer on one side of the substrate.
And S230, sequentially forming a first gate insulating layer and a second semiconductor layer on one side of the gate layer far away from the substrate, wherein the first gate insulating layer covers the gate layer.
S240, forming a second gate insulating layer on one side of the first gate insulating layer far away from the substrate, wherein the second gate insulating layer is contacted with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer.
S250, forming a first semiconductor layer on one side of the second gate insulating layer away from the substrate, wherein the first semiconductor layer is in contact with the second gate insulating layer.
Specifically, the manufacturing method of the array substrate shown in fig. 7 is that the thin film transistor with the bottom gate structure is formed, and the process flow is the same as that of the method for forming the thin film transistor with the top gate structure shown in fig. 6, and the difference is only that the sequence of the processes is different, and the specific working principle is not described herein.
Alternatively, fig. 8 to 19 are schematic diagrams of specific structures formed by corresponding method steps of the array substrate, and based on the above technical solutions, referring to fig. 8 to 19, the embodiment uses a thin film transistor with a top gate structure as an example for illustration.
In the process 1, a substrate 100 is provided, and a protective layer 810 is formed on the substrate 100, where the material of the protective layer 810 may be a polyimide film.
In process 2, the buffer layer 820 is formed on the side of the protective layer 810 away from the substrate 100, and the buffer layer 820 may be formed of an inorganic material, and the protective layer 810 and the buffer layer 820 may perform a buffer protection function on the array substrate. An amorphous silicon layer is deposited on a side of the buffer layer 820 remote from the substrate 100, and the amorphous silicon is polycrystallized by Excimer laser annealing (specifier LASER ANNEAL, ELA) to form a polysilicon layer. The polysilicon layer is then patterned by a photolithographic process (a reticle is required), and in order to prevent shrinkage dislocation of the amorphous silicon layer due to exposure to high temperatures, the amorphous silicon layer is preferably annealed between the patterning. After forming the patterned polysilicon layer, ion implantation (e.g., phosphorus ion or boron ion) is performed on the polysilicon layer, and doping is performed to form the first semiconductor layer 101, wherein the region of the first semiconductor layer 101 into which ions are not implanted forms a first active layer, and the region into which ions are implanted forms a source/drain.
In process 3, a first gate insulating layer 200 is formed on the substrate 100, and the first gate insulating layer 200 covers the first semiconductor layer 101, and the material of the first gate insulating layer 200 may be silicon oxide and/or silicon nitride. The first gate insulating layer 200 is used as an insulating layer of the first semiconductor layer 101, and in order to improve film formation quality of the first gate insulating layer 200, the first gate insulating layer 200 may be subjected to annealing treatment for the purpose of dehydrogenation and film density improvement. Then, a metal oxide layer, such as indium gallium zinc oxide, is formed on a side of the first gate insulating layer 200 remote from the substrate 100, and the metal oxide layer may be formed by a sputtering method. After forming the metal oxide layer, the metal oxide layer is patterned (using a mask) by a photolithography process to obtain the second semiconductor layer 201.
In process 4, a second gate insulating layer 300 is formed on a side of the second semiconductor layer 201 away from the substrate 100, and the second gate insulating layer 300 covers the second semiconductor layer 201 and contacts the first gate insulating layer 200, and the material of the second gate insulating layer 300 may be silicon oxide and/or silicon nitride. A metal film is sputtered on a side of the second gate insulating layer 300 remote from the substrate 100, and is etched using a photolithography process to form the gate layer 110 and the metal wiring layer 410, and the metal wiring layer 410 includes at least one of a data signal line, a scan signal line, and a power signal line. The material of the gate layer 110 may be Mo/Al/Mo, ti/Al/Ti, or the like. The gate layer 110 is patterned by a photolithography process to form the first gate layer 102 and the second gate layer 202. And performing ion implantation (such as phosphorus ions or boron ions) on the second semiconductor layer 201 by using the second gate layer 202 as a mask, and doping to form the second semiconductor layer 201, wherein the region of the second semiconductor layer 201, into which ions are not implanted, forms a second active layer, and the region into which ions are implanted forms a source/drain.
In process 5, a first interlayer insulating layer 400 is formed on a side of the gate layer 110 remote from the substrate 100, such that the first interlayer insulating layer 400 covers the gate layer 110. The first interlayer insulating layer 400 is etched using a photolithography process to form a first via hole and a second via hole. Illustratively, a positive photoresist layer is coated on the first interlayer insulating layer 400, the first interlayer insulating layer 400 is exposed at a position where the photoresist layer is illuminated by a mask, the first interlayer insulating layer 400 is etched to form a first via 11, a second via 12 and a trace via 41, respectively, and the photoresist layer is removed.
In process 6, a metal film is sputtered on a side of the first interlayer insulating layer 400 away from the substrate 100, and the metal film is filled into the first via hole and the second via hole, and etched by using a photolithography technique to form the first source drain electrode layer 310, the second source drain electrode layer 320, the second electrode layer 204, and the first connection electrode layer 510, respectively. The first connection electrode layer 510 is used for connecting to the metal wiring layer 410. In this embodiment, the capacitor electrode layer has the first electrode layer 203 and the second electrode layer 204, and the first interlayer insulating layer 400 sandwiched between the first electrode layer 203 and the second electrode layer 204 together form a storage capacitor, and by sharing the first electrode layer 203 and the second gate layer 202 of the capacitor electrode layer, that is, multiplexing the second gate layer 202 into the first electrode layer 203, the film space on the array substrate can be greatly reduced, so that more pixel regions can be disposed on the array substrate, which is further beneficial to improving the resolution of the display panel. Meanwhile, the manufacturing process flow of the array substrate can be reduced, and the production cost is reduced.
In the process 7, the second interlayer insulating layer 500 is formed on the side of the source/drain electrode layer away from the substrate 100, and the material of the second interlayer insulating layer 500 may be silicon oxide and/or silicon nitride, which plays an insulating role. A third via hole 42 penetrating the second interlayer insulating layer 500 is etched on the second interlayer insulating layer 500 using a photolithography technique.
In process 8, the film layer located in the bending region is etched by using photolithography technique to form a groove 520, so as to expose the protective layer 810 located on the substrate 100.
In process 9, the first planarization layer 530 is formed in the groove 520, where a material of the first planarization layer 530 may be an organic material, which is beneficial to reducing an internal stress of the bending region when the bending region is bent, so as to facilitate bending.
In the process 10, a metal film is sputtered on a side of the second interlayer insulating layer 500 away from the substrate 100, and the metal film is etched to form the second connection electrode layer 401, and the second connection electrode layer 401 is connected to the first source/drain electrode layer 310, the second source/drain electrode layer 320, and the first connection electrode layer 510, respectively.
In the process 11, a third interlayer insulating layer 600 is formed on the side of the second connection electrode layer 401 away from the substrate 100, and the third interlayer insulating layer 600 is etched by using a photolithography technique, so as to prevent the third interlayer insulating layer 600 from covering the groove 520 of the bending region, thereby avoiding affecting the bending effect of the bending region.
In process 12, a second planarization layer 540 is formed on a side of the third interlayer insulating layer 600 away from the substrate 100, and the second planarization layer 540 is etched by using a photolithography process to form a via 44 penetrating through the second planarization layer 540, so that a subsequent film layer is connected to the thin film transistor on the array substrate.
Therefore, in combination with the prior art of fig. 1, the technical solution provided in the embodiment of the present invention does not need to provide a protective layer between the first semiconductor layer 101 and the second semiconductor layer 201 by providing a double-layer gate insulating layer, which is beneficial to reducing one etching process, that is, reducing the number of masks, so that the second semiconductor layer 201 is located between the first gate insulating layer 200 and the second gate insulating layer 300, and the first semiconductor layer 101 and the second semiconductor layer 201 can share the second gate insulating layer 300, and the first thin film transistor formed by the first semiconductor layer 101 is in a double-layer gate insulating layer structure, and the second thin film transistor formed by the second semiconductor layer 201 is in a single-layer gate insulating layer structure, so that the distance between the first semiconductor layer 101 and the second semiconductor layer 201 can be greatly reduced, that is, the film thickness between the two thin film transistors can be reduced.
Fig. 20 is a schematic cross-sectional structure of another array substrate according to the embodiment of the present invention, referring to fig. 20, the subsequent process further includes forming the anode 920, the pixel defining layer 910, and the support columns 930 of the light emitting device on the side of the second planarization layer 540 away from the substrate 100, and the process for forming these structures can refer to the processes in the prior art and will not be repeated herein.
The embodiment of the invention also provides a display panel which comprises the array substrate provided by any embodiment of the invention, so that the display panel provided by the embodiment of the invention also has the beneficial effects described in any embodiment.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. An array substrate, characterized by comprising:
A substrate;
a protective layer located on one side of the substrate; the material of the protective layer is polyimide film;
The first grid insulation layer is positioned on one side of the protection layer away from the substrate; when the first gate insulating layer is formed, annealing the first gate insulating layer; the second gate insulating layer is positioned on one side of the first gate insulating layer away from the substrate and is in contact with the first gate insulating layer;
a first semiconductor layer and a gate layer, wherein the first semiconductor layer is positioned on one side of the first gate insulating layer close to the substrate, the first gate insulating layer covers the first semiconductor layer, and the gate layer is positioned on one side of the second gate insulating layer far from the substrate and is in contact with the second gate insulating layer; or alternatively
The first semiconductor layer is positioned on one side of the second gate insulating layer away from the substrate, the gate layer is positioned on one side of the first gate insulating layer close to the substrate, and the first gate insulating layer covers the gate layer;
A second semiconductor layer between the first gate insulating layer and the second gate insulating layer, and the second gate insulating layer entirely covers the second semiconductor layer; wherein the first semiconductor layer and the second semiconductor layer are different in material;
the material of the first semiconductor layer comprises polysilicon, and the material of the second semiconductor layer comprises metal oxide;
the thin film transistor formed by the first semiconductor layer comprising polysilicon is of a double-layer grid insulation layer structure; the thin film transistor formed by the second semiconductor layer comprising metal oxide is of a single-layer gate insulating layer structure.
2. The array substrate of claim 1, wherein the first semiconductor layer comprises a first active layer and the second semiconductor layer comprises a second active layer, and wherein there is no overlap between an orthographic projection of the first active layer on the substrate and an orthographic projection of the second active layer on the substrate.
3. The array substrate of claim 1, wherein when the first semiconductor layer is located on a side of the first gate insulating layer close to the substrate and the first gate insulating layer covers the first semiconductor layer, the gate layer is located on a side of the second gate insulating layer away from the substrate and is in contact with the second gate insulating layer;
the array substrate further includes:
A first interlayer insulating layer; the grid electrode layer is positioned on one side of the substrate far away from the substrate and covers the grid electrode layer;
The source-drain electrode layer is positioned on one side, far away from the substrate, of the first interlayer insulating layer, and comprises a first source-drain electrode layer and a second source-drain electrode layer which are arranged in the same layer;
The first source/drain electrode layer is in contact with the first semiconductor layer through a first via hole penetrating through the first interlayer insulating layer; the second source/drain electrode layer is in contact with the second semiconductor layer through a second via hole penetrating through the first interlayer insulating layer.
4. The array substrate of claim 3, wherein the gate layer comprises a first gate layer and a second gate layer, the first gate layer being co-layer with the second gate layer; the orthographic projection of the first grid layer on the substrate falls into the orthographic projection of the first semiconductor layer on the substrate, and the orthographic projection of the second grid layer on the substrate falls into the orthographic projection of the second semiconductor layer on the substrate.
5. The array substrate of claim 4, further comprising a capacitive electrode layer comprising a first electrode layer and a second electrode layer, the first electrode layer being common to the second gate layer, the second electrode layer being on a side of the first interlayer insulating layer remote from the substrate and being co-layer with the source drain layer.
6. The array substrate of claim 5, wherein the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the second electrode layer on the substrate.
7. The array substrate according to claim 4, further comprising a second interlayer insulating layer, a third interlayer insulating layer, a planarizing layer, and a plurality of connection electrode layers;
The second interlayer insulating layer is positioned on one side of the source-drain electrode layer, which is far away from the substrate, the connecting electrode layer is positioned on one side of the second interlayer insulating layer, which is far away from the substrate, a plurality of connecting electrode layers are arranged on the same layer, and each connecting electrode layer is respectively contacted with the first source-drain electrode layer and the second source-drain electrode layer through a third via hole penetrating through the second interlayer insulating layer;
The third interlayer insulating layer and the flattening layer are sequentially stacked on one side, away from the substrate, of the connecting electrode layer.
8. The manufacturing method of the array substrate is characterized by comprising the following steps of:
Providing a substrate, and forming a protective layer on the substrate, wherein the protective layer is made of polyimide film;
forming a first semiconductor layer on one side of the protective layer away from the substrate;
A first grid insulation layer and a second semiconductor layer are sequentially formed on one side, far away from the substrate, of the first semiconductor layer, and the first grid insulation layer covers the first semiconductor layer; when the first gate insulating layer is formed, annealing the first gate insulating layer;
Forming a second gate insulating layer on one side of the first gate insulating layer far away from the substrate, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer completely covers the second semiconductor layer;
and forming a gate layer on one side of the second gate insulating layer away from the substrate, wherein the gate layer is in contact with the second gate insulating layer.
9. The manufacturing method of the array substrate is characterized by comprising the following steps of:
Providing a substrate, and forming a protective layer on the substrate, wherein the protective layer is made of polyimide film;
forming a grid electrode layer on one side of the protective layer away from the substrate;
A first gate insulating layer and a second semiconductor layer are sequentially formed on one side, far away from the substrate, of the gate layer, and the first gate insulating layer covers the gate layer; when the first gate insulating layer is formed, annealing the first gate insulating layer;
forming a second gate insulating layer on one side of the first gate insulating layer far away from the substrate, wherein the second gate insulating layer is in contact with the first gate insulating layer, and the second gate insulating layer covers the second semiconductor layer;
Forming a first semiconductor layer on one side of the second gate insulating layer away from the substrate, the first semiconductor layer being in contact with the second gate insulating layer;
the material of the first semiconductor layer comprises polysilicon, and the material of the second semiconductor layer comprises metal oxide;
the thin film transistor formed by the first semiconductor layer comprising polysilicon is of a double-layer grid insulation layer structure; the thin film transistor formed by the second semiconductor layer comprising metal oxide is of a single-layer gate insulating layer structure.
10. A display panel comprising an array substrate according to any one of claims 1-7.
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| CN108288621B (en) * | 2018-03-09 | 2021-01-26 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display panel |
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