CN113192923A - Design method of packaging substrate, packaging substrate and chip - Google Patents
Design method of packaging substrate, packaging substrate and chip Download PDFInfo
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
The application provides a design method of a packaging substrate, the packaging substrate and a chip, wherein the packaging substrate comprises an build-up build layer and a core layer, and the core layer comprises a plurality of signal holes; the method comprises the following steps: a ground core hole vss core via is added on the diagonal of two signal holes in the core layer for providing a return path for the signals transferred by the two signal holes. By adopting the method, the signals transmitted by the two signal holes on the diagonal can return to the ground end through the ground core hole, thereby reducing the coupling of the signals between the two signal holes and further reducing the crosstalk.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a design method of a package substrate, and a chip.
Background
With the advent of new applications, the rapid development of artificial intelligence, computer vision and autopilot, and high performance computing, Data transmission rates have become higher and higher, Double Data Rate (DDR) for parallel buses has progressed to 16Gbps, and serial-to-parallel transceivers Serdes for serial buses have also landed on the stage of 112 Gbps.
As the data transmission rate is higher and higher, the rising edge of the signal is faster and faster, the quality problem of the signal is more and more obvious, and the problems of reflection, ringing, crosstalk, intersymbol interference, power supply noise, track collapse and the like can cause the phenomena that the error code occurs in the signal transmission, even the data cannot be received and the like. Most digital systems employ signal interfaces that are carried by a large number of signal lines through redistribution layers (RDLs), packages, connectors, and PCBs, where crosstalk can greatly affect the performance of the system. When the crosstalk is-20 dB, 10% of the noise is coupled to the signal line; when the crosstalk is-40 dB, 1% of the noise is coupled to the signal line; when the crosstalk is-60 dB, 1% of the noise is coupled to the signal line. For a 56G Serdes design, the specification requires that the total amount of crosstalk on the signal lines cannot exceed 3mV, and for a 1000mV input signal, the crosstalk coupled to the signal lines cannot exceed 3% o, i.e., -50dB, so crosstalk optimization is one of the key points of the package design.
Crosstalk is typically reduced in the prior art by increasing the spacing between signal lines, reducing line width, reducing dielectric thickness, increasing VSS shielding, changing bump maps (bump maps) for IP, or changing package pin layout maps (ball maps). However, the crosstalk method provided in the prior art is generally limited by the physical size, material, trace, and the like of the package design, for example, when the ball map is changed, the prior art adopts the fully-wrapped ball pattern to reduce the crosstalk, but the fully-wrapped ball pattern increases the package size of the substrate, which leads to an increase in cost.
Therefore, how to reduce crosstalk in package design without increasing cost is one of the considerable technical issues.
Disclosure of Invention
In view of the above, the present application provides a method for designing a package substrate, a package substrate and a chip, so as to reduce crosstalk in package design without increasing cost.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, a method for designing a package substrate is provided, where the package substrate includes a build-up build stack layer and a core layer, and the core layer includes a plurality of signal holes; the method comprises the following steps:
a ground core hole vss core via is added on the diagonal of two signal holes in the core layer for providing a return path for the signals transferred by the two signal holes.
According to a second aspect of the present application, there is provided a package substrate comprising:
build up build dup layer and core layer;
and the diagonals of the two signal holes in the core layer are provided with ground core holes vsscore via which are used for providing return paths for signals transmitted by the two signal holes.
According to a third aspect of the present application, a chip is provided, which is obtained by packaging with the method provided in the first aspect of the present application.
According to a fourth aspect of the present application, there is provided an electronic device comprising a processor and a machine-readable storage medium, the machine-readable storage medium storing a computer program executable by the processor, the processor being caused by the computer program to perform the method provided by the first aspect of the embodiments of the present application.
According to a fifth aspect of the present application, there is provided a machine-readable storage medium storing a computer program which, when invoked and executed by a processor, causes the processor to perform the method provided by the first aspect of the embodiments of the present application.
The beneficial effects of the embodiment of the application are as follows:
by drilling the ground core hole at the set position on the diagonal of the two signal holes, the signals transmitted by the two signal holes on the diagonal can return to the ground end through the ground core hole, thereby reducing the coupling of the signals between the two signal holes and further reducing the crosstalk. In addition, in the embodiment, the ground core hole vss core via is drilled on the diagonal line of the two signal holes, so that the package size and the cost are not increased.
Drawings
Fig. 1a is a schematic diagram of an electric field distribution of a signal line according to an embodiment of the present disclosure;
FIG. 1b is a schematic diagram of an electric field distribution of another signal line provided in the embodiment of the present application;
fig. 2 is a flowchart of a method for designing a package substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a package substrate according to an embodiment of the present disclosure;
FIG. 4a is a schematic diagram of a ball pattern layout of an LPDDR5 provided in the prior art;
FIG. 4b is a schematic diagram of a signal hole layout of a core layer corresponding to a ball pattern layout in the prior art;
fig. 4c is a schematic layout diagram of signal holes of a core layer corresponding to ball pattern arrangement provided in the embodiment of the present application;
FIG. 5a is a schematic diagram of a ball pattern layout of differential signal holes provided in the prior art;
FIG. 5b is a schematic layout diagram of signal vias of a core layer corresponding to a ball pattern arrangement of a conventional differential signal via;
fig. 5c is one of the schematic layout diagrams of signal holes of the core layer corresponding to the ball pattern arrangement of the differential signal holes provided in this embodiment;
fig. 6 is a second schematic layout diagram of signal holes of the core layer corresponding to the ball pattern arrangement of the differential signal holes provided in this embodiment;
fig. 7 is a schematic hardware structure diagram of an electronic device implementing a method for designing a package substrate according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects such as the present application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Before describing the package design method of the substrate provided by the present application, the technical terms related to the present application are described:
crosstalk: signals are propagated in the form of electromagnetic waves on a transmission line as a carrier, the electromagnetic waves being formed between two conductors of the transmission line. When adjacent transmission lines are close to each other, the edges of the electric field and the magnetic field generated by the signal will affect each other, and when external excitation is applied, the interaction between the fields will cause energy coupling between the transmission lines, which is referred to as crosstalk. Referring to the distribution of the electric field shown in fig. 1a and 1b, the transmission line pitch of fig. 1a is large and the noise of the victim line is small; the transmission line pitch of fig. 1b is small, the victim line is affected by the attack line, and the noise is large, which is why increasing the pitch reduces crosstalk. Signals are transmitted often find the shortest path to return to ground (vss), so vss is usually added between two signals to let the signals return to ground by the shortest path without coupling to adjacent signal lines. Based on this principle, the present application proposes to add vss via between the signal holes so that the coupling of the signal holes is reduced, thereby reducing crosstalk, as will be described in detail later.
The method for designing the package substrate provided by the present application is described in detail below.
Referring to fig. 2, fig. 2 is a flowchart of a method for designing a package substrate, which is provided by the present application, and is used for designing a package substrate, where the package substrate includes a build-up stack layer and a core layer, and referring to the substrate shown in fig. 3, the core layer includes a plurality of signal holes, and the method may include the following steps:
and S201, adding a ground core hole vss core via on the diagonal line of two signal holes in the core layer, for providing a return path for signals transferred by the two signal holes.
Specifically, in the package design, the substrate includes a build-up layer and a core layer, and the build-up layer and the core layer are different in punching manner when connecting to each signal line, and in the current package design, there are two via hole manners, one is a laser via (laser via), which is mainly used for punching the build-up build dup layer, please refer to the laser via hole illustrated in fig. 3; another type is a mechanical via (pthvia) which is used to punch holes in the transmission lines of the core layer, and may be referred to as a core via (core via), and referring to the core via shown in fig. 3, if the signal lines of each layer of the core layer are punched to connect the signal lines of each layer, the punched holes are referred to as signal vias.
Optionally, the core layer is located in the thickest layers of the package substrate, for example, the core layer is the thickest two layers of the substrate of a certain chip package.
It should be noted that the characteristic of the core layer punch is that the aperture is large, the distance in the vertical direction is long, and if there is no ground line near the signal holes when the signal passes through, there is mutual coupling between the signal holes, which results in crosstalk between the signal holes. In order to solve the problem, the present application proposes to add a ground core hole VSS core via on the diagonal of two signal holes in the core layer, refer to fig. 4a to 4c, fig. 4a lists an arrangement schematic diagram of a package pin arrangement fixed mode ball pattern of a conventional Low Power consumption Double Data Rate SDRAM (LPDDR 5), and a layout schematic diagram of a signal hole of a core layer corresponding to the pin thereof refers to fig. 4b, as seen from fig. 4a and 4b, there are 4 ground pins VSS as a return path near one signal pin SIG, for example, there are 4 VSS near the signal pin 3, in the prior art, if a full packet ground ball pattern is used to reduce crosstalk, SIG (SIG1, SIG2, SIG4, SIG5) at four corners in fig. 4a should be changed to VSS, and the same Data transmission bandwidth is guaranteed, the package size needs to be increased to drop so many signals, which results in a larger package size and a higher cost. To avoid this, the present application proposes to add a ground core hole vss core via on the diagonal of the two signal holes of the core layer, refer to the layout diagram of the ground core hole vss core via shown in fig. 4c, for example, the ground core hole vss core via is punched on the diagonal between the signal hole SIG1 and the signal hole SIG3, and the ground core hole vss core via is punched on the diagonal between the signal hole SIG2 and the signal hole SIG3, etc.; by drilling the ground core hole at the set position on the diagonal line of the two signal holes, the signals transmitted by the two signal holes on the diagonal line can return to the ground end through the ground core hole, so that the coupling of the signals between the two signal holes is effectively reduced, and the crosstalk is further reduced. In addition, in the embodiment, the ground core hole vss core via is drilled on the diagonal line of the two signal holes, so that the package size and the cost are not increased.
It should be noted that, when the ground core hole vss core via is added to the diagonal of the two signal holes, in general, the ground core hole vss core via may be added to the middle position of the diagonal, so that the distance between the two signal holes and the ground core hole may be ensured to be the same, and the signals transmitted by the two signal holes may reach the ground simultaneously. Alternatively, the ground core hole vss core via may be drilled at a position other than the middle position on the diagonal, so that the signals transmitted by the two signal holes may be directly returned to the ground. In practical applications, the position of the ground wire core via on the diagonal may be determined according to practical situations.
Alternatively, the signals transferred by the two signal holes can be parallel bus signals, such as DDR parallel bus signals.
Optionally, the core layer provided in this embodiment includes a plurality of pairs of differential signal holes, each pair of differential signal holes is formed by two signal holes; step S201 may be performed according to the following procedure: and a ground core hole vss core via is added on the diagonal line of two signal holes with similar positions in two adjacent pairs of differential signal holes, and is used for providing a return path for signals transmitted by the two signal holes with similar positions.
In practical applications, the signal holes in the core layer may also be used for transmitting serial bus signals, and accordingly, two signal holes for providing serial bus signals form a pair of differential signal holes, as shown in fig. 5a, fig. 5a illustrates a ball pattern layout diagram of the differential signal holes provided in the prior art, SIGi _ N and SIGi _ P in fig. 5a are a pair of differential signal holes, for example, signal hole SIG1_ N and signal hole SIG1_ P are a first pair of differential signal holes, signal hole SIG2_ N and signal hole SIG2_ P are a second pair of differential signal holes, signal hole SIG3_ N and signal hole SIG3_ P are a third pair of differential signal holes, fig. 5b illustrates a layout diagram of signal holes of the core layer corresponding to the ball pattern layout, only ground holes vss via are provided in the current signal holes, and only ground wires vss via are provided in the upper, lower, left and right sides of the signal holes to provide a return path, and crosstalk occurs when no ground wire exists between the signal holes, if the prior art full-packet arrangement needs to be made to reduce crosstalk, the number of vsss balls needs to be increased, and the package size needs to be increased, so that the same transmission bandwidth can be realized. However, the whole package ground ball pattern approach inevitably increases the package size, and the larger the chip package size is, which not only results in large chip factory size but also results in large cost increase, in order to solve the problem, the present embodiment proposes to punch a ground core hole vss core via on the diagonal line between two signal holes in adjacent two pairs of differential signal holes, as shown in fig. 5c, where the signal hole SIG1_ P in the first pair of differential signal holes and the signal hole SIG3_ N in the third pair of differential signal holes belong to two signal holes in adjacent positions, and then punch a ground core hole vss core via on the diagonal line between the signal hole SIG1_ P in the first pair of differential signal holes and the signal hole SIG3_ N in the third pair of differential signal holes; for example, the signal hole SIG2_ P in the second pair of differential signal holes and the signal hole SIG3_ N in the third pair of differential signal holes belong to two signal holes in close positions, and then a ground core hole vss core via is drilled on a diagonal line between the signal hole SIG2_ P in the second pair of differential signal holes and the signal hole SIG3_ N in the third pair of differential signal holes, and so on. It should be noted that, in practical applications, it is also possible to make a ground core hole vss core via on a diagonal line between two signal holes providing SIG _ P signals in each of the two pairs of differential signal holes; it is also possible to tie a ground core hole vss core via to the diagonal between the two signal holes providing the SIG _ N signals in both pairs of differential signal holes, as the case may be. By drilling the ground core hole vss core via on the diagonal line between two signal holes with similar positions in two pairs of differential signal holes, the signals transmitted by the two signal holes can directly return to the ground end through the ground core hole vss core via, thereby avoiding the occurrence of the condition that the two signal holes increase crosstalk due to the coupling of the transmitted signals. In addition, in the embodiment, the ground core hole vss core via is drilled on the diagonal line of the two signal holes, so that the package size and the cost are not increased.
When the ground core hole vss core via is added to the diagonal line of the two signal holes close to each other, in general, the ground core hole vss core via may be added to the middle position of the diagonal line, so that the distance between the two signal holes and the ground core hole may be ensured to be the same, and the signals transmitted by the two signal holes close to each other may be simultaneously transmitted to the ground. Alternatively, the ground core hole vss core via may be drilled at a position other than the middle position on the diagonal line, and the return path generated by the ground core hole vss core via may be added, or the signals transmitted by the two signal holes close to each other may be returned to the ground through the added ground core hole vss core via, so that the coupling may be reduced, and the crosstalk may be reduced. In practical applications, the position of the ground core via vsss core via on the diagonal may be determined according to practical situations, and the purpose is to reduce or avoid crosstalk generated when two signal vias at close positions transmit signals.
Further, the package design method of the substrate provided in this embodiment further includes:
ground vias vss via are added to the horizontal lines on either side of each pair of differential signal vias, and a ground core via vss core via is added to the diagonal of each signal via of the pair to the added ground vias vss via to provide a return path for the differential signals carried by the differential signal vias.
Specifically, in this embodiment, in addition to the ground core holes vss core via on the diagonal line between two adjacent signal holes in two adjacent pairs of differential signal holes, for each pair of differential signal holes, ground holes vss via may be drilled on the left and right horizontal lines of two signal holes in the pair of differential signal holes, as shown in fig. 6. Then, a ground core hole vss core via is drilled on the diagonal between the ground hole vss via and the signal hole, as also shown in fig. 6. For example, in fig. 6, in addition to the ground core hole vss via1 being perforated on a diagonal line between two adjacent signal holes (SIG1_ P and SIG3_ N) in two adjacent pairs of differential signal holes (the first pair of differential signal holes and the third pair of differential signal holes), a ground hole vss 1 and a ground hole vss via2 are added to the left and right horizontal lines of the signal hole SIG3_ N, a ground hole vss via3 and a ground hole vss via4 are added to the left and right horizontal lines of the signal hole SIG3_ P, a ground core hole vss via2 is added to the diagonal line between the ground hole vss via1 and the signal hole SIG3_ P, and similarly, a ground core hole vss via3 is added to the diagonal line between the ground hole vss via2 and the signal hole SIG3_ P, and so on. In this way, when the signal vias of the pair of differential signal vias transmit signals, the signals can be guided to the ground through the ground vias vss via or the ground core via, i.e., a return path is provided for the differential signals transmitted by the two signal vias of the pair of differential signal vias, thereby reducing crosstalk generated when the two signal vias transmit signals. Compared with the existing full-coverage layout mode, the method not only reduces crosstalk, but also saves cost.
It should be noted that the ground wire hole vss via is also a core hole in nature, and is only for distinguishing from the ground wire core hole vss core via.
Optionally, based on any of the above embodiments, the signals transmitted by the two signal holes in this embodiment may be, but are not limited to, high-speed signals, and the like.
Any layout shown in fig. 4a to 6 is only a partial example of the signal hole, and does not show the entire structure of the core layer. It should be noted that the size of the ground core hole vss core via and the ground hole vss via according to any embodiment of the present application is not limited, and may be specifically determined according to the thickness of the stacked layer.
Based on the same inventive concept, the present application further provides a package substrate, which is obtained by packaging based on the package design method provided in any one of fig. 2 to 6, and the package substrate includes an build-up build layer and a core layer, as shown in fig. 3; for reference, fig. 4c and the above description on fig. 4c are referred to, and details thereof are not repeated herein. Alternatively, the signals transmitted by the two signal holes in this embodiment may be parallel bus signals.
Optionally, the core layer includes a plurality of pairs of differential signal holes, each pair of differential signal holes is formed by two signal holes, and the package substrate provided in this embodiment further includes: two adjacent pairs of differential signal holes have ground core holes vss core via on the diagonal of the two signal holes in the same position, which are used to provide a return path for the signals transmitted by the two signal holes in the same position. It should be noted that, the package substrate provided in this embodiment may refer to the description related to fig. 5a to 5c, and is not described in detail here.
Furthermore, the package substrate provided in this embodiment further includes: each pair of differential signal vias has a ground via vss via in the horizontal line on both sides thereof, and each signal via of the pair of differential signal vias has a ground core via vss core via in the diagonal line to the ground via vss via, for providing a return path for the differential signal carried by the differential signal via. It should be noted that, the package substrate provided in this embodiment may refer to the description related to fig. 6, and is not described in detail here.
It should be noted that the signals transmitted by two signal holes in each pair of differential signal holes provided in this embodiment may be serial bus signals.
Alternatively, based on any of the above embodiments, the signals transmitted by the two signal holes in the present embodiment may be high-speed signals, and the like.
According to the package substrate provided by the embodiment, the ground core hole is drilled at the set position on the diagonal line of the two signal holes, so that the signals transmitted by the two signal holes on the diagonal line can be conducted to the ground end through the ground core hole, thereby reducing the coupling of the signals between the two signal holes and further reducing the crosstalk. In addition, in the embodiment, the ground core hole vss core via is drilled on the diagonal line of the two signal holes, so that the package size and the cost are not increased.
Based on the same inventive concept, the present embodiment further provides a chip, and a package substrate of the chip is designed by using the design method of the package substrate provided in any embodiment of the present application. By adopting the packaging substrate provided by any embodiment of the application in the chip, the crosstalk between signal holes in the chip can be reduced, and the packaging cost cannot be increased.
Based on the same inventive concept, the application also provides a substrate package design device corresponding to the substrate package design method. The implementation of the package design apparatus of the substrate may refer to the above description of the package design method of the substrate, which is not discussed herein.
The design apparatus for a package substrate provided in this embodiment is used for designing a package substrate, where the package substrate includes a build-up build layer and a core layer, and the core layer includes a plurality of signal holes; the above-mentioned device includes:
and the punching module is used for adding a ground core hole vsss core via on the diagonal line of the two signal holes in the core layer and providing a return path for the signals transmitted by the two signal holes.
Optionally, in this embodiment, the core layer includes a plurality of pairs of differential signal holes, and each pair of differential signal holes is formed by two signal holes; then
The punching module is specifically configured to add a ground core hole vss core via to a diagonal line of two signal holes in close positions in two adjacent pairs of differential signal holes, and is configured to provide a return path for signals transmitted by the two signal holes in close positions.
Optionally, the punching module is further configured to add ground line holes vss via on the horizontal lines on both sides of each pair of differential signal holes, and add ground core holes vss core via on the diagonal line of each signal hole of the pair of differential signal holes and the added ground line hole vss via, so that the differential signals transferred by the differential signal holes provide a return path.
Optionally, based on any one of the above embodiments, the signals transmitted by the two signal holes in this embodiment are parallel bus signals.
Optionally, based on any of the above embodiments, the signals transmitted by the two signal holes in this embodiment are high-speed signals.
Based on the same inventive concept, an electronic device according to an embodiment of the present application is provided, as shown in fig. 7, and includes a processor 701 and a machine-readable storage medium 702, where the machine-readable storage medium 702 stores a computer program capable of being executed by the processor 701, and the processor 701 is caused by the computer program to execute the package design method of the substrate according to any embodiment of the present application.
The computer-readable storage medium may include a RAM (Random Access Memory), a DDR SRAM (Double Data Rate Synchronous Dynamic Random Access Memory), and may also include a NVM (Non-volatile Memory), such as at least one disk Memory. Alternatively, the computer readable storage medium may be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
In addition, the present application provides a machine-readable storage medium, which stores a computer program, and when the computer program is called and executed by a processor, the computer program causes the processor to execute the package design method of the substrate provided in any embodiment of the present application.
For the embodiments of the electronic device and the machine-readable storage medium, since the contents of the related methods are substantially similar to those of the foregoing embodiments of the methods, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the embodiments of the methods.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and actions of each unit/module in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, wherein the units/modules described as separate parts may or may not be physically separate, and the parts displayed as units/modules may or may not be physical units/modules, may be located in one place, or may be distributed on a plurality of network units/modules. Some or all of the units/modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (10)
1. The method for designing the package of the substrate is characterized by being used for designing the package substrate, wherein the package substrate comprises a build-up build layer and a core layer, and the core layer comprises a plurality of signal holes; the method comprises the following steps:
a ground core hole vss core via is added on the diagonal of two signal holes in the core layer for providing a return path for the signals transferred by the two signal holes.
2. The method of claim 1, wherein the core layer comprises a plurality of pairs of differential signal holes, each pair of differential signal holes consisting of two signal holes; then adding a ground core hole vss core via on the diagonal of two signal holes in said core layer, comprising:
and a ground core hole vss core via is added on the diagonal line of two signal holes with similar positions in two adjacent pairs of differential signal holes, and is used for providing a return path for signals transmitted by the two signal holes with similar positions.
3. The method of claim 2, further comprising:
ground vias vss via are added to the horizontal lines on either side of each pair of differential signal vias, and a ground core via vss core via is added to the diagonal of each signal via of the pair to the added ground vias vss via to provide a return path for the differential signals carried by the differential signal vias.
4. The method of claim 1, wherein the signals transferred by the two signal holes are parallel bus signals.
5. The method of any one of claims 1 to 4, wherein the signals transmitted by the two signal holes are high speed signals.
6. A package substrate, comprising:
build up build dup layer and core layer;
and the diagonals of the two signal holes in the core layer are provided with ground core holes vsscore via which are used for providing return paths for signals transmitted by the two signal holes.
7. The package substrate according to claim 6, wherein the core layer comprises a plurality of pairs of differential signal holes, each pair of differential signal holes consisting of two signal holes, and further comprising:
two adjacent pairs of differential signal holes have ground core holes vss core via on the diagonal of the two signal holes in the same position, which are used to provide a return path for the signals transmitted by the two signal holes in the same position.
8. The package substrate of claim 6, further comprising:
each pair of differential signal vias has a ground via vss via in the horizontal line on both sides thereof, and each signal via of the pair of differential signal vias has a ground core via vss core via in the diagonal line to the ground via vss via, for providing a return path for the differential signal carried by the differential signal via.
9. The package substrate of claim 6, wherein the signals transferred by the two signal holes are parallel bus signals.
10. A chip, wherein a package substrate of the chip is designed by the method of any one of claims 1 to 5.
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| CN113192923B (en) | 2024-04-19 |
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