CN113130929B

CN113130929B - Method for reducing resistance of silicon-based bipolar plate, silicon-based bipolar plate and fuel cell

Info

Publication number: CN113130929B
Application number: CN202110312904.8A
Authority: CN
Inventors: 施正荣; 朱景兵; 王沛远; 吴王聪
Original assignee: Zhejiang Haihao New Energy Technology Co ltd
Current assignee: Zhejiang Haihao New Energy Technology Co ltd
Priority date: 2021-03-24
Filing date: 2021-03-24
Publication date: 2022-08-30
Anticipated expiration: 2041-03-24
Also published as: CN113130929A

Abstract

The invention discloses a method for reducing the resistance of a silicon-based bipolar plate, the silicon-based bipolar plate and a fuel cell, wherein the bipolar plate comprises a cathode plate and an anode plate which are in stacked contact, and each polar plate is made of doped silicon wafers; integrally manufacturing a high-doping layer at least on the stacking contact surface of the cathode plate and/or the anode plate, and reducing the contact resistance between the cathode plate and the anode plate in a single bipolar plate through the high-doping layer; the invention effectively reduces the overall body resistance of the bipolar plate on the basis of the technology without arranging a conductive metal composite layer, and meanwhile, the bipolar plate is not easy to corrode and has excellent durability inside the cooling flow channel of the bipolar plate with higher working temperature.

Description

Method for reducing resistance of silicon-based bipolar plate, silicon-based bipolar plate and fuel cell

Technical Field

The invention belongs to the technical field of fuel cells, and particularly relates to a method for reducing the resistance of a silicon-based bipolar plate, and the bipolar plate and the fuel cell prepared by the method.

Background

Two materials are typically used for the plates of a conventional stack: graphite and metal plates. The graphite pole plates have good conductivity, and meanwhile, the contact resistance between the cooling water channel surfaces of the bipolar plates and the contact resistance between the gas channel surfaces of the bipolar plates and the carbon fiber gas diffusion layers are small, so that the requirement of low resistance of a fuel cell stack can be easily met. The main defects of the graphite pole plate are that the mechanical strength is low, the thickness of the pole plate is thick, and the power density of the galvanic pile is influenced; the volume resistance of the metal polar plate is smaller than that of the graphite polar plate, people adopt a welding method to manufacture the bipolar plate, and the contact resistance of the metal polar plate on the water channel surface is small. Carbon film or noble metal is deposited on the surface of the gas channel of the metal pole plate, and forms better electric contact with the carbon fiber gas diffusion layer, but because of the natural characteristic that the metal pole plate is easy to corrode in the acidic environment of the fuel cell, the chemical stability of the metal pole plate protected by the carbon film or noble metal film is still the main factor influencing the service life of the galvanic pile.

Therefore, a highly doped and high-conductivity crystalline silicon material is selected as a plate material of the fuel cell stack (the technical scheme can be specifically referred to as CN110581288B, CN110581290A and CN110581291A), and the resistance requirement used in the fuel cell stack can be met due to the fact that the bulk resistance of the silicon plate is small. However, when the applicant deeply popularizes and applies the technology, the applicant finds that the contact resistance between the high-conductivity silicon materials is large, in order to realize the excellent substitution of the crystalline silicon plates for the metal plates and the graphite plates, the reduction of the contact resistance between the high-doped crystalline silicon plates on the water channel surface and the contact resistance between the silicon plates and the gas diffusion layer needs to be considered, and therefore the fuel cell stack with high power density and high durability is manufactured.

The applicant proposed a prior application CN111916783A, specifically proposed to use a silicon plate to make a fuel cell and to reduce the contact resistance between the silicon plate and a carbon fiber gas diffusion layer by depositing a transition layer and a carbon film on the silicon plate, and did not specifically refer to how to reduce the contact resistance inside the silicon-based bipolar plate as much as possible.

The contact resistance inside the silicon-based bipolar plate mainly relates to the electrical contact between the silicon base surface and the silicon base surface, and is substantially different from the problems of internal resistance, electrodeposition property and processability of the metal bipolar plate or the graphite bipolar plate adopted in the prior art, so that the conventional technical personnel cannot apply the resistance reduction scheme of the bipolar plate made of the conventional material to the silicon-based bipolar plate. According to the teaching of the prior art, the silicon substrate is mainly and maturely applied to the photovoltaic industry, and based on the power generation principle of photovoltaic, the silicon substrate for photovoltaic does not have the technical problem of stacking and contacting the silicon substrate.

It is generally considered to prepare a silicon-based bipolar plate by stacking and composite connection through a conductive material, and the conductive material is preferably a metal material, which easily causes a durability problem due to corrosion of cooling channels located inside the bipolar plate; the arrangement of the non-metal conductive material for the rechecking composite connection has higher process difficulty.

Therefore, based on the above current state of the art, based on the leading development experience of the present inventors in the photovoltaic industry for many years and based on the intensive research on the silicon-based bipolar plate by the present inventors in recent years, it is desirable to seek a technical solution to reduce the resistance of the silicon-based bipolar plate.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method for reducing the resistance of a silicon-based bipolar plate, a silicon-based bipolar plate and a fuel cell, which effectively reduce the overall bulk resistance of the bipolar plate without providing a conductive metal composite layer, and meanwhile, are not easily corroded inside a bipolar plate cooling flow channel having a high working temperature, and have excellent durability.

The technical scheme adopted by the invention is as follows:

a method for reducing the resistance of a silicon-based bipolar plate comprises a cathode plate and an anode plate which are in stacked contact, wherein each electrode plate is made of a doped silicon wafer; a highly doped layer is integrally formed on at least the stacking contact surfaces of the cathode and/or anode plates, and the contact resistance between the cathode and anode plates in a single bipolar plate is reduced by the highly doped layer.

Preferably, when the doped silicon wafer is an N-type doped silicon wafer, the doping raw material adopted by the high-doping layer comprises phosphorus or arsenic; when the doped silicon wafer is a P-type doped silicon wafer, the doping raw material adopted by the high-doping layer comprises aluminum or boron or gallium.

Preferably, the contact resistance between the cathode plate and the anode plate in a single bipolar plate is no more than 12m Ω cm ² 。

Preferably, the method comprises the following operation steps:

s10), selecting at least 2 doped silicon wafers with flow channels on the surfaces as silicon-based polar plates;

s20), integrally manufacturing a high-doped layer on one side or two sides of at least 1 silicon-based polar plate;

s30), directly stacking, pressing and contacting the two silicon-based pole plates, wherein the stacking contact surface of at least 1 silicon-based pole plate is provided with the high-doping layer;

s40), a low-resistance bipolar plate is obtained.

Preferably, in step S20), the highly doped layer includes a doped diffusion layer and/or a silicon doped layer, wherein the doped diffusion layer is formed by a high temperature diffusion process, and the silicon doped layer is formed by a deposition process.

Preferably, the high temperature diffusion process comprises: diffusing the surface of the doped silicon wafer for at least 0.01 hour at the temperature of not less than 800 ℃ by adopting a diffusion source; and after the diffusion is finished, carrying out post-treatment process on the doped silicon wafer, wherein the post-treatment process comprises acid washing and/or alkali washing, removing the high-resistance layer on the surface of the silicon wafer, and avoiding the generation of a conductive dead zone on the silicon wafer.

Preferably, the silicon doped layer is manufactured by a PECVD process, wherein the PECVD process includes: depositing an amorphous silicon doping layer or a microcrystalline silicon doping layer on the surface of the doped silicon wafer by a PECVD method at the temperature of less than 600 ℃, and then annealing the amorphous silicon doping layer or the microcrystalline silicon doping layer at the temperature of not less than 600 ℃, so that the crystallization rate of the silicon doping layer is improved, and the amorphous silicon doping layer or the microcrystalline silicon doping layer is used for reducing the bulk resistance of the silicon doping layer.

Preferably, the bipolar plate comprises a cathode plate and an anode plate which are in stacked contact, each of the plates is made of doped silicon wafers, and the bipolar plate is prepared by the method for reducing the resistance of the silicon-based bipolar plate.

Preferably, the surface of the bipolar plate is respectively provided with an oxidant flow channel and a reducing agent flow channel, the interior of the bipolar plate is provided with a cooling channel, and the peripheries of the cathode plate and the anode plate are hermetically installed and connected.

Preferably, the fuel cell comprises a first membrane electrode, a bipolar plate and a second membrane electrode, wherein the bipolar plate adopts the bipolar plate, and the surfaces of the bipolar plates are respectively deposited with an intermediate transition layer (comprising a carbon film) for reducing contact resistance, and the intermediate transition layer is electrically contacted with a gas diffusion layer of the membrane electrode.

This application provides an integrative preparation high doping layer on silicon-based negative plate and/or silicon-based anode plate's the contact surface that piles up, through high doping layer as silicon-based bipolar plate's the contact surface that piles up, can obviously reduce the inside contact resistance of silicon-based bipolar plate, and then in the technique that need not set up the conductive metal composite bed, effectively reduced the holistic bulk resistance of bipolar plate, inside the bipolar plate cooling flow channel that has higher operating temperature simultaneously, be difficult for receiving the corruption, the durability is excellent.

Drawings

FIG. 1 is a schematic structural view of a silicon-based bipolar plate of example 1 according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a silicon-based bipolar plate structure according to example 3 of the present application;

FIG. 3 is a schematic structural view of a silicon-based bipolar plate of example 4 according to an embodiment of the present application;

figure 4 is a schematic view of the structure of a silicon-based bipolar plate of example 5 in accordance with an embodiment of the present invention.

Figure 5 is a block diagram of the steps in the process of fabricating a silicon-based bipolar plate according to an embodiment of the present invention.

Detailed Description

The embodiment of the invention discloses a method for reducing the resistance of a silicon-based bipolar plate, wherein the bipolar plate comprises a cathode plate and an anode plate which are in stacked contact, and each polar plate is made of doped silicon wafers; preferably, in the application, a conventional commercially available monocrystalline or polycrystalline highly-doped silicon wafer can be specifically adopted as the doped silicon wafer; and the resistivity should not be higher than 0.1 omega cm, and the thickness of the silicon wafer is usually in the range of 0.2-5 mm.

In the embodiment, a high-doping layer is integrally manufactured on at least the stacking contact surface of the cathode plate and/or the anode plate, and the contact resistance between the cathode plate and the anode plate in a single bipolar plate is reduced through the high-doping layer; wherein, a high-doping layer is uniformly manufactured on the stacking contact surface of the cathode plate and the anode plate at the same time, which is a more preferable scheme of the application and has lower contact resistance; preferably, in this embodiment, the contact resistance between the cathode plate and the anode plate in a single bipolar plate is no greater than 12m Ω cm ² (ii) a More preferably, not more than 8m Ω cm ² (ii) a Even more preferably, not more than 5m Ω cm ² ；

Preferably, in this embodiment, when the doped silicon wafer is an N-type doped silicon wafer, the doping material used for the high-doping layer includes phosphorus or arsenic or other doping materials with similar effects; when the doped silicon wafer is a P-type doped silicon wafer, the doping raw material adopted by the high-doping layer comprises aluminum, boron, gallium or other doping raw materials with similar effects; the internal contact resistance of the surface of the silicon-based bipolar plate can be obviously reduced through doping, and after stacking contact is carried out, the contact resistance between the silicon-based polar plates can be obviously reduced; the N-type doped silicon wafer and the P-type doped silicon wafer can be specifically selected according to actual requirements, and similar low contact resistance effects can be obtained.

Preferably, in the present embodiment, the method for reducing the resistance of the silicon-based bipolar plate comprises the following operation steps:

s20), integrally manufacturing a high-doped layer on one side or two sides of at least 1 silicon-based polar plate; wherein, preferably, in step S20), the highly doped layer includes a doped diffusion layer, wherein the doped diffusion layer is prepared by a high temperature diffusion process, and the thickness of the doped diffusion layer ranges from 0.001 to 50 micrometers, preferably from 0.1 to 10 micrometers; further preferably, the high temperature diffusion process comprises: diffusing the surface of the doped silicon wafer for at least 0.01 hour (preferably 0.01-20 hours, more preferably 0.5-10 hours) by using a diffusion source at the temperature of not less than 800 ℃ (preferably 800-; the diffusion source in this embodiment may be in a gaseous state, a liquid state, or a solid state, wherein the solid state is used as a more preferable diffusion source; and after the diffusion is finished, carrying out post-treatment process on the doped silicon wafer, wherein the post-treatment process comprises acid washing and/or alkali washing, the high-resistance layer on the surface of the silicon wafer can be removed through the acid washing, the generation of a conductive dead zone on the silicon wafer can be avoided through the alkali washing, and the surface of the silicon wafer cannot be damaged too much.

In other embodiments, the highly doped layer may also include a silicon doped layer, and the silicon doped layer is manufactured by a PECVD process, and has the advantages of high deposition speed, mature process, low process cost, and the like; of course, other well-known deposition processes may also be used, and this embodiment is not particularly limited thereto; further preferably, the PECVD process comprises: depositing an amorphous silicon doping layer or a microcrystalline silicon doping layer on the surface of the doped silicon wafer by a PECVD method at the temperature of less than 600 ℃, and then annealing the amorphous silicon doping layer or the microcrystalline silicon doping layer at the temperature of not less than 600 ℃ (more preferably 800-1000 ℃), so as to improve the crystallization rate of the silicon doping layer and reduce the bulk resistance of the silicon doping layer.

S30), directly stacking, pressing and contacting the two silicon-based pole plates, wherein the stacking contact surface of at least 1 silicon-based pole plate is provided with a high-doping layer;

s40), a low-resistance bipolar plate is obtained.

The embodiment provides a bipolar plate, which comprises a cathode plate and an anode plate which are in stacked contact, wherein each electrode plate is made of doped silicon wafers, and the bipolar plate is prepared by the method for reducing the resistance of the silicon-based bipolar plate; preferably, the bipolar plate of the present embodiment is provided with an oxidant passage and a reductant passage on the surfaces thereof, respectively, and a cooling passage inside thereof, while the outer peripheries of the cathode plate and the anode plate are sealingly attached.

It should be noted that, in the embodiments of the present application, other technical solutions (for example, manufacturing methods of a reducing agent flow channel, an oxidizing agent flow channel, and a cooling flow channel in a bipolar plate) of a bipolar plate can be directly referred to in CN110581288A, CN110581290A, and CN110581291A, and other known flow channel manufacturing solutions can also be adopted, and the embodiments are not particularly limited thereto. The present embodiment is not described in detail for the sake of brevity.

The embodiment also provides a fuel cell, which comprises a first membrane electrode, a bipolar plate and a second membrane electrode, wherein the bipolar plate adopts the bipolar plate, and the surfaces of the bipolar plates are respectively deposited with an intermediate transition layer (comprising a carbon film) for reducing contact resistance, and the intermediate transition layer is electrically contacted with a gas diffusion layer (usually made of carbon fiber) of the membrane electrode.

The membrane electrode and the bipolar plate are both used as main structures of fuel cell stacks, wherein the membrane electrode is an electrochemical reaction site where a reducing agent (usually methanol, hydrogen or other fuels) performs an oxidation reaction and an oxidizing agent (usually oxygen or air) performs a reduction reaction; a conventional membrane electrode mainly includes a proton exchange membrane (also referred to as PEM) located in the middle and having a cathode and an anode integrally disposed on two sides thereof, and gas diffusion layers (also referred to as GDLs) located on the upper and lower surfaces of the proton exchange membrane, respectively, and in order to promote the electrochemical reaction, a catalyst (usually located at the interface between the proton exchange membrane and the gas diffusion layers) is also disposed between the cathode, the anode, and the proton exchange membrane; these are common knowledge in the art and the present embodiment is not specifically developed.

It should be noted that the intermediate transition layer involved in the embodiments of the present application can be directly referred to the description of the prior patent application CN111769293A of the present applicant, and can significantly reduce the contact resistance between the bipolar plate and the membrane electrode.

The embodiment provides that an organic whole preparation high doping layer on silicon-based negative plate and/or silicon-based positive plate's the contact surface that piles up, through high doping layer as silicon-based bipolar plate's the contact surface that piles up, can obviously reduce silicon-based bipolar plate's contact resistance, and then in the technique that need not set up the conductive metal composite bed, effectively reduced the holistic bulk resistance of bipolar plate, inside the bipolar plate cooling flow channel that has higher operating temperature simultaneously, be difficult for receiving the corruption, the durability is excellent.

It should be noted that, the thickness range limitation of various deposition layers in the present application can be tested by using a conductive film thickness meter, and various data related to the present embodiment are obtained by testing a Fisher model film thickness meter; the contact resistance value related to the application is detected by referring to a stacking test method in GB/T20042.6-2011, wherein the pressure in the stacking contact test is 1.5 MPa.

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.

Example 1: the technical solution of this embodiment 1 is different from the above embodiments in that, please refer to the silicon-based bipolar plate 10 shown in fig. 1, which includes a cathode plate 11 and an anode plate 12 in stacked contact, doped

diffusion layers

13a and 13b are integrally formed on both sides of the cathode plate 11 and the anode plate 12, and the

doped diffusion layers

13a and 13b are directly stacked, pressed and electrically contacted; as shown in fig. 5, the preparation process of the silicon-based bipolar plate 10 in the present embodiment includes the following steps:

s10)', selecting 2N-type arsenic-doped monocrystalline silicon wafers with double channels on the surfaces and resistivity of 2.5m omega cm as a silicon-based cathode plate 11 and a silicon-based anode plate 12 respectively, wherein an oxidant channel 11a and a cooling channel 11b are arranged on two sides of the silicon-based cathode plate 11 respectively, and a reductant channel 12a and a cooling channel 12b are arranged on two sides of the silicon-based anode plate 12 respectively;

s20)', respectively integrally forming doped

diffusion layers

13a, 13b on both sides of the silicon-based cathode plate 11 and the silicon-based anode plate 12, wherein the diffusion process of the

doped diffusion layers

13a, 13b in this step includes the following steps:

the doping raw material adopts phosphorus; the diffusion source is a mixed solution of phosphoric acid/silica sol/ethanol in a ratio of 20:16: 64; the diffusion conditions were set as: the temperature is 1200 ℃ and the time is 5 hours; after the diffusion is finished, soaking the silicon-based polar plate for 2 hours by adopting hydrofluoric acid to remove phosphorosilicate glass, and then soaking the silicon-based polar plate in 3mol/L KOH alkaline solution at 40 ℃ for 5 minutes;

it should be noted that, of course, it is also possible to integrally prepare a doped diffusion layer (see example 5 below) on one side of the silicon-based cathode plate 11 and the silicon-based anode plate 12, where the doped diffusion layer is located on the contact surface of the stack; in order to simplify the process and avoid the need to create masks to prevent diffusion, the applicant proposes to provide the

dopant diffusion layers

13a, 13b directly on both sides, and to provide the

dopant diffusion layers

13a, 13b on the surface of the bipolar plate 10 to further facilitate the electrical contact between the bipolar plate and the membrane electrode.

S30)', the two silicon-based

pole plates

11 and 12 are directly stacked, pressed and contacted, low-resistance contact is directly realized through the

doped diffusion layers

13a and 13b, and the cooling channel 11b and the cooling channel 12b are correspondingly matched to form a cooling channel 14;

s40)', a low-resistance bipolar plate 10 was obtained, and the contact resistance value between the silicon-based cathode plate 11 and the silicon-based anode plate 12 in the low-resistance bipolar plate 10 was 2.5m Ω cm by test ² 。

An intermediate transition layer (comprising a carbon deposition film and a metal deposition film, and electrically contacting with a gas diffusion layer of a corresponding membrane electrode through the carbon deposition film) is further arranged on the bipolar plate in the embodiment according to the technical scheme described in embodiment 2 in CN 111769293A; the contact resistance between the bipolar plate 10 and the membrane electrode was 2.2m Ω cm by testing ² 。

Example 2: the technical solution of this embodiment 2 is the same as that of embodiment 1, except that, referring to fig. 1 as well, in this embodiment 2, 2N-type phosphorus-doped monocrystalline silicon wafers with double flow channels on the surfaces are selected as a silicon-based cathode plate 11 and a silicon-based anode plate 12, respectively; through detection, the contact resistance value between the silicon-based cathode plate 11 and the silicon-based anode plate 12 in the obtained low-resistance bipolar plate 10 is 4.1m omega cm ² 。

Example 3: the technical solution of this embodiment 3 is different from that of embodiment 1 in that, referring to the silicon-based bipolar plate 20 shown in fig. 2, the silicon-based bipolar plate includes a silicon-based cathode plate 21 and a silicon-based anode plate 22 which are stacked and contacted, and doped diffusion layers 23a are integrally formed on both sides of the silicon-based cathode plate 21; the contact resistance value between the silicon-based cathode plate 21 and the silicon-based anode plate 22 in the obtained low-resistance bipolar plate 20 is 10.71m omega cm ² 。

Example 4: the technical solution of this embodiment 4 is different from that of embodiment 1 in that, referring to the silicon-based bipolar plate 30 shown in fig. 3, the silicon-based bipolar plate includes a silicon-based cathode plate 31 and a silicon-based anode plate 32 which are stacked and contacted, and a doped diffusion layer 33a is integrally formed on both sides of the silicon-based anode plate 32; the contact resistance between the silicon-based cathode plate 31 and the silicon-based anode plate 32 in the obtained low-resistance bipolar plate is 10.56m omega cm ² 。

Example 5: the technical solution of this embodiment 5 is similar to that of embodiment 1, except that the silicon-based bipolar plate 40 shown in fig. 4 comprises stacking connectionA silicon-based cathode plate 41 and a silicon-based anode plate 42, wherein high-doped

layers

43a and 43b are integrally deposited only on the stacking contact surfaces of the silicon-based cathode plate 41 and the silicon-based anode plate 42; the contact resistance value between the silicon-based cathode plate 41 and the silicon-based anode plate 42 in the obtained low-resistance bipolar plate is 2.5m omega cm through detection ² 。

Example 6: the technical solution of this embodiment 6 is the same as that of embodiment 1, except that, in step S20)' as shown in fig. 1, silicon doped layers 13a and 13b are integrally deposited on both sides of the silicon-based cathode plate 11 and the silicon-based anode plate 12, respectively, and the silicon doped layers 13a and 13b are formed by PECVD (plasma enhanced chemical vapor deposition) process; particularly preferably, the PECVD process comprises: at 590 ℃, an amorphous silicon phosphorus-doped composite layer is deposited on the upper surface of the N-type arsenic-doped monocrystalline silicon piece by a PECVD method, the energy consumption of PECVD equipment is low, the deposition speed is high, and lamplight rapid thermal annealing with visible light as a heat source can be specifically selected for annealing; then, annealing the amorphous silicon phosphorus-doped composite layer at 1000 ℃ for 20 minutes (the annealing mode can adopt lamplight rapid thermal annealing with visible light as a heat source, the annealing time is usually controlled within 30 minutes, and other annealing modes can be adopted, so that the crystallization rate of the silicon phosphorus-doped composite layer is improved, and the bulk resistance of the silicon phosphorus-doped composite layers 13a and 13b is reduced; through detection, the contact resistance value between the silicon-based cathode plate 11 and the silicon-based anode plate 12 in the obtained low-resistance bipolar plate is 2.2m omega cm ² 。

Comparative example 1: the technical scheme of the comparative example 1 is different from that of the example 1 in that the silicon-based cathode plate and the silicon-based anode plate in the comparative example 1 are not provided with high-doped layers; the detection proves that the contact resistance value between the silicon-based cathode plate and the silicon-based anode plate in the bipolar plate is up to 64.56m omega cm ² 。

The applicant finds that the high-doping layer is arranged on the stacking contact surface of the cathode plate or the anode plate in a single bipolar plate, and the silicon-based pole plates are electrically contacted by increasing the high-doping layer, so that the electric contact between the silicon-based cathode plate and the silicon-based anode plate can be obviously improved; certainly, the stacked contact surfaces of the cathode plate and the anode plate in a single bipolar plate are both provided with the high-doped layers, and the inside of the bipolar plate is electrically contacted through the 2 high-doped layers, so that the resistance of the silicon-based bipolar plate can be further remarkably reduced, and the silicon-based bipolar plate has very excellent electrical contact performance.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A method for reducing the resistance of a silicon-based bipolar plate comprises a cathode plate and an anode plate which are in stacked contact, wherein each electrode plate is made of a doped silicon wafer; wherein, at least on the stacking contact surface of the cathode plate and/or the anode plate, a high doping layer is integrally manufactured, and the contact resistance between the cathode plate and the anode plate in a single bipolar plate is reduced by the high doping layer; when the doped silicon wafer is an N-type doped silicon wafer, the doping raw material adopted by the high-doping layer comprises phosphorus or arsenic; when the doped silicon wafer is a P-type doped silicon wafer, the doping raw material adopted by the high-doping layer comprises aluminum, boron or gallium; the high-doping layer comprises a doping diffusion layer or/and a silicon doping layer, wherein the doping diffusion layer is prepared through a high-temperature diffusion process, and the silicon doping layer is prepared through a deposition process.

2. Root of herbaceous plantsThe method of reducing the electrical resistance of a silicon-based bipolar plate of claim 1, wherein the contact resistance between the cathode plate and the anode plate in a single bipolar plate is not greater than 12m Ω cm ² 。

3. The method for reducing the resistance of a silicon-based bipolar plate according to claim 1, comprising the following steps:

s10), selecting at least 2 doped silicon wafers with flow channels on the surface as the silicon-based polar plate;

s40), a low-resistance bipolar plate is obtained.

4. The method for reducing the resistance of a silicon-based bipolar plate according to claim 3, wherein the high temperature diffusion process comprises: diffusing the surface of the doped silicon wafer for at least 0.01 hour at the temperature of not less than 800 ℃ by adopting a diffusion source; and after the diffusion is finished, carrying out post-treatment process on the doped silicon wafer, wherein the post-treatment process comprises acid washing and/or alkali washing, removing the high-resistance layer on the surface of the silicon wafer, and avoiding the generation of a conductive dead zone on the silicon wafer.

5. The method for reducing the resistance of a silicon-based bipolar plate according to claim 1, wherein the silicon doped layer is formed by a PECVD process, wherein the PECVD process comprises: depositing an amorphous silicon doping layer or a microcrystalline silicon doping layer on the surface of the doped silicon wafer by a PECVD method at the temperature of less than 600 ℃, and then annealing the amorphous silicon doping layer or the microcrystalline silicon doping layer at the temperature of not less than 600 ℃, so that the crystallization rate of the silicon doping layer is improved, and the amorphous silicon doping layer or the microcrystalline silicon doping layer is used for reducing the bulk resistance of the silicon doping layer.

6. A bipolar plate comprising a cathode plate and an anode plate in stacked contact, each plate being made of doped silicon wafers, wherein the bipolar plate is manufactured by the method for reducing the resistance of a silicon-based bipolar plate according to any one of claims 1 to 5.

7. The bipolar plate of claim 6, wherein an oxidant flow channel and a reductant flow channel are respectively formed on the surface of the bipolar plate, and a cooling channel is formed inside the bipolar plate, and the peripheries of the cathode plate and the anode plate are hermetically mounted and connected.

8. A fuel cell comprising a first membrane electrode, a bipolar plate arranged in the middle and a second membrane electrode, wherein the bipolar plate is the bipolar plate of claim 6 or 7, and the surfaces of the bipolar plates are respectively deposited with an intermediate transition layer for reducing the contact resistance, and the intermediate transition layer is electrically contacted with a gas diffusion layer of the membrane electrode.