CN113113072B

CN113113072B - Method for loading trim value in chip test

Info

Publication number: CN113113072B
Application number: CN202110346107.1A
Authority: CN
Inventors: 傅俊亮
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2024-02-06
Anticipated expiration: 2041-03-31
Also published as: CN113113072A

Abstract

The invention discloses a method for loading a trim value in chip test, which is characterized in that a trim bit value is written into a storage unit of a memory, and one trim bit value is written into 2 or more storage units at the same time when the trim bit value is written. When reading, 2 or more memory cells which are written with the same triming bit value are selected at the same time, and SA is used for judging that the triming bit value stored in all 2 or more memory cells is 1 or 0, and the window for reading data is improved because more memory cells provide data for comparison. When the memory cell is written with the triming bit value, the inverse value of the triming bit value can be written simultaneously, namely, when the original triming bit value is 1, the inverse value of 0 is written simultaneously; the read-out mutual comparison verification can be performed when reading out the data.

Description

Method for loading trim value in chip test

Technical Field

The invention relates to the field of semiconductor integrated circuit testing, in particular to a chip testing method, and specifically relates to a method for loading a trim value in chip testing.

Background

In SONOS EEPROM or Flash chip testing, it is often necessary to scan the dac value of the analog until a suitable dac value is found, i.e., trimming (Trimming) test. The method is that the dac value scanning mode of each test chip is scanned from 0 to the end value. Chip IP evaluation often requires setting the value of the personalized trim at high temperature at normal temperature or low temperature, or setting the value of the personalized trim at normal temperature at high temperature or low temperature, so as to evaluate the influence of changing temperature on the product performance. However, since the individual IP is separated from flash, there is no register for storing the personalized trim value, and the number of individual die (die on the wafer) is manually set one by one for a long time, for the die on the wafer, it is necessary to debug the die one by one and manually set the obtained dac value, then perform trimming for the next die, and then manually set the obtained dac value until the last die.

SONOS EEPROM or Flash requires different analog quantities, such as VPOS (positive high voltage for erasing), VNEG (negative high voltage for erasing), ITIM (current for generating read timing), ISA (reference current when reading data), etc., for erasing and reading of NVM.

When a factory performs a wafer processing process, die on the same wafer are different, die on different batches of wafers are different in production process, and analog values among the die are different. If VPOS and VNEG voltages are different, the erasing and writing degrees of different die are increased; if the ITIM is different, the read timing of different die is different; if the ISA is different, the difference of different die increases. Too large a difference may also lead to a failure of the erasure and reading.

Therefore, the analog quantity of all die is adjustable, and the analog quantity of different die is basically equivalent. All die have the same erasing and reading conditions, and the memory can be more reliably represented.

One analog corresponds to 3-5 bits of trimming bits, and the analog can be selected from 8-32 gears. Each triming bit is determined after CP1 trim (CP, probe test) and then written to a special word line special word line (SWL 3) of the SONOS NVM. After CP screening, SWL3 inhibits erasure and only allows reading. One trim bit value is written into one SONOS cell, and SA is used to distinguish between "1" cell (cell has no current) and "0" cell (cell has current), as shown in fig. 1.

SONOS IP allows entry into various modes of operation only after the trim value is loaded. Its mode of operation will meet the specification performance parameters (SPEC) specified in the chip manual.

The trim value is loaded by reliably reading the positive and negative trim values written in NVM SWL3 without trim ITIM and ISA, and loading them into the registers of BIST (built-in self test technology).

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method for loading a trim value in chip test, which is used for writing a trim bit value into a storage unit of a memory:

when writing a trimmable bit value, one trimmable bit value is written into 2 or more memory cells at the same time.

The further improvement is that the same triming bit value is written into 2 or more memory units, and when the triming bit value is loaded and then read, all 2 or more memory units written with the same triming bit value are simultaneously selected, SA is used for judging that the triming bit value stored in all 2 or more selected memory units is 1 or 0, and the data reading window is improved because more memory units provide data for comparison.

A further improvement is that the 2 or more memory cells are 2 or consecutive memory cells located adjacent to one another on the same column in the memory cell array.

In a further improvement, the SA is a sense amplifier for reading data in the memory.

The further improvement is that when the memory cell is written with the triming bit value, the memory cell also comprises writing the inverse value of the triming bit value, namely writing the inverse value of 0 under the condition that the original triming bit value is 1; the read-out mutual comparison verification can be performed when reading out the data.

The further improvement is that the trimming bit value is written into the memory cell through a special word line SWL; namely, the triming bit value is stored in the SONOS storage tube through the selection tube.

In the further improvement, when the trimmable bit value in the memory cell is read, the trimmable bit value stored in the memory cell is read by adopting a time sequence lower than the normal reading and writing time sequence of the memory, namely a slower time sequence, and the original value and the inverse value of the original value are read at the same time so as to perform mutual verification.

A further improvement is that the time sequence lower than the normal reading and writing of the memory is adopted, after the memory chip is powered up, the BIST internal register is set to a default value, the default dac value of the ITIM is all set to the lowest value of 0, and the time sequence is the slowest.

According to the method for loading the trim value in the chip test, aiming at writing of the trim bit value in the memory chip test, writing of one trim bit value from a traditional single memory unit is changed into writing of not less than 2 memory units at the same time, expansion of a reading window is achieved, and meanwhile, the inverse value of the current trim bit value can be written at the same time for mutual comparison verification after reading, so that stability of data reading is improved.

Drawings

FIG. 1 is a schematic diagram of a conventional method of writing a trimming bit value into a SONOS memory cell.

FIG. 2 is a schematic diagram of the present invention for writing a trimming bit value to adjacent 2 SONOS memory cells simultaneously.

Detailed Description

The following description of the embodiments of the present invention will be given with reference to the accompanying drawings, in which the technical solutions of the present invention are clearly and completely described, but the present invention is not limited to the following embodiments. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. Advantages and features of the invention will become more apparent from the following description and from the claims. It is noted that the drawings are in a very simplified form and use non-precise ratios for convenience and clarity in assisting in illustrating embodiments of the invention. All other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout.

The invention discloses a method for loading a trim value in a chip test, which is used for writing a trim bit value into a storage unit of a memory. The embodiment relates to a SONOS memory cell as shown in fig. 2, in which 2 memory cells are cut out from a single memory cell array, each memory cell includes two transistors, a selection transistor and a SONOS memory tube, which are sequentially connected in series, a source and a drain of each transistor form a bit line SL, a gate of each transistor form a SWL line, and second and third memory cells are shown in the figure, and a second specific word line SWL2 and a third specific word line SWL3 are led out.

When the memory unit is written with a triming bit value, one triming bit value is written into 2 or more memory units at the same time. The 2 or more memory cells are 2 or a plurality of consecutive memory cells located adjacent to the same column in the memory cell array. This embodiment shows that 2 memory cells are written simultaneously, by writing the same triming bit value in 2 memory cells simultaneously, i.e. in two memory cells shown in fig. 2, the same triming bit value is written simultaneously in SWL2 and SWL3, respectively, such as both writing "1". Writing into the memory cell through the specific word lines SWL2 and SWL3, namely the triming bit value is stored in the SONOS memory tube through the selection tube. The fncast in fig. 2 is a select transistor, and the gate voltage of the select transistor is pulled high when reading data in the memory transistor. When the triming bit value is loaded for reading, all 2 memory cells which are written with the same triming bit value are selected at the same time, and the sense amplifier SA for reading data judges that the triming bit value stored in all 2 memory cells is 1 or 0, and the window for reading data is improved because more memory cells provide data for comparison.

Meanwhile, a writing value can be added, namely, when the writing of the trimming bit value is carried out in the storage unit, the inverse value of the trimming bit value can be written simultaneously, namely, if the original trimming bit value in the storage unit is 1, the inverse value of 0 is written simultaneously; this makes it possible to perform mutual comparison verification after reading out the data, and to verify whether the stored original value is correct by the inverse value.

When the triming bit value in the memory cell is read, the triming bit value stored in the memory cell is read at a timing lower than the normal reading and writing of the memory, namely at a slower timing, including the simultaneous reading of the original value and the inverse value thereof, so as to perform mutual verification. Generally, after the memory chip is powered up, the BIST internal register is set to a default value, and the read timing at this time is the slowest when the default dac value of the ITIM is all set to the lowest gear, i.e., all "0" state. The triming bit values written into 2 or more SONOS memory cells have larger current windows, and the positive and negative triming bit values in the memory cells are read at a relatively slower time sequence, and the positive and negative values are verified after reading.

The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for loading trim value in chip test, aiming at a plurality of memory units forming an array with the same structure of a memory, writes the trim bit value, is characterized in that: each memory cell includes two transistors: the SONOS storage tube comprises a grid, a first switch end and a second switch end, the second switch end of the selection tube is connected with the first switch end of the SONOS storage tube, the selection tube and the SONOS storage tube are connected in series, and the first switch end of the selection tube and the second switch end of the SONOS storage tube are respectively connected with adjacent storage units on the same column; the grid electrode of the selection tube leads out an SWL word line, and the grid electrode of the SONOS storage tube leads out an SWLS word line;

writing one triming bit value into 2 or more memory units at the same time when writing the triming bit value; when the same triming bit value is written into 2 or more storage units and is read after the triming bit value is loaded, 2 or more storage units which are written into the same triming bit value are selected at the same time, SA is used for judging that the triming bit value stored in all the selected 2 or more storage units is 1 or 0, and the data are provided for comparison by more storage units, so that the window for data reading is improved.

2. The method for loading a trim value in a chip test of claim 1, wherein: the 2 or more memory cells are 2 or a plurality of consecutive memory cells located adjacent to the same column in the memory cell array.

3. The method for loading a trim value in a chip test of claim 1, wherein: the SA is a sense amplifier for reading data in the memory.

4. The method for loading a trim value in a chip test of claim 1, wherein: when the memory cell is written with the triming bit value, the memory cell also comprises a reverse value of the written triming bit value, namely, when the original triming bit value is 1, the memory cell is simultaneously written with a reverse value of 0; the read-out mutual comparison verification can be performed when reading out the data.

5. The method for loading a trim value in a chip test of claim 1, wherein: the trimming bit value is written into the memory cell through a special word line SWL; namely, the triming bit value is stored in the SONOS storage tube through the selection tube.

6. The method for loading a trim value in a chip test of claim 4, wherein: when the triming bit value in the memory cell is read, the triming bit value stored in the memory cell is read at a timing lower than the normal reading and writing of the memory, namely at a slower timing, including the simultaneous reading of the original value and the inverse value thereof, so as to perform mutual verification.

7. The method for loading a trim value in a chip test of claim 6, wherein: the time sequence lower than the normal reading and writing of the memory is that after the memory chip is powered up, the BIST internal register is set to a default value, the default dac value of the ITIM is all set to the lowest value of 0, and the reading time sequence is the slowest.