CN113097241A - Display substrate and manufacturing method thereof - Google Patents
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- CN113097241A CN113097241A CN202110301833.1A CN202110301833A CN113097241A CN 113097241 A CN113097241 A CN 113097241A CN 202110301833 A CN202110301833 A CN 202110301833A CN 113097241 A CN113097241 A CN 113097241A
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- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
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- 239000004020 conductor Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 36
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- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000003990 capacitor Substances 0.000 claims description 20
- 239000010409 thin film Substances 0.000 claims description 20
- 239000012044 organic layer Substances 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 12
- 239000011810 insulating material Substances 0.000 claims description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a display substrate and a manufacturing method thereof, wherein the display substrate comprises a source electrode and a drain electrode which are positioned on the substrate, a first interlayer dielectric layer which covers the source electrode and the drain electrode, a first conductor layer which is positioned on the first interlayer dielectric layer, the source electrode and the drain electrode, a first grid electrode insulating layer which is positioned on the first conductor layer, and a first grid electrode layer which is positioned on the first grid electrode insulating layer. The first interlayer dielectric layer is provided with openings above the source electrode and the drain electrode respectively, so that the first conductor layer can be connected with the source electrode and the drain electrode through the openings. The first conductor layer is used as an active layer and is connected with the source electrode and the drain electrode to be used as a lead of the source drain electrode, so that the source drain electrode lead does not need to be additionally formed, and the structure is simple. In addition, compared with the holes of the buffer layer and the interlayer dielectric layer in the existing structure, the holes of the first interlayer dielectric layer are reduced in depth, so that the process difficulty can be reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate and a manufacturing method thereof.
Background
As an emerging Display technology, self-luminous displays such as Micro Light-Emitting diodes (Micro LEDs) and Organic Light-Emitting diodes (OLEDs) have advantages such as lower power consumption, higher color gamut, faster response rate, and the like compared to conventional Liquid Crystal Displays (LCDs), and are regarded as a Display technology with better development prospects. Therefore, more panel manufacturers participate in the development of Micro LED and OLED technologies. Under the influence of a transfer technology and current driving, the micro LED can only be manufactured in a small size at present, and a splicing technical scheme is needed if large-size display is realized. Meanwhile, the foldable display is more and more popular as a new display form for consumers. Splicing and folding are realized by adopting a flexible substrate bending technology.
In the existing top gate type Thin Film Transistor (TFT), an active layer is formed on a substrate, an interlayer dielectric layer and a buffer layer are formed on the active layer, then the interlayer dielectric layer and the buffer layer are punched to form a source drain connected with the active layer, and finally a wire connected with the source drain is formed, so that the opening size is deep, the process difficulty is high, and the structure is complex.
Disclosure of Invention
The invention provides a display substrate and a manufacturing method thereof, aiming at simplifying the structure, reducing the opening depth and reducing the process difficulty.
In one aspect, the present invention provides a display substrate, the display substrate includes a flat region and a folding region, the flat region includes a thin film transistor region, a capacitor region and a binding region, and the display substrate includes, in a longitudinal direction:
a substrate;
the metal layer is positioned on the substrate and comprises a source electrode and a drain electrode which are positioned in the thin film transistor area;
a first interlayer dielectric layer covering the source and the drain, the first interlayer dielectric layer having openings above the source and the drain, respectively;
the first conductor layer is positioned on the first interlayer dielectric layer, the source electrode and the drain electrode and is connected with the source electrode and the drain electrode through the opening;
a first gate insulating layer on the first conductor layer;
a first gate layer on the first gate insulating layer.
Further preferably, the metal layer further includes a first metal line located in the folding region, and the display substrate further includes, in the longitudinal direction: the second interlayer dielectric layer is positioned on the first metal wire, the second grid electrode insulating layer is positioned on the second interlayer dielectric layer, the second grid electrode layer is positioned on the second grid electrode insulating layer, and the organic layer covers the first metal wire, the second interlayer dielectric layer, the second grid electrode insulating layer and the second grid electrode layer.
Further preferably, the metal layer further includes a first metal line located in the folding region, and the display substrate further includes, in the longitudinal direction: the second interlayer dielectric layer is positioned on the first metal wire, and the organic layer covers the first metal wire and the second interlayer dielectric layer.
Further preferably, the display substrate further includes, in the longitudinal direction: the semiconductor device includes a first gate insulating layer on the first gate electrode, a first gate electrode layer on the first gate insulating layer, and an organic layer covering the first gate insulating layer and the first gate electrode layer.
Further preferably, the metal layer further includes a second metal line located in the bonding region, and the display substrate further includes, in the longitudinal direction: a second conductor layer on the second metal line, and an anode layer on the second conductor layer.
Further preferably, the metal layer further includes a light shielding layer located in the capacitor region, and the display substrate further includes, in the longitudinal direction: a third gate insulating layer on the light-shielding layer, and a third gate layer on the third gate insulating layer; the light shielding layer, the third gate insulating layer and the third gate layer form a capacitance structure.
In another aspect, the present invention provides a method for manufacturing a display substrate, the display substrate includes a flat region and a folded region, the flat region includes a thin film transistor region, a capacitor region and a bonding region, the method includes:
providing a substrate;
forming a patterned metal layer on the substrate, wherein the metal layer comprises a source electrode and a drain electrode which are positioned in the thin film transistor area;
forming a first interlayer dielectric layer covering the source electrode and the drain electrode, wherein the first interlayer dielectric layer is provided with openings above the source electrode and the drain electrode respectively;
forming a first active layer on the first interlayer dielectric layer, the source electrode and the drain electrode, wherein the first active layer is connected with the source electrode and the drain electrode through the opening;
forming a first gate insulating layer on the first active layer;
forming a first gate layer on the first gate insulating layer;
and conducting a conductor process on the first active layer to form a first conductor layer.
Further preferably, the metal layer further includes a first metal line located in the folding region; in the step of covering the first interlayer dielectric layer of the source electrode and the drain electrode, forming a second interlayer dielectric layer positioned on the first metal wire; in the step of forming the first gate insulating layer on the first active layer, forming a second gate insulating layer on the second interlayer dielectric layer; during the step of forming a first gate layer on the first gate insulating layer, further comprising forming a second gate layer on the second gate insulating layer; the manufacturing method further comprises forming an organic layer covering the first metal line, the second interlayer dielectric layer, the second gate insulating layer and the second gate layer.
Further preferably, the metal layer further includes a second metal line located in the bonding region; in the step of forming the first active layer on the first interlayer dielectric layer, the source electrode and the drain electrode, forming a second active layer on the second metal line; during the step of conducting a conductor process on the first active layer to form a first conductor layer, conducting a conductor process on the second active layer to form a second conductor layer; the method also includes forming an anode layer over the second conductor layer.
Further preferably, the step of forming a first gate insulating layer on the first active layer and the step of forming a first gate layer on the first gate insulating layer include:
evaporating a grid insulating material on the first active layer;
evaporating a grid electrode material on the grid electrode insulating material;
patterning the gate material by using a mask plate to form the first gate layer;
and carrying out a patterning process on the gate insulating material by utilizing a self-alignment process to form the first gate insulating layer.
The invention has the beneficial effects that: the display substrate comprises a source electrode and a drain electrode which are positioned on the substrate, a first interlayer dielectric layer covering the source electrode and the drain electrode, first conductor layers positioned on the first interlayer dielectric layer, the source electrode and the drain electrode, a first grid electrode insulating layer positioned on the first conductor layers, and a first grid electrode layer positioned on the first grid electrode insulating layer. The first interlayer dielectric layer is provided with openings above the source electrode and the drain electrode respectively, so that the first conductor layer is connected with the source electrode and the drain electrode through the openings. The first conductor layer is used as an active layer and is connected with the source electrode and the drain electrode to be used as a lead of the source drain electrode, so that the source drain electrode lead does not need to be additionally formed, and the structure is simple. In addition, compared with the holes of the buffer layer and the interlayer dielectric layer in the existing structure, the holes of the first interlayer dielectric layer are reduced in depth, so that the process difficulty can be reduced.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display substrate according to a first embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a display substrate according to a second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a display substrate according to a third embodiment of the present invention;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a display substrate according to a fourth embodiment of the invention;
FIGS. 5a to 5e are schematic structural diagrams illustrating a display substrate according to a fourth embodiment of the present invention during a manufacturing process thereof;
fig. 6a to 6c are schematic structural diagrams of the display substrate in the process of forming the gate insulating layer and the gate layer according to the fifth embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature. As used herein, "longitudinal" refers to a direction perpendicular to the substrate.
The embodiment of the invention provides a display substrate.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display substrate according to a first embodiment of the disclosure. The display substrate 10 may be applied to any display device. The display substrate 10 includes a flat region 11 and a folding region 12, wherein the flat region 11 includes a thin film transistor region 111, a capacitor region 112 and a bonding region 113. In this embodiment, the tft region 111 is adjacent to the folding region 12, the capacitor region 112 is adjacent to the tft region 111, and the bonding region 113 is adjacent to the capacitor region 112.
The display substrate 10 includes a substrate 101, a metal layer 102 disposed on the substrate 101, wherein the metal layer 102 includes a source 1021 and a drain 1022 located in the thin film transistor region 111, a first interlayer dielectric layer 103a covering the source 1021 and the drain 1022, a first conductor layer 104a disposed on the first interlayer dielectric layer 103a, the source 1021, and the drain 1022, a first gate insulating layer 105a disposed on the first conductor layer 104a, and a first gate layer 106a disposed on the first gate insulating layer 105 a. In this embodiment, the first interlayer dielectric layer 103a has an opening 1031 above the source 1021 and the drain 1022 respectively, and the first conductive layer 104a is connected to the source 1021 and the drain 1022 through the opening 1031. The source 1021, the drain 1022, the first interlayer dielectric layer 103a, the first conductor layer 104a, the first gate insulating layer 105a, and the first gate layer 106a constitute a thin film transistor in the thin film transistor region 111. The source 1021 may also serve as a light-shielding layer of the thin film transistor.
In this embodiment, the substrate 101 includes a glass substrate 1011 and a flexible substrate 1012 on the glass substrate 1011, and the display substrate 10 may further include a passivation layer 107 covering the thin film transistor.
In this embodiment, the first conductive layer 104a may implement the function of the source layer, and is connected to the source 1021 and the drain 1022 to serve as a source/drain conductive line, so that no additional source/drain conductive line is required, and the structure is simplified. In addition, compared with the openings of the buffer layer and the interlayer dielectric layer in the existing structure, the opening 1031 of the first interlayer dielectric layer 103a has a reduced depth, so that the process difficulty can be reduced.
As shown in fig. 1, the metal layer 102 may further include a first metal line 1023 located in the folding region 12, and the first metal line 1023 may be a data line. The display substrate 10 further includes a second interlayer dielectric layer 103b on the first metal line 1023, a second gate insulating layer 105b on the second interlayer dielectric layer 103b, a second gate layer 106b on the second gate insulating layer 105b, and an organic layer 108 covering the first metal line 1023, the second interlayer dielectric layer 103b, the second gate insulating layer 105b, and the second gate layer 106b in the longitudinal direction. The second gate layer 106b may serve as a scan line.
In this embodiment, the organic layer 108 covering the data lines and the scan lines is formed in the folding region 12, and the position of the neutral layer can be adjusted to move the neutral layer from the original position of the substrate 101 to the positions of the routing lines such as the data lines and the scan lines, so that the routing lines are closer to the neutral layer, the stress applied to the routing lines can be reduced, and the risk of breaking the routing lines in the folding region 12 is reduced.
In this embodiment, the metal layer 102 may further include a second metal line 1024 located at the bonding region 113. The display substrate 10 further includes in a longitudinal direction: a second conductor layer 104b on the second metal line 1024, and an anode layer 109 on the second conductor layer 104 b. The display substrate 10 may further comprise a protective layer 110 covering the anode layer 109. The second metal line 1024, the second conductor layer 104b, the anode layer 109, and the protection layer 110 form an LED chip located in the bonding region 113.
In this embodiment, the metal layer 102 may further include a light-shielding layer 1025 located in the capacitor region 112, and the display substrate 10 further includes a third gate insulating layer 105c located on the light-shielding layer 1025 and a third gate layer 106c located on the third gate insulating layer 105 c. The third gate layer 106c, the third gate insulating layer 105c and the light-shielding layer 1025 form a large capacitor structure, and compared with the storage capacitor (composed of a scan line, an interlayer dielectric layer and a data line) in the prior art, the capacitor occupation ratio is reduced by removing the interlayer dielectric layer, which is beneficial to the structural design with high pixel density. Wherein, the passivation layer 107 may also cover the capacitor structure.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a display substrate according to a second embodiment of the disclosure. For ease of understanding, in the second embodiment, the same reference numerals are used for the same structures in the display substrate 20 as those of the display substrate 10 described above. The difference between the display substrate 20 and the display substrate 10 in the first embodiment is the structure of the traces in the folding region 12, and therefore the structures of the tft, the capacitor and the LED chip in the flat region 11 are not described in detail in this embodiment.
In this embodiment, the structure of the traces in the folding area 12 includes a first metal trace 1023 and a second interlayer dielectric layer 103b located on the first trace 1023, that is, the traces in the folding area 12 may only include data lines, and do not include scan lines, that is, a single-layer metal trace is adopted. Therefore, the structure of the display substrate 20 of the second embodiment can reduce the traces in the folding area 12, and reduce the risk of trace breakage.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a display substrate according to a third embodiment of the disclosure. For ease of understanding, in the third embodiment, the same reference numerals are used for the same structures in the display substrate 30 as those of the display substrate 10 described above. The difference between the display substrate 30 and the display substrate 10 in the first embodiment is also the structure of the traces in the folding region 12, and therefore the structures of the thin film transistor, the capacitor structure and the LED chip in the flat region 11 are not described in detail in this embodiment.
In the third embodiment, the folding area 12 is also a single layer of metal traces as in the second embodiment. Specifically, the structure routed by the folding region 12 includes a gate insulating layer 105b and a gate electrode layer 106b located on the gate insulating layer 105b, so that the folding region 12 only includes the scan lines.
Different from the prior art, in the display substrate provided in the embodiment of the present invention, the first conductive layer 104a in the thin film transistor in the flat region 11 serves as an active layer, and is also connected to the source/drain electrode to serve as the conductive lines of the source 1021 and the drain 1022. Compared with the existing structure trepanning (interlayer dielectric layer and buffer layer opening) design, the depth of the opening 1031 can be reduced, and the process difficulty is reduced. In addition, the organic layer 108 in the folding area 12 can adjust the position of the neutral layer to make the trace closer to the neutral layer, so as to reduce the stress on the trace, thereby reducing the risk of breaking the trace in the folding area 12. The folding region 12 may adopt a dual-layer metal trace composed of the first metal trace 1023 and the second gate layer 106b, or adopt a single-layer metal trace of the first metal trace 1023 or the second gate layer 106 b.
The embodiment of the present invention further provides a manufacturing method for manufacturing the display substrate 10, so that the structural reference numerals of the display substrate 10 are continuously used.
Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a manufacturing method of a display substrate according to a fourth embodiment of the invention. Referring to fig. 5a to 5e, fig. 5a to 5e are schematic structural diagrams of a display substrate according to a fourth embodiment of the invention in a manufacturing process.
Please first refer to steps S1-S2 and fig. 5a in fig. 4.
Step S1: a substrate 101 is provided.
Step S2: a patterned metal layer 102 is formed on the substrate 101, and the metal layer 102 includes a source 1021 and a drain 1022 located in the tft region 111, a first metal line 1023 located in the folding region 12, a second metal line 1024 located in the bonding region 113, and a light shielding layer 1025 located in the capacitor region 112.
In this embodiment, the substrate 101 includes two layers, a glass substrate 1011 and a flexible substrate 1012 on the glass substrate 1011, and the material of the flexible substrate 1012 may be Polyimide (PI). Firstly, a metal material coating film is coated on the flexible substrate 1012, wherein the metal material can be Mo, Al/Mo, Mo/Cu/IZO, IZO/Cu/IZO, Mo/Cu/ITO, Ni/Cu/Ni, MoTiNi/Cu/MoTiNi, NiCr/Cu/NiCr or CuNb, and the like, then the metal material coating film is patterned by using a mask plate to obtain a source 1021 and a drain 1022 located in the thin film transistor area 111, and simultaneously obtain a first metal wire 1023 located in the folding area 12, a second metal wire 1024 located in the binding area 113 and a shading layer 1025 located in the capacitor area 112, so that the source 1021, the drain 1022, the first metal wire 1023, the second metal wire 1024 and the shading layer 1025 are made of the same mask plate.
Please refer to step S3 and fig. 5b in fig. 4.
Step S3: forming a first interlayer dielectric layer 103a covering the source 1021 and the drain 1022, and simultaneously forming a second interlayer dielectric layer 103b on the first metal line 1023, wherein the first interlayer dielectric layer 103a has an opening 1031 above the source 1021 and the drain 1022 respectively.
In this embodiment, an interlayer dielectric layer covering the metal layer 102 may be formed first, and the interlayer dielectric layer may be SiOx or SiNx/SiOx or SiNOx, and then patterned to obtain a first interlayer dielectric layer 103a (having openings 1031 above the source 1021 and the drain 1022, respectively) covering the source 1021 and the drain 1022, and a second interlayer dielectric layer 103b on the first metal line 1023. The opening 1031 is also formed by a patterning process, that is, the opening 1031 is formed on the source electrode 1021 and the drain electrode 1022 by using a mask plate, so that a subsequently formed conductor layer can be in contact with the source electrode 1021 and the drain electrode 1022.
Please refer to step S4 and fig. 5c in fig. 4.
Step S4: a first active layer 104a ' on the first interlayer dielectric layer 103a, the source electrode 1021, and the drain electrode 1022 is formed, and a second active layer 104b ' on the second metal line 1024 is formed, the first active layer 104a ' being connected to the source electrode 1021 and the drain electrode 1022 through the opening 1031.
In the present embodiment, the active layer is a semiconductor material, which may be an oxide semiconductor or other type of semiconductor, such as IGZO, IGTO, IGZO, IGO, IZO, AIZO, or the like. Specifically, a layer of semiconductor material may be plated, and then a patterning process is performed to form a first active layer 104a 'on the first interlayer dielectric layer 103a, the source electrode 1021, and the drain electrode 1022, and a second active layer 104 b' on the second metal line 1024.
Please refer to steps S5-S6 and fig. 5d in fig. 4.
Step S5: a first gate insulating layer 105a on the first active layer 104 a' is formed, and simultaneously a second gate insulating layer 105b on the second interlayer dielectric layer 103b and a third gate insulating layer 105c on the light-shielding layer 1025 are formed.
Step S6: a first gate layer 106a over the first gate insulating layer 105a is formed, and a second gate layer 106b over the second gate insulating layer 105b and a third gate layer 106c over the third gate insulating layer 105c are formed at the same time.
Specifically, referring to fig. 6a to 6c, fig. 6a to 6c are schematic structural diagrams of a display substrate in the process of forming a gate insulating layer and a gate layer according to a fifth embodiment of the present invention, and steps S5 and S6 may specifically include: 1) a gate insulating material 105 is vapor-deposited on the first active layer 104 a', and the structure after vapor deposition is as shown in fig. 6 a; 2) a gate material 106 is evaporated on the gate insulating material 105, and the structure after evaporation is shown in fig. 6 b; 3) performing a patterning process on the gate material 106 by using a mask to form the first gate layer 106a, the second gate layer 106b, and the third gate layer 106c, where the patterned structure is shown in fig. 6 c; 4) the gate insulating material 105 is patterned by a self-aligned process to form the first gate insulating layer 105a, the second gate insulating layer 105b and the third gate insulating layer 105c, and the resulting structure is shown in fig. 5 d.
The gate insulating material 105 may be SiOx, SiNx, Al2O3/SiNx/SiOx, SiOx/SiNx/SiOx, etc., and the gate material 106 may be Mo, Mo/Al, Mo/Cu/IZO, IZO/Cu/IZO, Mo/Cu/ITO, Ni/Cu/Ni, MoTiNi/Cu/MoTiNi, NiCr/Cu/NiCr, CuNb, etc.
Please refer to steps S7-S8 and fig. 5e in fig. 4.
Step S7: the first and second active layers 104a 'and 104 b' are subjected to a conductor process to form first and second conductor layers 104a and 104 b.
Step S8: a passivation layer 107 covering the thin film transistor region 111 and the capacitor region 112 is formed.
In the present embodiment, the purpose of the conductive process is to conduct the active layer so as to be able to serve as a conductive line for the source 1021 and the drain 1022, and to connect the source 1021 and the drain 1022. The passivation layer 107 may be made of SiOx, SiNx, SiNOx, or the like, and the passivation layer 107 is formed by evaporating a passivation material and then performing a patterning process to form the passivation layer 107 covering only the thin film transistor region 111 and the capacitor region 112.
Please refer to step S9 in fig. 4 and fig. 1.
Step S9: an organic layer 108 is formed covering the first metal line 1023, the second interlayer dielectric layer 103b, the second gate insulating layer 105b, and the second gate layer 106 b.
In this embodiment, the organic layer 108 can adjust the position of the neutral layer, so that the trace of the folding region 12 is close to the neutral layer, and since the tensile stress of the position of the neutral layer is close to the compressive stress, the organic layer 108 can reduce the stress of the trace of the folding region 12, and reduce the risk of the trace breaking in the folding region 12. The formation of the organic layer 108 also includes plating and patterning processes.
In this embodiment, as shown in fig. 1, the manufacturing method further includes: forming an anode layer 109 on the second conductor layer 104 b; a protective layer 110 is formed at the bonding region 113 to cover the anode layer 109 to protect the structure of the bonding region 113. The anode layer 109 is formed by depositing a layer of anode material, which may be Mo, Mo/Al, Mo/Cu/IZO, IZO/Cu/IZO, Mo/Cu/ITO, Ni/Cu/Ni, MoTiNi/Cu/MoTiNi, NiCr/Cu/NiCr, or CuNb, and then patterning the anode material.
Different from the prior art, in the manufacturing method of the display substrate provided by this embodiment, the formation of the metal layer 102 in step S2, the formation of the first interlayer dielectric layer 103a and the second interlayer dielectric layer 103b in step S3, the formation of the first active layer 104a 'and the second active layer 104 b' in step S4, the formation of the gate layer in step S6, the formation of the passivation layer 107 in step S8, the formation of the organic layer 108 in step S9, and the formation of the anode layer 109 respectively require one mask to perform the patterning process, so that the manufacturing method of the display substrate 10 uses 7 masks in total, and has a simple structure and a low cost. In addition, in the manufacturing method of the display substrate 10, the first active layer 104 a' is made conductive, so that the formed first conductive layer 104 can be used as a source/drain wire and connected with the source electrode 1021 and the drain electrode 1022. In addition, in the manufacturing method, the first interlayer dielectric layer 103a is punched by using a patterning process, so that compared with the prior art, the hole opening depth can be reduced, and the process difficulty is reduced.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A display substrate, comprising a flat area and a folding area, wherein the flat area comprises a thin film transistor area, a capacitor area and a binding area, and the display substrate comprises in a longitudinal direction:
a substrate;
the metal layer is positioned on the substrate and comprises a source electrode and a drain electrode which are positioned in the thin film transistor area;
a first interlayer dielectric layer covering the source and the drain, the first interlayer dielectric layer having openings above the source and the drain, respectively;
the first conductor layer is positioned on the first interlayer dielectric layer, the source electrode and the drain electrode and is connected with the source electrode and the drain electrode through the opening;
a first gate insulating layer on the first conductor layer;
a first gate layer on the first gate insulating layer.
2. The display substrate of claim 1, wherein the metal layer further comprises a first metal line in the folding region, and wherein the display substrate further comprises in the longitudinal direction: the second interlayer dielectric layer is positioned on the first metal wire, the second grid electrode insulating layer is positioned on the second interlayer dielectric layer, the second grid electrode layer is positioned on the second grid electrode insulating layer, and the organic layer covers the first metal wire, the second interlayer dielectric layer, the second grid electrode insulating layer and the second grid electrode layer.
3. The display substrate of claim 1, wherein the metal layer further comprises a first metal line in the folding region, and wherein the display substrate further comprises in the longitudinal direction: the second interlayer dielectric layer is positioned on the first metal wire, and the organic layer covers the first metal wire and the second interlayer dielectric layer.
4. The display substrate of claim 1, further comprising, in the machine direction: the semiconductor device includes a first gate insulating layer on the first gate electrode, a first gate electrode layer on the first gate insulating layer, and an organic layer covering the first gate insulating layer and the first gate electrode layer.
5. The display substrate of claim 1, wherein the metal layer further comprises a second metal line located in the bonding region, and the display substrate further comprises, in the vertical direction: a second conductor layer on the second metal line, and an anode layer on the second conductor layer.
6. The display substrate according to claim 1, wherein the metal layer further comprises a light shielding layer located in the capacitor region, and the display substrate further comprises in the vertical direction: a third gate insulating layer on the light-shielding layer, and a third gate layer on the third gate insulating layer; the light shielding layer, the third gate insulating layer and the third gate layer form a capacitance structure.
7. A manufacturing method of a display substrate is characterized in that the display substrate comprises a flat area and a folding area, the flat area comprises a thin film transistor area, a capacitor area and a binding area, and the manufacturing method comprises the following steps:
providing a substrate;
forming a patterned metal layer on the substrate, wherein the metal layer comprises a source electrode and a drain electrode which are positioned in the thin film transistor area;
forming a first interlayer dielectric layer covering the source electrode and the drain electrode, wherein the first interlayer dielectric layer is provided with openings above the source electrode and the drain electrode respectively;
forming a first active layer on the first interlayer dielectric layer, the source electrode and the drain electrode, wherein the first active layer is connected with the source electrode and the drain electrode through the opening;
forming a first gate insulating layer on the first active layer;
forming a first gate layer on the first gate insulating layer;
and conducting a conductor process on the first active layer to form a first conductor layer.
8. The method of claim 7, wherein the metal layer further comprises a first metal line in the folding region; in the step of covering the first interlayer dielectric layer of the source electrode and the drain electrode, forming a second interlayer dielectric layer positioned on the first metal wire; in the step of forming the first gate insulating layer on the first active layer, forming a second gate insulating layer on the second interlayer dielectric layer; during the step of forming a first gate layer on the first gate insulating layer, further comprising forming a second gate layer on the second gate insulating layer; the manufacturing method further comprises forming an organic layer covering the first metal line, the second interlayer dielectric layer, the second gate insulating layer and the second gate layer.
9. The method of manufacturing a display substrate according to claim 7, wherein the metal layer further comprises a second metal line located in the bonding region; in the step of forming the first active layer on the first interlayer dielectric layer, the source electrode and the drain electrode, forming a second active layer on the second metal line; during the step of conducting a conductor process on the first active layer to form a first conductor layer, conducting a conductor process on the second active layer to form a second conductor layer; the method also includes forming an anode layer over the second conductor layer.
10. The method according to claim 7, wherein the step of forming a first gate insulating layer over the first active layer and the step of forming a first gate layer over the first gate insulating layer comprise:
evaporating a grid insulating material on the first active layer;
evaporating a grid electrode material on the grid electrode insulating material;
patterning the gate material by using a mask plate to form the first gate layer;
and carrying out a patterning process on the gate insulating material by utilizing a self-alignment process to form the first gate insulating layer.
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| US20210066422A1 (en) * | 2019-09-03 | 2021-03-04 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and display panel |
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| CN109560109A (en) * | 2017-09-26 | 2019-04-02 | 三星显示有限公司 | Display device |
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