CN113076028A

CN113076028A - Display panel and electronic device

Info

Publication number: CN113076028A
Application number: CN202110346965.6A
Authority: CN
Inventors: 冷传利
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-07-06

Abstract

The application discloses display panel and electronic equipment, among the display panel, test circuit has signal transmission line, the touch-control signal line is connected to signal transmission line electricity, signal transmission line still walks the line electricity with the data line through being connected and is connected. Therefore, in the test stage, the test signal can be input into the data line through the signal line transmission line, the panel test is realized through the signal transmission line, in the non-test stage, the connection wiring and the test circuit are in an open circuit, the signal transmission line outputs the touch signal detected by the touch electrode, and the touch detection is realized through the signal transmission line, so that the signal transmission line in the test circuit can be used for the panel test and the touch detection, and the wiring quantity is reduced. Electronic equipment adopts above-mentioned display panel, can reduce and walk line quantity, is convenient for realize narrow frame design and comprehensive screen design.

Description

Display panel and electronic device

Technical Field

The application relates to the technical field of electronic equipment, in particular to a display panel and electronic equipment.

Background

With the continuous progress of science and technology, more and more electronic devices with display functions are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.

The main part of the electronic equipment for realizing the display function is the display panel, and along with the continuous strong functions of the electronic equipment, the display panel is required to have not only the image display function, but also other functions, such as the integrated touch electrode has the touch detection function, so that the display panel needs to have more wiring, and the narrow frame design and the comprehensive screen design are not convenient.

Disclosure of Invention

In view of the above, the present application provides a display panel and an electronic device, and the scheme is as follows:

a display panel having a display area and a bezel area, the display panel comprising:

a plurality of sub-pixels disposed in the display area, the sub-pixels being electrically connected to the data lines;

a touch electrode located in the display area;

a touch signal line electrically connected to the touch electrode;

a test circuit disposed in the frame area; the test circuit comprises a signal transmission line which is electrically connected with the touch signal line;

the connecting wires correspond to the data wires one to one, the signal transmission wires are communicated with the data wires through the connecting wires in the testing stage, the signal transmission wires are used for inputting testing signals for the data wires, the connecting wires are disconnected with the testing circuit in the non-testing stage, and the signal transmission wires output touch signals detected by the touch electrodes.

In the display panel provided by the technical scheme of the application, the test circuit is provided with the signal transmission line, the signal transmission line is electrically connected with the touch signal line, and the signal transmission line is also electrically connected with the data line through the connecting wiring. Therefore, in the test stage, the test signal can be input into the data line through the signal line transmission line, the panel test is realized through the signal transmission line, in the non-test stage, the connection wiring and the test circuit are disconnected, the signal transmission line outputs the touch signal detected by the touch electrode, the touch detection is realized through the signal transmission line, and the signal transmission line in the visible test circuit can be used for the panel test and the touch detection, so that the wiring quantity is reduced.

The application also provides an electronic device which comprises the display panel.

The electronic equipment that this application technical scheme provided adopts above-mentioned display panel, can reduce and walk line quantity, is convenient for realize narrow frame design and comprehensive screen design.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structure, proportion, size and the like shown in the drawings are only used for matching with the content disclosed in the specification, so that the person skilled in the art can understand and read the description, and the description is not used for limiting the limit condition of the implementation of the invention, so the method has no technical essence, and any structural modification, proportion relation change or size adjustment still falls within the scope of the technical content disclosed by the invention without affecting the effect and the achievable purpose of the invention.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another display panel provided in the embodiment of the present application;

fig. 3 is a schematic structural diagram of a test circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a pass circuit unit in the test circuit shown in FIG. 3;

FIG. 5 is a schematic diagram of a display array in a display panel according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another test circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram illustrating an arrangement of signal transmission lines in a display panel according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating an arrangement of switch signal lines in a display panel according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the existing display panel, the test circuit is only used for panel test before leaving factory and is used for testing whether data lines are broken or sub-pixels which cannot be normally displayed exist, and the test circuit needs to be provided with separate wiring and a gating circuit to be electrically connected with the data lines. The touch signal lines of the touch electrodes also need to be provided with separate routing lines and gating circuits, so that the number of the signal lines and the gating circuits in the panel is large, and a large step area needs to be occupied.

In order to solve the above problem, in the display panel and the electronic device provided in the embodiments of the present application, a signal transmission line of the touch trace multiplexing test circuit is designed, so that it is not necessary to separately set traces and gating circuits for the touch traces, the number of traces and the number of gating circuits are reduced, and narrow-frame and full-screen designs of the electronic device are facilitated.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

As shown in fig. 1, fig. 1 is a schematic structural diagram of a display panel provided in the present embodiment, the display panel 100 has a display area AA and a frame area BB, and the display panel includes:

a plurality of sub-pixels P disposed in the display area AA, the sub-pixels P being electrically connected to the DATA lines DATA;

a touch electrode 200 located in the display area AA;

a touch signal line TP electrically connected to the touch electrode 200;

a test circuit 11 arranged in the frame area BB; the test circuit 11 comprises a signal transmission line TPX which is electrically connected with the touch signal line TP;

the connecting wires 13 correspond to the DATA lines DATA one to one, in a testing stage, the signal transmission lines TPX are communicated with the DATA lines DATA through the connecting wires 13, the signal transmission lines TPX are used for inputting testing signals for the DATA lines DATA, in a non-testing stage, the connecting wires 13 are disconnected with the testing circuit 11, and the signal transmission lines TPX output touch signals detected by the touch electrodes.

It should be noted that fig. 1 only shows one touch electrode 200, the display panel has a plurality of touch electrodes 200, and the plurality of touch electrodes 200 are arranged in an array, and the specific number and arrangement of the touch electrodes 200 are not limited in this application. The touch electrode 200 and the touch signal line TP may be connected through a via hole in different layers, and in order to reduce the connection impedance, the touch electrode 200 and the electrically connected touch signal line TP may be connected through a plurality of via holes, which are not shown in fig. 1.

The metal layer can be added to the display panel for manufacturing the touch electrode 200, or the existing metal layer in the display panel can be reused as the touch electrode 200. For example, when the display panel is an LCD panel, the common electrode may be reused as the touch electrode 200, when the display panel is an OLED panel, the OLED sub-pixels need to be protected by an encapsulation layer, and a metal layer is added on a side of the encapsulation layer away from the OLED sub-pixels to form the touch electrode 200. In the embodiment of the present application, the implementation manner of the touch electrode 200 is not particularly limited.

The DATA line DATA may be electrically connected to the display control chip 14 located in the frame area BB, and in the non-test stage, the display control chip 14 provides the DATA signal to the sub-pixel P through the DATA line DATA to implement the light emitting display of the sub-pixel P.

In the display panel provided by the technical scheme of the application, in the test stage, the signal transmission line TPX of the test circuit 11 can not only provide a test signal for the DATA line DATA through the connection wiring 13, so as to realize the panel test (such as VT test), the display image of the display panel can be displayed based on the input test signal, whether the DATA line DATA open circuit or the dead pixel P exists in the test is detected, in the non-test stage, the signal transmission line TPX can also acquire and output the touch signal detected by the touch electrode 200 to the touch chip through the touch signal line TP, and the touch chip realizes the touch detection based on the touch signal. Therefore, the signal transmission line TPX in the test circuit 11 can be used for panel testing and touch detection, and the number of the wires is reduced.

In the technical scheme of the application, after the test stage is completed, the connection wire 13 between the test circuit 11 and the DATA line DATA can be directly cut off, so that the open circuit of the connection wire 13 and the test circuit 11 is realized in the non-test stage, and as shown by a dotted line L in fig. 1, the connection wire 13 between the test circuit 11 and the DATA line DATA can be cut off by laser. Alternatively, a switching element is provided in the connection trace 13 between the test circuit 11 and the DATA line DATA, by which the connection trace 13 between the test circuit 11 and the DATA line DATA is broken.

In the testing stage, the testing circuit 11 inputs the testing signal for the DATA line DATA through the signal transmission line TPX, at this time, the touch signal line TP is electrically connected to the signal transmission line TPX, and the signal transmission line TPX is used as the input signal line.

In the prior art, the test circuit is only used for VT testing, and after the VT testing is completed, the test circuit is not used, but in the technical solution of the present application, the test circuit 11 can perform panel testing in the test stage, and in the non-test stage, can be used as a gate circuit for touch detection, and outputs a touch signal detected by the touch electrode 200 for touch detection.

As shown in fig. 2, fig. 2 is a schematic structural diagram of another display panel provided in the embodiment of the present application, and based on the manner shown in fig. 1, in the display panel shown in fig. 2, the test circuit 11 has a plurality of first gating transistors T1; the test circuit 11 also has a switching signal line sw.

The first gate transistor T1 has a gate, a first electrode, and a second electrode. The gate of the first gating transistor T1 is electrically connected to the switch signal line sw, the first electrode of the first gating transistor T1 is electrically connected to the touch signal line TP and is electrically connected to the corresponding DATA line DATA through the connection trace 13, and the second electrode of the first gating transistor T1 is electrically connected to the signal transmission line TPX. The conductive state of the first gating transistor T1 is controlled by the switching signal line sw. In the embodiment of the present application, one of the first electrode and the second electrode of the gate transistor is a drain, and the other is a source.

The first gating transistors T1 are electrically connected to the DATA lines DATA in a one-to-one correspondence, and different first gating transistors T1 are electrically connected to different DATA lines DATA. The first electrode of each first gating transistor T1 is electrically connected to the corresponding DATA line DATA through a separate connection trace 13. In the test stage, the switch signal line sw controls the conduction state of the first gating transistor T1 so as to provide a test signal for the data line through the signal transmission line TPX to implement the panel test, and in the non-test stage, the switch signal line sw controls the conduction state of the first gating transistor T1 to obtain the touch signal output by the touch electrode 200 through the signal transmission line TPX to implement the touch detection.

The test circuit has a plurality of gate circuit units 111, and at least a part of the gate circuit units 111 includes a plurality of first gate transistors T1. The gate circuit unit 111 has a plurality of first gate transistors, and can reduce the equivalent impedance of the touch signal line TP and the electrically connected gate circuit unit 111. In the same gate circuit unit 111, the first gate transistor T1 electrically connects the same touch signal line TP, signal transmission line TPX, and switch signal line sw. In this manner, the same gate circuit unit 111 can simultaneously supply the test signals to the plurality of DATA lines DATA through the same signal transfer line TPX, and the plurality of first gate transistors T1 can be controlled based on the same switching signal line sw, reducing the number of the signal transfer lines TPX and the switching signal lines sw.

Only one gate circuit unit 111 is shown in fig. 2, and the gate circuit unit 111 has four first gate transistors T1. The number of the first gating transistors T1 in the same gating circuit unit 111 may be set to any number based on the requirement, and is not limited to four as shown in fig. 2, and may be set to 3 or 6. The number of the gate circuit units 111 may be set based on the number of the DATA lines DATA in the display panel and the number of the first gate transistors T1 in each of the gate circuit units 111, and in the embodiment of the present application, the number of the DATA lines DATA in the display panel and the number of the gate circuit units 111 are not particularly limited.

As shown in fig. 3 and 4, fig. 3 is a schematic structural diagram of a test circuit provided in an embodiment of the present application, and fig. 4 is a schematic structural diagram of a gate circuit unit in the test circuit shown in fig. 3, and in combination with fig. 2 to 4, a test circuit 11 has a plurality of gate circuit groups 10, and the gate circuit groups 10 have a plurality of gate circuit units 111; in the same gating circuit group 10, the gating circuit units 111 are electrically connected to the same signal transmission line TPX; the gate circuit units 111 in the different gate circuit groups 10 are electrically connected to the different signal transmission lines TPX.

In the embodiment of the present application, the gating circuit group 10 includes a plurality of gating circuit units 111, and the plurality of gating circuit units 111 in the same gating circuit group 10 share the same signal transmission line TPX, so that the number of the signal transmission lines TPX is greatly reduced.

The number of the first gating transistors T1 in each gating circuit unit 111 may be set to be the same, and the number of the pass circuit units 111 in each gating circuit group 10 may be set to be the same, so as to facilitate circuit layout, test driving, and touch detection. In another mode, the number of the first gate transistors T1 may be different for each gate circuit unit 111, and the number of the gate circuit units 111 may be different for each gate circuit group 10. Alternatively, the number of the first gate transistors T1 in the partial gate circuit unit 111 may be the same, and the number of the first gate transistors T1 in another partial gate circuit unit 111 may be different. Similarly, the number of the conducting circuit units 111 in one part of the gated circuit group 10 may be different, and the number of the conducting circuit units 111 in the other part of the gated circuit group 10 may be different. And are not limited herein.

As shown in fig. 3 and 4 in conjunction, each gate circuit group 10 includes Y gate circuit units 111, Y being a positive integer greater than 1; in the same gating circuit group 10, the gating circuit units 111 are respectively and correspondingly connected with one switch signal line sw, the gating circuit groups 10 are electrically connected with Y switch signal lines sw, and each gating circuit group 10 is electrically connected with the same Y switch signal lines. In the embodiment of the present application, taking Y ═ 30 as an example for explanation, each gate circuit group 10 includes 30 gate circuit units 111, and 30 switch signal lines sw and 30 touch signal lines TP are electrically connected correspondingly. Obviously, Y can be set to be any positive integer greater than 1 based on requirements, and is not limited to be Y of 30, and the value of Y is not limited in the embodiment of the present application.

In the embodiment of the application, the same gating circuit group 10 is electrically connected with Y switch signal lines sw, in the same gating circuit group 10, the Y switch signal lines sw are electrically connected with the gating circuit units 111 in a one-to-one correspondence mode, and different gating circuit units 111 are electrically connected with different switch signal lines sw. All the gate circuit groups 10 share the Y switch signal lines sw, so that the number of the switch signal lines sw is greatly reduced.

As shown in fig. 3 and 4, the test circuit 11 has N gate circuit groups 10, where N is a positive integer greater than 1; the arrangement extending direction of the gate circuit units 111 in the gate circuit group 10 is a first direction F1, a plurality of gate circuit units 111 are sequentially arranged in a straight line direction, the straight line direction is the extending direction thereof, and the first direction F1 is parallel to the straight line; in the same gate circuit group 10, along the first direction F1, Y (Y is 30 in fig. 4) gate circuit units 111 are the 1 st gate circuit unit to the Y th gate circuit unit in sequence. The switching signal lines sw are the 1 st to the Y-th switching signal lines sw1 to swY in this order along the second direction Y. The test circuit 11 has N signal transmission lines TPX (N is 12 in fig. 3), and the signal transmission lines TPX are sequentially the 1 st signal transmission line TPX1 to the nth signal transmission line TPXN along the first direction F1. In the gating circuit group 10, the Y-th gating circuit unit is electrically connected with the Y-th switching signal line swy, and Y is a positive integer not greater than Y; the gate circuit unit 111 in the nth gate circuit group is electrically connected to the nth signal transmission line TPXn, N being a positive integer not greater than N. The second direction F2 is perpendicular to the first direction F1.

Through setting values of Y and N, a plurality of gating circuit units 111 in the same gating circuit group 10 can share the same signal transmission line TPX, different gating circuit groups 10 can share Y switch signal lines sw, and the number of the signal transmission lines TPX and the switch signal lines sw is greatly reduced. And a plurality of gating circuit groups 10 are sequentially arranged in the first direction F1, a plurality of signal transmission lines TPX which are correspondingly and electrically connected are sequentially arranged in the first direction F1, and a plurality of switching signal lines which are common to the plurality of gating circuit groups 10 are arranged in the second direction F2, so that wiring is facilitated, and complicated winding is not needed.

In the embodiment of the present application, the first direction F1 may be perpendicular to the extending direction of the DATA lines DATA in the display area AA. The second direction F2 is parallel to the extending direction of the DATA lines DATA in the display area AA, and is directed from the display area AA to the test circuit 11.

In the non-test stage, when performing touch detection, the same gating circuit group 10 is connected to Y touch signal lines TP to perform touch detection in a time-sharing manner, so as to determine the touch signal line TP outputting a touch signal at the current time.

The values of Y and N are related to the number of DATA lines DATA in the display panel, and may be set based on requirements, which is not specifically limited in the embodiment of the present application. For example, the display panel has 1440 columns of sub-pixels, each column of sub-pixels is electrically connected to one DATA line DATA separately, and has 1440 DATA lines DATA, N may be set to 12, Y may be set to 30, and each gate circuit unit 111 has 4 first gate transistors T1, and 4 × Y may be set to N may be set to 1440.

As an example, in the first direction F1, 30 gate units 111 in the 1 st gate circuit group shown in fig. 4 sequentially serve as the 1 st gate unit to the 30 th gate unit, and sequentially electrically connect the 1 st touch signal line TP1 to the 30 th touch signal line TP30 correspondingly. In fig. 3, there are 30 switching signal lines sw, and in the second direction F2, the 30 switching signal lines sw are sequentially the 1 st switching signal line sw1 through the 30 th switching signal line sw30, there are 12 gate circuit groups 10, correspondingly electrically connected to the 12 signal transmission lines TPX, the 12 signal transmission lines TPX are sequentially the 1 st signal transmission line TPX1 to the 12 th signal transmission line TPX12, and have 360 touch signal lines TP in total, the first direction F1 is sequentially a 1 st touch signal line TP1 to a 360 th touch signal line TP360, wherein 30 gate circuit units 111 in the 1 st gate circuit group are respectively and correspondingly electrically connected to the 1 st touch signal line TP1 to the 30 th touch signal line TP30, 30 gate circuit units 111 in the 2 nd gate circuit group are respectively and correspondingly electrically connected to the 31 st touch signal line TP31 to the 60 th touch signal lines TP60, …, and 30 gate circuit units 111 in the 12 th gate circuit group are respectively and correspondingly and electrically connected to the 331 st touch signal line TP331 to the 360 th touch signal line TP 360.

As can be seen, for the display panel with 1440 columns of sub-pixels, based on the technical solution of the embodiment of the present application, the same gate circuit unit 111 can provide test signals for 4 data lines at the same time, and only 30 switch signal lines sw and 12 signal transmission lines TPX are needed, so that the number of traces is greatly reduced.

As shown in fig. 5, fig. 5 is a schematic diagram of a display array in a display panel provided in the present embodiment, the display panel has a display array, the display array has a plurality of sub-pixels P arranged in an array, the display array has three color sub-pixels P, and the three color sub-pixels P are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively. The color of any adjacent three sub-pixels P in the same row is set to be different. In any two adjacent columns of the sub-pixels P, one column of the sub-pixels P is formed by alternately arranging red sub-pixels R and blue sub-pixels B, and the other sub-pixel P is a green sub-pixel G. Therefore, each pixel unit is provided with four sub-pixels P, the four sub-pixels P form a 2 x 2 Bayer array, and the four sub-pixels P are provided with one blue sub-pixel B, one red sub-pixel R and two green sub-pixels G, and the arrangement mode can simulate the sensitivity and specificity of human eyes to green to realize color restoration, and meanwhile, the arrangement mode is convenient for color restoration.

It should be noted that the number of rows and columns of the subpixels P in the display array is set according to requirements, and fig. 5 is only a schematic illustration and does not show the actual number of rows and columns of the subpixels P in the display panel. In addition, in the display panel provided in the embodiment of the present application, the arrangement manner of the sub-pixels P in the display array is not limited to the arrangement manner shown in fig. 5, and the arrangement manners such as RYYB and RGBW may also be adopted, which is not specifically limited in the embodiment of the present application.

As shown in fig. 6, fig. 6 is a schematic structural diagram of another test circuit provided in the embodiment of the present application, and as shown in fig. 2 to fig. 6, a plurality of second gate transistors T2 corresponding to the first gate transistors T1 one to one are provided in the frame area BB, and each of the second gate transistors T2 and the first gate transistors T1 has a gate, a first electrode, and a second electrode. A first electrode of the second gate transistor T2 is electrically connected with a first electrode of the corresponding first gate transistor T1; in the testing phase, the first gate transistor T1 and the second gate transistor T2 are turned on in a time-sharing manner to provide the testing signals for the DATA lines DATA connected electrically, respectively, and after the testing phase, the gate of the second gate transistor T2 inputs the turn-off signal, so that the second electrode of the second gate transistor T2 is disconnected from the DATA lines DATA.

In the embodiment of the present application, the existing first gating transistor T1 in the multiplexing panel forms the test circuit 11 of the present application, and in the test stage, the test circuit 11 of the present application provides the test signal for the sub-pixel P in the DATA line DATA in a time-sharing manner through the first gating transistor T1 in the test circuit and the existing second gating transistor T2 in the panel, so that the test efficiency is faster.

The first gating transistor T1 may be set to PMOS or NMOS on demand, and the second gating transistor T2 may be set to PMOS or NMOS on demand.

Three adjacent DATA lines DATA are shown in FIG. 6_i-1、DATA_iAnd DATA_i+1And a first gate transistor T1 and a second gate transistor T2 are connected to each data line. The gates of the three first gating transistors T1 are electrically connected to a switch signal line sw, respectively, to control the on state of the first gating transistor T1 via the switch signal line sw, and the gates of the second transistors T2 are electrically connected to a control signal line sw' to control the on state of the second gating transistor T2, respectively. When the test is completed, the control signal line sw' inputs a constant turn-off signal, so that the second gate transistor T2 is turned off to open the second electrode of the second gate transistor T2 from the DATA line DATA.

In the technical scheme of the application, the first gating transistor T1 in the shorting bar (shorting bar) for VT test in the display panel is multiplexed to form the gating circuit unit 111, specifically, the second electrodes of the four first gating transistors T1 for inputting the same color sub-pixel test signal are shorted to form one gating circuit unit 111, for example, the second electrodes of the four first gating transistors T1 for inputting the red sub-pixel test signal r are shorted to form one gating circuit unit 111, the second electrodes of the four first gating transistors T1 for inputting the green sub-pixel test signal g are shorted to form one gating circuit unit 111, and the second electrodes of the four first gating transistors T1 for inputting the blue sub-pixel test signal b are shorted to form one gating circuit unit 111.

It is assumed that the display area AA has M DATA lines DATA sequentially arranged in the first direction F1, where M is a positive integer and is a multiple of 3. The M DATA lines DATA are sequentially the 1 st DATA line DATA in the first direction F1₁To the Mth DATA line DATA_M. The M DATA lines DATA include 3 DATA line groups, which are a first DATA line group, a second DATA line group, and a third DATA line group, respectively. The M DATA lines DATA are correspondingly connected to the M first gating transistors T1. In the first direction F1, the M first gate transistors T1 may be sequentially arranged based on the connected DATA lines DATA, or may be sequentially arranged in other sorting manners in the first direction F1, and a flexible circuit layout may be implemented by using a jumper line and a via hole, which is not specifically limited in this embodiment of the present invention.

The DATA lines DATA in the first DATA line group satisfy a first general expression a_m3m-2, i.e. the 1 st DATA line DATA₁DATA line No. 4₄And 7 th DATA line DATA₇…, a_mDATA line DATA_3m-2All belong to the first data line group.

The DATA lines DATA in the second DATA line group satisfy a second general expression b_m3m-1, i.e. the 2 nd DATA line DATA₂And the 5 th DATA line DATA₅8 th DATA line DATA₈…, b_mDATA line DATA_3m-1All belong to the second data line group.

The DATA lines DATA in the third DATA line group satisfy a third formula c_m3m, i.e. the 3 rd DATA line DATA₃6 th DATA line DATA₆9 th DATA line DATA₉…, c_mDATA line DATA_3mAll belong to the third data line group.

Wherein, a_m、b_mAnd c_mAre all less than M. M is related to M, and M is M/3.

In the same DATA line group, the DATA lines DATA are respectively connected to a first gate transistor T1, and in the test phase, the second electrodes of the first gate transistors T1 all input the test signals of the same color sub-pixels, and with reference to fig. 6, for example, the second electrodes of the first gate transistors T1 connected to the DATA lines DATA in the first DATA line group can be set to input the red sub-pixel test signal r in the test phase, the second electrodes of the first gate transistors T1 connected to the DATA lines DATA in the second DATA line group can be set to input the green sub-pixel test signal g in the test phase, and the second electrodes of the first gate transistors T1 connected to the DATA lines DATA in the third DATA line group can be set to input the blue sub-pixel test signal b in the test phase.

In the same DATA line group, all the DATA lines DATA are equally divided into a plurality of DATA line subgroups, each DATA line subgroup has X DATA lines DATA sequentially arranged in the first direction F1, X is a positive integer greater than 1, and m is an integer multiple of X. The X first gate transistors T1 electrically connected to the X DATA lines DATA in the same DATA line subset form one gate unit 111, and if X is 4, each gate unit 111 has four first gate transistors T1. In the same data line group, Y adjacent gate circuit units 111 are arranged as one gate circuit group 10.

For example, M1440, X, 4, Y, 30, there are 480 DATA lines DATA in the same DATA line group, the correspondingly connected 480 first gate transistors T1 are divided into 120 gate circuit units 111, the 120 gate circuit units 111 are divided into 4 gate circuit groups 10, the three DATA line groups form 12 gate circuit groups 10, each gate circuit group 10 is electrically connected to 30 touch signal lines TP, and the total number of 30 touch signal lines TP is 30. In this way, the same gate circuit group 10 is correspondingly connected to 30 touch signal lines TP, and outputs touch signals in a time-sharing manner through the same signal transmission line TPX, which requires 12 signal transmission lines TPX in total. The signal transmission line TPX is connected with the touch chip, and the touch chip is used for touch detection based on the touch signal. The touch chip and the display control chip 14 may be the same chip, and at this time, the display control chip is not only used to drive the sub-pixel P to display an image, but also used to perform touch detection based on a touch signal output by the signal transmission line TPX, or the touch chip and the display control chip 14 are two independent chips.

For example, for the first data line group, 30 gate circuit units 111 connected to the red subpixel test signal r form one gate circuit group 10, and 30 correspondingly connected touch signal lines TP output touch signals in a time-sharing manner through the same signal transmission line TPX.

As shown in fig. 7, fig. 7 is a schematic diagram of an arrangement manner of signal transmission lines in a display panel according to an embodiment of the present disclosure, in a test phase, in order to facilitate uniform input of sub-pixel test signals of the same color by a probe, a plurality of signal transmission line groups are provided, where each signal transmission line group has a plurality of signal transmission lines TPX; the plurality of signal transmission lines TPX in the same signal transmission line group are adjacently arranged. All the signal transmission lines TPX may be arranged in sequence in the first direction F1. As can be provided with 3 signal

transmission line groups

21, 22, 23.

The signal transmission lines TPX which can set all input red sub-pixel test signals r are arranged adjacently in sequence, the signal transmission lines TPX which set all input green sub-pixel test signals g are arranged adjacently in sequence, and the signal transmission lines TPX which set all input blue sub-pixel test signals b are arranged adjacently in sequence, so that the connection test of the test signal input probes and the signal transmission lines TPX can be facilitated. As described in the above embodiment, when there are 1440 DATA lines DATA, and 12 signal transmission lines TPX are correspondingly disposed, there are 4 signal transmission lines TPX for inputting the red subpixel test signal r, and the 4 signal transmission lines TPX are adjacently arranged in sequence and are a transmission line group 21; the pixel circuit comprises 4 signal transmission lines TPX for inputting green sub-pixel test signals g, wherein the 4 signal transmission lines TPX are arranged adjacently in sequence and form a transmission line group 22; there are 4 signal transmission lines TPX to which the blue subpixel test signal b is input, and the 4 signal transmission lines TPX are arranged adjacent to each other in sequence as a transmission line group 23.

In the embodiment of the present application, the display panel has a plurality of sub-pixels P, and the plurality of sub-pixels includes: a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels; for example, the first sub-pixel may be a red sub-pixel R, the second sub-pixel may be a green sub-pixel G, and the third sub-pixel may be a blue sub-pixel B. Having three signal

transmission line groups

21, 22, 23; at the same time in the test phase, the same test signal is input to the multiple signal transmission lines TPX in the same signal transmission line group, and the three signal transmission line groups are respectively used for different test signals. In this way, the signal transmission lines TPX corresponding to the first data line group are all inputted with the red subpixel test signal r, the signal transmission lines TPX corresponding to the second data line group are all inputted with the green subpixel test signal, the signal transmission lines TPX corresponding to the third data line group are all inputted with the blue subpixel test signal, and the display test of all the subpixels is realized through the second gating transistor T2 corresponding to the first gating transistor T1.

As shown in fig. 8, fig. 8 is a schematic diagram of an arrangement manner of switch signal lines in a display panel provided in this embodiment of the application, in a test stage, in order to facilitate a probe to contact with a switch signal line sw, so that a first gating transistor T1 is turned on for testing, all the switch signal lines sw are arranged adjacently in sequence, and no other trace exists between the adjacent switch signal lines sw. The switching signal lines sw may be arranged in sequence in the second direction F2. The switch signal line sw can be connected with the touch chip, and when touch detection is performed, a control signal is provided for the touch chip through the touch chip so as to control the on state of the touch chip. As described above, when there are 30 switching signal lines sw, the 30 switching signal lines sw may be the 1 st switching signal line sw1 to the 30 th switching signal down sw30 in order in the second direction F2.

As shown in fig. 9, fig. 9 is a schematic structural diagram of another display panel provided in the embodiment of the present application, and with reference to fig. 2 to 4, 6 and 9, the frame area BB has a bonding area CC, the bonding area CC has a pad electrically connected to the DATA line DATA, and the pad is used for fixedly and electrically connecting the display control chip 14; the first gate transistor T1 is located at a side of the bonding area CC facing away from the display area AA, and the gate circuit units 111 are located at a side of the bonding area CC facing away from the display area AA. In the same gate circuit unit 111, the plurality of connecting traces 13 connected to each other may be arranged adjacently in the first direction F1, so as to facilitate the subsequent cutting and disconnection uniformly. It should be noted that fig. 9 shows the gate circuit unit 111, the position of the gate circuit unit 111 is used to represent the position of the first gate transistor T1 relative to the strapping region CC, the first gate transistor T1 is not shown, and the structure and wiring principle of the first gate transistor T1 can refer to the above description.

As shown in fig. 10, fig. 10 is a schematic structural diagram of another display panel provided in the embodiment of the present application, and referring to fig. 2 to 4, 6, 9 and 10, a frame area BB has a plurality of second gate transistors T2 corresponding to DATA lines DATA one to one, and a second gate transistor T2 has a gate, a first electrode and a second electrode; a first electrode of the second gate transistor T2 is electrically connected with a first electrode of the corresponding first gate transistor T1; the second gate transistor T2 is located between the display area AA and the binding area CC. The first gate transistor T1 and the second gate transistor T2 are respectively disposed at two sides of the bonding region CC, so that the connection trace 13 connected to the gate circuit unit 111 can be cut and disconnected. It should be noted that fig. 10 shows the gate circuit unit 111, the position of the gate circuit unit 111 is used to represent the position of the first gate transistor T1 relative to the strapping region CC, the first gate transistor T1 is not shown, and the structure and wiring principle of the first gate transistor T1 can refer to the above description; the position of the second gate transistor T2 with respect to the strapping region CC is represented by the position of a circuit block corresponding one-to-one to the gate circuit cells 111, and the second gate transistor T2 is not shown, and the circuit block includes four second gate transistors T2 corresponding to the gate circuit cells 111.

In the embodiment of the present application, the sub-pixel P has a pixel transistor. The first gate transistor T1 and the second gate transistor T2 are in the same layer as the pixel transistor, the first gate transistor T1 and the second gate transistor T2 are formed at the same time when the pixel transistor is formed, and the first gate transistor T1 and the second gate transistor T2 do not need to be manufactured by separate processes, so that the manufacturing process is simple and the manufacturing cost is low.

In the embodiment of the application, the sub-pixel is provided with a pixel transistor; the first gate transistor T1 is in the same layer as the pixel transistor. The second transistor T2 is provided at the same level or different level from the pixel transistor based on wiring requirements.

The display panel can be an LCD panel or an OLED panel, and the OLED panel can be a hard panel or a flexible bendable panel.

In the embodiment of the present application, the number of the first gate transistors T1 in each gate circuit unit 111 may be the same as described above, and in other ways, the first gate transistors T1 in the gate circuit units 111 may be different as shown in fig. 11.

As shown in fig. 11, fig. 11 is a schematic structural diagram of another display panel provided in the present embodiment, based on the foregoing embodiment, in the manner shown in fig. 11, a signal transmission line TP is used for connecting a touch chip; the display panel is provided with a plurality of touch electrodes 200, the plurality of touch electrodes 200 at least comprise a first touch electrode 201 and a second touch electrode 202, and the distance from the first touch electrode 201 to the touch chip is greater than the distance from the second touch electrode 202 to the touch chip; the number of the first gate transistors T1 in the gate circuit unit 111 correspondingly connected to the first touch electrode 201 is greater than the number of the first gate transistors T1 in the gate circuit unit 111 correspondingly connected to the second touch electrode 202.

In fig. 11, taking an example that the gate circuit unit 111 correspondingly connected to the first touch electrode 201 has 4 first gate transistors T1, and the gate circuit unit 111 correspondingly connected to the second touch electrode 202 has 2 first gate transistors T1, the number of the first gate transistors T1 correspondingly connected to each touch electrode 200 may be set according to requirements, and is not limited to the manner shown in fig. 4.

Because the distances between the touch electrode 200 and the touch chip are different, the connection lengths between the touch electrode and the touch chip are different, and the connection lengths are different, impedance is uneven, and touch accuracy is affected. Based on the method shown in fig. 11, the first gating transistors T1 with a smaller number of connections are disposed corresponding to the touch electrodes 200 with a larger distance from the touch chip, and the first gating transistors T1 with a larger number of connections are disposed corresponding to the touch electrodes 200 with a smaller distance from the touch chip, so that the difference between the connection resistances of the touch electrodes 200 with different distances from the touch chip can be reduced, and the touch accuracy can be improved.

It should be noted that, in the technical solution of the present application, a plurality of touch electrodes 200 may be arranged in an array, a distance between each touch electrode 200 and a touch chip is a distance in a reverse direction of extension of the touch trace TP in the display area AA, in the touch electrodes 200 arranged in the array, if the extending direction is a column direction of the array, distances between each touch electrode 200 and the touch chip in the same column are different, the number of the touch electrodes 200 correspondingly connected to the first gating transistor T1 is gradually increased from the display area to the touch chip, distances between each touch electrode 200 and the touch chip in the same row are the same, and the distances between each touch electrode 200 and the touch chip in the same row are correspondingly connected to the same number of the first gating transistors T1.

Based on the foregoing embodiment, another embodiment of the present application further provides an electronic device, as shown in fig. 12, fig. 12 is a schematic structural diagram of the electronic device provided in the embodiment of the present application, the electronic device includes a display panel 41, and the display panel 41 is a display panel in any mode of the foregoing embodiments.

The electronic equipment can be mobile phones, tablet computers, intelligent wearable equipment and other electronic equipment with a display function. The electronic equipment adopts the display panel of the embodiment, so that the wiring quantity can be reduced, and the narrow frame and the comprehensive screen design are facilitated.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. For the electronic device disclosed in the embodiment, since it corresponds to the display panel disclosed in the embodiment, the description is relatively simple, and the relevant points can be described with reference to the corresponding parts of the display panel.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel having a display area and a frame area, the display panel comprising:

the touch electrode is positioned in the display area;

a touch signal line electrically connected to the touch electrode;

the test circuit is arranged in the frame area; the test circuit comprises a signal transmission line which is electrically connected with the touch signal line;

the connection wires correspond to the data wires one to one, the signal transmission wires are communicated with the data wires through the connection wires in a test stage, the signal transmission wires are used for inputting test signals to the data wires, the connection wires and the test circuit are in open circuit in a non-test stage, and the signal transmission wires output the touch signals detected by the touch electrodes.

2. The display panel of claim 1, wherein the test circuit has a plurality of first pass transistors having a gate, a first electrode, and a second electrode; the test circuit is also provided with a switch signal line; the grid electrode of the first gating transistor is electrically connected with the switch signal line, the first electrode of the first gating transistor is electrically connected with the touch signal line and is electrically connected with the corresponding data line through the connecting routing line, and the second electrode of the first gating transistor is electrically connected with the signal transmission line.

3. The display panel according to claim 2, wherein the test circuit has a plurality of gate circuit units, at least a part of the gate circuit units including a plurality of the first gate transistors;

in the same gating circuit unit, the first gating transistors are electrically connected with the same touch signal line, the same signal transmission line and the same switch signal line, and the first gating transistors are electrically connected with the data lines in a one-to-one correspondence manner.

4. The display panel according to claim 3, wherein the signal transmission line is used for connecting a touch chip;

the display panel is provided with a plurality of touch electrodes, the touch electrodes at least comprise a first touch electrode and a second touch electrode, and the distance from the first touch electrode to the touch chip is greater than the distance from the second touch electrode to the touch chip;

the number of the first gating transistors in the gating circuit unit correspondingly connected with the first touch electrode is larger than that of the first gating transistors in the gating circuit unit correspondingly connected with the second touch electrode.

5. The display panel according to claim 3, wherein the test circuit has a plurality of gate circuit groups having a plurality of the gate circuit units;

in the same gating circuit group, the gating circuit units are electrically connected with the same signal transmission line; and the gating circuit units in different gating circuit groups are electrically connected with different signal transmission lines.

6. The display panel according to claim 5, wherein each of the gate circuit groups includes Y of the gate circuit units, Y being a positive integer greater than 1; in the same gating circuit group, the gating circuit units are respectively and correspondingly connected with one switch signal line, the gating circuit groups are electrically connected with Y switch signal lines, and each gating circuit group is electrically connected with the same Y switch signal lines.

7. The display panel according to claim 6, wherein the test circuit has N of the gate circuit groups, N being a positive integer greater than 1; the arrangement extending direction of the gating circuit units in the gating circuit group is a first direction; in the same gating circuit group, along the first direction, Y gating circuit units are from the 1 st gating circuit unit to the Y th gating circuit unit in sequence;

along a second direction, the switch signal lines are sequentially from a 1 st switch signal line to a Y-th switch signal line; the second direction is perpendicular to the first direction;

the test circuit is provided with N signal transmission lines, and the signal transmission lines are sequentially a 1 st signal transmission line to an Nth signal transmission line along the first direction;

in the gating circuit group, the Y-th gating circuit unit is electrically connected with a Y-th switching signal line, and Y is a positive integer not greater than Y; the gating circuit units in the nth gating circuit group are electrically connected with the nth signal transmission line, and N is a positive integer not greater than N.

8. The display panel according to claim 2, wherein the frame region has a plurality of second gate transistors in one-to-one correspondence with the first gate transistors, the second gate transistors having gates, first electrodes, and second electrodes; the first electrode of the second gating transistor is electrically connected with the first electrode of the corresponding first gating transistor;

in the test stage, the first gating transistor and the second gating transistor are turned on in a time-sharing mode to respectively provide the test signals for the data lines which are electrically connected, and after the test stage, a gate of the second gating transistor is input with a turn-off signal, so that the second electrode of the second gating transistor is disconnected with the data lines.

9. The display panel of claim 2, wherein the frame area has a bonding area, the bonding area has a bonding pad electrically connected to the data line, and the bonding pad is used for fixedly and electrically connecting the display control chip;

the first gating transistor is positioned on one side of the binding region, which is far away from the display region.

10. The display panel according to claim 9, wherein the frame region has a plurality of second gate transistors in one-to-one correspondence with the data lines, the second gate transistors having a gate electrode, a first electrode, and a second electrode; the first electrode of the second gating transistor is electrically connected with the first electrode of the corresponding first gating transistor;

the second gating transistor is located between the display region and the binding region.

11. The display panel according to claim 8 or 10, wherein the sub-pixel has a pixel transistor;

the first gating transistor, the second gating transistor and the pixel transistor are on the same layer.

12. The display panel according to claim 2, wherein the sub-pixel has a pixel transistor;

the first gating transistor and the pixel transistor are in the same layer.

13. The display panel according to claim 1, wherein there are a plurality of signal transmission line groups having a plurality of the signal transmission lines;

and a plurality of signal transmission lines in the same signal transmission line group are arranged adjacently.

14. The display panel of claim 13, wherein the plurality of sub-pixels comprises: a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels;

having three of said signal transmission line groups; at the same time of the test stage, the same test signal is input to a plurality of signal transmission lines in the same signal transmission line group, and the three signal transmission line groups are respectively used for different test signals.

15. An electronic device characterized by comprising the display panel according to any one of claims 1 to 14.