CN113035877B - Manufacturing method of semiconductor device, semiconductor device and electronic device - Google Patents
Manufacturing method of semiconductor device, semiconductor device and electronic device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 153
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims abstract description 101
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000000463 material Substances 0.000 claims abstract description 49
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 238000000926 separation method Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 61
- 230000010354 integration Effects 0.000 abstract description 3
- 230000015654 memory Effects 0.000 description 25
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
The invention provides a method of manufacturing a semiconductor device, and an electronic apparatus. The method comprises the following steps: step S1, providing a semiconductor substrate, forming a floating gate structure on the semiconductor substrate, wherein the floating gate structure comprises a floating gate layer, and the floating gate structure comprises a spacing region exposing part of the semiconductor substrate; step S2, forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer; step S3, depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure; step S4, patterning the control gate material layer to form a control gate structure, the control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer. According to the invention, the integration of the flash memory device and the manufacturing process of the PIP capacitor is realized, and the PIP capacitor with the upper structure and the lower structure is changed into a left structure and a right structure.
Description
Technical Field
The invention relates to the technical field of motors, in particular to a manufacturing method of a semiconductor device, the semiconductor device and an electronic device.
Background
Flash memories are divided into two types: stacked gate (stack gate) devices and split gate (split gate) devices. Stacked gate devices having a floating gate and a control gate, wherein the control gate is located above the floating gate, are simpler to manufacture than split gate devices, however, stacked gate devices suffer from over-erase problems. Different from the stacked gate device, the word line serving as the erasing gate is formed on one side of the floating gate of the split gate device, and the word line serves as the control gate. In addition, the split gate device is programmed by using source end hot electron injection, and has higher programming efficiency, so that the split gate device is widely applied to various electronic products such as smart cards, SIM cards, microcontrollers, mobile phones and the like.
In flash memories, PIP capacitors are widely used to prevent noise and frequency modulation of analog devices. However, due to the difference in structure between split gate devices and stacked gate devices, additional process steps are required to integrate the PIP capacitor in the split gate device process. As shown in fig. 1A to 1E, a process of forming a flash memory cell and a PIP capacitor in a stacked gate device process is illustrated, wherein the process of forming the flash memory cell and the PIP capacitor includes: as shown in fig. 1A, a tunnel oxide layer 101 and a floating gate material layer 102 covering the tunnel oxide layer 101 are formed on a semiconductor substrate 100; as shown in fig. 1B, an ONO (oxide-nitride-oxide) layer 103 is formed on the floating gate material layer 102; as shown in fig. 1C, a control gate material layer 104 is formed to cover the NON layer 103 and the floating gate material layer 102; as shown in fig. 1D, the control gate material layer 104, the tunnel oxide layer 101, the floating gate material layer 102 and the ONO layer 103 are patterned to form a control gate structure a, and then a portion of the control gate material layer and the ONO layer 103 are removed to form a logic gate structure B and a PIP capacitor C; as shown in fig. 1E, contact holes 105 are formed to connect the semiconductor substrate 100, the control gate structure a, the logic gate structure B, and the PIP capacitor C, respectively, wherein the control gate material layer 104 in the PIP capacitor C constitutes an upper plate of the PIP capacitor, and the floating gate material layer 102 in the PIP capacitor C constitutes a lower plate of the PIP capacitor. As shown in fig. 2A-2E, a process of forming a split-gate device, as shown in fig. 2A, a floating gate structure 201 is formed on a semiconductor substrate 200, the floating gate structure includes a gate electrode layer 2011, a floating gate material layer 2012 and a field oxide 2013 which are stacked in sequence; as shown in fig. 2B, a tunnel oxide layer 202 is formed; as shown in fig. 2C, a control gate material layer 203 is formed; as shown in fig. 2D, the control gate material layer 203 is etched to form a gate structure; as shown in fig. 2E, contact holes 204 are formed to connect the control gate material layer 203 and the semiconductor substrate 200, respectively. Comparing the above-described processes of forming the flash memory cell and the PIP capacitor in the stacked gate device process of fig. 1A to 1E and the processes of forming the split gate device of fig. 2A to 2E, it is apparent that the processes of forming the PIP capacitor cannot be incorporated into the processes of forming the split gate device.
For this reason, it is necessary to provide a new method for manufacturing a semiconductor device, and an electronic apparatus, which solve the problems in the prior art.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the problems in the prior art, the present invention provides a method of manufacturing a semiconductor device, the method including:
step S1, providing a semiconductor substrate, forming a floating gate structure on the semiconductor substrate, wherein the floating gate structure comprises a floating gate layer, and the floating gate structure comprises a spacing region exposing part of the semiconductor substrate;
step S2, forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer;
step S3, depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure;
step S4, patterning the control gate material layer to form a control gate structure partially covering the dielectric layer on the side wall of the floating gate layer, wherein,
the floating gate layer, the control gate structure and the dielectric layer between the side wall of the floating gate layer and the control gate structure form a PIP capacitor.
Illustratively, the dielectric layer comprises a tunnel oxide layer.
Illustratively, the semiconductor substrate includes a flash memory device region and a PIP capacitor region.
Illustratively, the spaced regions are arranged in stripes arranged side by side along the first direction.
Illustratively, the floating gate structure located in the PIP capacitor region includes at least two strip-shaped gates juxtaposed along a first direction, with the spacer region disposed therebetween.
Illustratively, the floating gate structure in the PIP capacitor region is configured as a block gate, and the block gate includes a plurality of the spacer regions arranged in parallel along a first direction, and the spacer regions are in a stripe shape.
Illustratively, the control gate structure layer covers the floating gate structure along the first direction and exposes a part of the semiconductor substrate.
Exemplarily, the method further comprises the following steps: forming contact holes to connect the floating gate layer, the control gate structure to an external circuit to constitute the PIP capacitor.
Illustratively, the contact holes include a first contact hole contacting the floating gate layer and a second contact hole contacting the control gate structure, wherein the first contact hole contacts a sidewall of the floating gate layer.
Illustratively, the first contact hole is located at the spacing region.
Illustratively, the spacing regions are arranged in stripes arranged side by side along a first direction, and the first contact hole aperture is larger than or equal to the width of the spacing regions in the first direction.
Illustratively, the first contact hole is located at an end of the spacing region.
The present invention also provides a semiconductor device comprising:
a semiconductor substrate;
a floating gate structure on a semiconductor substrate, the floating gate structure including a floating gate layer and including a spacer region therein exposing a portion of the semiconductor substrate;
the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer;
the control gate structure partially covers the dielectric layer on the side wall of the floating gate layer; wherein,
the floating gate layer, the control gate structure and the dielectric layer between the floating gate layer and the control gate structure on the side wall of the floating gate layer form a PIP capacitor.
Illustratively, the dielectric layer comprises a tunnel oxide layer.
Illustratively, the semiconductor substrate includes a flash memory device region and a PIP capacitor region.
Illustratively, the spaced regions are arranged in stripes arranged side by side along the first direction.
Illustratively, the floating gate structure in the PIP capacitor region includes at least two strip-shaped gates juxtaposed along a first direction, with the spacer region disposed therebetween.
Illustratively, the floating gate structure in the PIP capacitor region is configured as a block gate, and the block gate includes a plurality of the spacer regions arranged in parallel along a first direction, and the spacer regions are in a stripe shape.
Illustratively, the control gate structure layer covers the floating gate structure along the first direction and exposes a part of the semiconductor substrate.
Illustratively, the PIP capacitor further comprises a contact hole connecting the floating gate layer and the control gate structure to an external circuit.
Illustratively, the contact holes include a first contact hole contacting the floating gate layer and a second contact hole contacting the control gate structure, wherein the first contact hole contacts a sidewall of the floating gate layer.
Illustratively, the first contact hole is located at the spacing region.
Illustratively, the spacing regions are arranged in stripes arranged side by side along a first direction, and the first contact hole aperture is larger than or equal to the width of the spacing regions in the first direction.
Illustratively, the first contact hole is located at an end of the spacing region.
The invention also provides an electronic device comprising the semiconductor device
According to the manufacturing method of the semiconductor device, the semiconductor device and the electronic device, the integration of the manufacturing process of the flash memory device and the PIP capacitor is realized, the PIP capacitor is formed by arranging the dielectric layer between the side wall of the floating gate layer in the floating gate structure and the control gate structure, and the PIP capacitor with the upper structure and the lower structure is changed into a left structure and a right structure, so that the PIP capacitor is manufactured while the flash memory unit is manufactured without adding any process steps and other costs.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A to 1E are flowcharts of forming a flash memory cell and a PIP capacitor in a stacked gate device process according to a method of manufacturing a semiconductor device;
FIGS. 2A-2E are flow diagrams of a split gate device process according to a method of fabricating a semiconductor device;
fig. 3A-1-3E-5 are schematic structural views of a semiconductor device formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein,
FIG. 3A-1, FIG. 3B-1, FIG. 3C-1, FIG. 3D-1 and FIG. 3E-1 are schematic structural views of a flash memory device region including a split gate structure in a semiconductor device formed in a method of manufacturing a semiconductor device according to an embodiment of the present invention,
figures 3A-4, 3B-4, 3C-4, 3D-4 and 3E-4 are top structural views of a PIP capacitor region in a semiconductor device formed in a method of fabricating a semiconductor device according to one embodiment of the present invention,
figures 3A-5, 3B-5, 3C-5, 3D-5 and 3E-5 are top structural views of a PIP capacitor region in a semiconductor device formed in a method of fabricating a semiconductor device according to another embodiment of the present invention,
fig. 3A-2, 3B-2, 3C-2, 3D-2 and 3E-2 are schematic structural views of the semiconductor device viewed in the X direction of the PIP capacitor region shown in fig. 3A-4, 3B-4, 3C-4, 3D-4 and 3E-4,
fig. 3A-3, 3B-3, 3C-3, 3D-3 and 3E-3 are schematic structural views of the semiconductor device viewed in the Y direction of the PIP capacitor region shown in fig. 3A-4, 3B-4, 3C-4, 3D-4 and 3E-4;
fig. 4 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.
In the following description, a detailed description will be given to explain a method of manufacturing a semiconductor device, and an electronic apparatus according to the present invention, in order to thoroughly understand the present invention. It is apparent that the invention is not limited in its application to the details of the details known to those skilled in the art of electrical machinery. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
Example one
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, including:
step S1, providing a semiconductor substrate, forming a floating gate structure on the semiconductor substrate, wherein the floating gate structure comprises a floating gate layer, and the floating gate structure comprises a spacing region exposing part of the semiconductor substrate;
step S2, forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer;
step S3, depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure;
step S4, patterning the control gate material layer to form a control gate structure partially covering the dielectric layer on the side wall of the floating gate layer, wherein,
the floating gate layer, the control gate structure and the dielectric layer between the side wall of the floating gate layer and the control gate structure form a PIP capacitor.
Referring to fig. 3A-1 to 3E-4 and fig. 4, a method of manufacturing a semiconductor device according to the present invention will be exemplarily described. FIGS. 3A-1 through 3E-4 are schematic structural views of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIGS. 3A-1, 3B-1, 3C-1, 3D-1 and 3E-1 are schematic structural views of a flash memory device region including a split gate structure in the semiconductor device formed in the method for manufacturing a semiconductor device according to an embodiment of the present invention, FIGS. 3A-4, 3B-4, 3C-4, 3D-4 and 3E-4 are schematic top structural views of a middle capacitor region in the semiconductor device formed in the method for manufacturing a semiconductor device according to an embodiment of the present invention, FIGS. 3A-5, 3B-5, PIP, Fig. 3C-5, 3D-5, and 3E-5 are schematic top structure views of a PIP capacitor region in a semiconductor device formed in a method of manufacturing a semiconductor device according to another embodiment of the present invention, fig. 3A-2, 3B-2, 3C-2, 3D-2, and 3E-2 are schematic structure views of a semiconductor device according to an X-direction observation of the PIP capacitor region illustrated in fig. 3A-4, 3B-4, 3C-4, 3D-4, and 3E-4, and fig. 3A-3, 3B-3, 3C-3, 3D-3, and 3E-3 are schematic structure views of a semiconductor device according to a Y-direction observation of the PIP capacitor region illustrated in fig. 3A-4, 3B-4, 3C-4, 3D-4, and 3E-4 A schematic structural view of the member; fig. 4 is a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
First, referring to fig. 4, step S1 is performed: providing a semiconductor substrate, forming a floating gate structure on the semiconductor substrate, wherein the floating gate structure comprises a floating gate layer, and the floating gate structure comprises a spacing region exposing part of the semiconductor substrate.
As shown in fig. 3A-1, 3A-2, 3A-3, 3A-4, and 3A-5, a semiconductor substrate 300 is provided, and a floating gate structure 301 is formed on the semiconductor substrate 300, wherein the floating gate structure 301 includes a spacer region 300A exposing a portion of the semiconductor substrate 300.
Illustratively, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
Illustratively, isolation structures (not shown) are formed in the semiconductor substrate 300.
Illustratively, the method of forming the isolation structure in the semiconductor substrate 300 includes: forming a patterned mask layer in a semiconductor substrate, and exposing a region to be formed with a shallow trench isolation structure in the semiconductor substrate; performing an etching process by taking the patterned mask layer as a mask to form a shallow trench; performing a chemical vapor deposition process to fill the isolation material layer in the shallow trench; and performing a chemical mechanical polishing process to remove the isolation material layer outside the shallow trench. The above-mentioned method for forming the isolation structure in the semiconductor substrate may be any method known to those skilled in the art, and will not be described herein.
With continued reference to fig. 3A-1, 3A-2, and 3A-3, floating gate structure 301 includes a gate dielectric layer 3011, a floating gate layer 3012, and a field oxide 3013.
According to the present invention, a manufacturing process of a PIP capacitor is integrated in a manufacturing process of a split gate device, fig. 3A-1 illustrates a schematic structural view of a flash memory cell device region, fig. 3A-2, 3A-3, and 3A-4 illustrate schematic structural views of a PIP capacitor region, wherein fig. 3A-4 and 3A-5 illustrate a plan structural view of a PIP capacitor region, and fig. 3A-2 and 3A-3 illustrate a cross-sectional structural view, respectively, as viewed in an X direction and a Y direction of fig. 3A-4.
Illustratively, the method of forming the floating gate structure 301 includes: forming a gate dielectric material layer and a floating gate material layer which are sequentially stacked on a semiconductor substrate; forming a patterned hard mask layer (such as a silicon nitride layer) on the floating gate material layer; performing an ion implantation process by taking the patterned hard mask layer as a mask to form a floating gate implantation region in the semiconductor substrate of the region to be formed with the floating gate structure; performing a thermal oxidation process to form field oxide in the floating gate material layer above the floating gate injection region; and removing the hard mask layer and the floating gate material layer outside the upper part of the floating gate injection region.
Illustratively, the material of the gate dielectric layer 3011 includes silicon oxide.
Illustratively, the material of the floating gate layer 3012 includes monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, and the like.
According to an example of the present invention, the floating gate structure 301 is a block in a flash memory cell device region.
According to an example of the present invention, as shown in fig. 3A-4, in the PIP capacitor region, the floating gate structure 301 includes a spacer region 300A that exposes a portion of the semiconductor substrate 300, such that the floating gate structure 301 is spaced apart by a portion of the semiconductor substrate 300. A spacer region is provided in the floating gate structure 301, and in the subsequent process of forming the control gate structure of the flash memory cell device, a dielectric layer (for example, a tunneling oxide layer is formed by oxidizing the semiconductor substrate) is formed on the semiconductor substrate 300 to cover the side wall of the floating gate structure 301, so that the floating gate structure is used as the dielectric layer of the interplate dielectric layer in the PIP capacitor, and thus, the manufacturing process of the PIP capacitor can be incorporated into the manufacturing process of the flash memory cell device with a split gate structure.
Illustratively, the spacing regions 300A are arranged in stripes.
Illustratively, as shown in fig. 3A-4, in the PIP capacitor region, the floating gate structure 301 is configured as a block gate, and the block gate includes a plurality of the spacer regions 300A arranged side by side along the first direction, the spacer regions 300A are in a stripe shape, and the spacer regions 300A expose the semiconductor substrate 300. Because the floating gate material layer is oxidized into the field oxide by thermal oxidation in the forming process of the floating gate structure, and the interval regions are arranged into a plurality of strips instead of a block shape which is connected into a piece, the phenomenon that the floating gate material layer is completely oxidized and is not conductive in the thermal oxidation process, so that a subsequent PIP device cannot be formed can be avoided.
According to an example of the present invention, as shown in fig. 3A-4, the spaced-apart regions 300A are formed as spaced-apart regions 300A juxtaposed along a first direction (as shown in the Y-direction in fig. 3B-4).
Illustratively, as shown in fig. 3A-5, in the PIP capacitor region, the floating gate structure 301 includes at least two strip-shaped gates 301A arranged in parallel along a first direction, and the strip-shaped gates have the spacing region 300A therebetween, which exposes the semiconductor substrate 300. Like the example in which the floating gate structure 301 includes the strip-shaped spacing regions 300A arranged in parallel along the first direction, the floating gate structure 301 is provided with a plurality of strip-shaped gates arranged in parallel along the first direction, and the spacing regions are also strip-shaped, so that it can be avoided that the floating gate material layer is completely oxidized and is not conductive in the thermal oxidation process, which results in that a subsequent PIP device cannot be formed.
Meanwhile, the floating gate structure 301 is set to include the strip-shaped spacing region 300A, and in the process of subsequently forming the contact hole to connect the floating gate layer in the floating gate structure 301 out, the contact hole can be set in the strip-shaped spacing region to increase the probability that the contact hole is in contact with the floating gate layer in the floating gate structure 301, so that poor contact caused by contact hole deviation is avoided.
In the following embodiments, the floating gate structure 301 is a block gate in which a plurality of stripe-shaped spacer regions 300A arranged in parallel along the first direction are arranged in the PIP capacitor region. It is to be understood that the embodiment that the floating gate structure 301 is configured as a block gate and the plurality of stripe-shaped spacing regions arranged in parallel along the first direction are arranged in the block gate is only exemplary, and those skilled in the art will understand that any method of arranging the spacing regions in the floating gate structure to expose a portion of the semiconductor substrate is applicable to the present invention.
Illustratively, the floating gate structure 301 of the above-described block-shaped flash memory cell device region is formed in the same floating gate formation process as the floating gate structure 301 of the PIP capacitor region. Specifically, when a patterned hard mask layer for performing an ion implantation process is formed, the patterned mask layer covers a region of the floating gate structure 301 in the flash memory cell device region where the semiconductor substrate 300 is to be exposed, so that after a floating gate implantation region is formed subsequently, the hard mask layer and the floating gate material layer outside the floating gate implantation region are removed, and at the same time, the region of the floating gate structure 301 in the flash memory cell device region where the semiconductor substrate 300 is to be exposed is exposed. The above process can be performed by designing the pattern of the patterned hard mask layer, which is a technique well known to those skilled in the art and will not be described herein.
Continuing, referring to fig. 4, step S2 is performed: and forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer.
As shown in fig. 3B-1, 3B-2, 3B-3 and 3B-4, a dielectric layer 302 is formed on the surface of the semiconductor substrate 300, wherein the dielectric layer 302 also covers the sidewalls of the floating gate structure 301.
According to the present invention, a manufacturing process of a PIP capacitor is integrated in a manufacturing process of a split gate flash memory cell device, fig. 3B-1 illustrates a structural view of a flash memory cell device region, fig. 3B-2, 3B-3, 3B-4, and 3B-5 illustrate structural views of a PIP capacitor region, wherein fig. 3B-4 and 3B-5 illustrate a plan view of a PIP capacitor region, and fig. 3B-2 and 3B-3 illustrate cross-sectional structural views viewed in X and Y directions of fig. 3B-4, respectively.
As shown in fig. 3B-1, the sidewalls of the floating gate structure 301 of the flash memory cell device region and the semiconductor substrate 300 are covered with a dielectric layer 302, which serves as a dielectric layer between the control gate and the floating gate structure in the subsequent manufacturing process of the flash memory cell device.
As shown in fig. 3B-2, 3B-3, 3B-4 and 3B-5, in the PIP capacitor region, the dielectric layer 302 serves as a dielectric layer 302 between the plates of the subsequent PIP capacitor, and the dielectric layer 302 covers the semiconductor substrate 300 and the sidewalls of the floating gate layer 3012 of the floating gate structure 301.
Illustratively, the method of forming the dielectric layer 302 includes: a deposition process is performed to cover the surface of the semiconductor substrate 300 and the surface of the floating gate structure with a layer of dielectric material, wherein the layer of dielectric material also covers the sidewalls of the floating gate structure 301.
Illustratively, the dielectric layer 302 includes a tunneling oxide layer, and the dielectric layer 302 is set as the tunneling oxide layer, so that the formation process of the dielectric layer can be simplified, the formed dielectric layer has uniform thickness and good dielectric property, and finally, the formation of the semiconductor device is improved.
Illustratively, the method of forming the dielectric layer 302 includes: a thermal oxidation process is performed to oxidize the surface of the semiconductor substrate 300 and the floating gate layer 3012 of the floating gate structure 301 to a tunnel oxide layer.
Continuing, referring to fig. 4, step S3 is performed: and depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure.
As shown in fig. 3C-1, 3C-2, 3C-3, 3C-4 and 3C-5, a control gate material layer 303 is formed on the surface of the semiconductor substrate 300, wherein the control gate material layer 303 covers the dielectric layer 302 of the flash memory cell device region and the floating gate structure 301, and at the same time, the control gate material layer 301 also covers the floating gate structure 301 and the dielectric layer 302 of the PIP capacitor region.
Illustratively, the material of the control gate material layer 303 includes single crystal silicon, polysilicon, doped polysilicon, and the like.
Exemplary methods for forming the control gate material layer 303 include chemical vapor deposition, physical vapor deposition, and the like, which are well known to those skilled in the art and will not be described herein.
Continuing, referring to fig. 4, step S4 is performed: patterning the control gate material layer to form a control gate structure, the control gate structure partially covering the dielectric layer on the sidewall of the floating gate layer.
After patterning the control gate material layer 303, a control gate structure 304 is formed, as shown in fig. 3D-1, 3D-2, 3D-3, 3D-4 and 3D-5. The floating gate layer 3012, the control gate structure 304, and the dielectric layer 302 between the sidewalls of the floating gate layer 3012 and the control gate structure 304 form a PIP capacitor, as shown by the dashed boxes in fig. 3D-3 and 3D-4.
In accordance with the present invention, a manufacturing process of the PIP capacitor is integrated in a manufacturing process of the split-gate device, and fig. 3D-1 shows a schematic structural diagram of a flash memory cell device region, partially covering a floating gate structure 301 on a control gate structure 304. Fig. 3D-2, 3D-3, 3D-4 and 3D-5 are schematic structural views of the PIP capacitor region, wherein fig. 3D-4 is a schematic plan structural view of the PIP capacitor region, and fig. 3D-2 and 3D-3 are schematic sectional structural views observed in the X direction and the Y direction of fig. 3D-4, respectively.
As shown in fig. 3D-1, the control gate structure 304 of the flash cell device region constitutes a split gate of the flash cell.
As shown in fig. 3D-2, 3D-3, 3D-4 and 3D-5, the control gate structure 304 partially overlaps the floating gate structure 301 existing as a stripe gate in the PIP capacitor region, wherein the control gate structure 304 overlaps the floating gate structure along a direction (Y direction) aligned with the stripe gate. Referring to fig. 3D-2 and 3D-3, in the PIP capacitor, the sidewall of the floating gate structure 301 serves as an upper plate, the control gate structure 304 on the opposite sidewall serves as a lower plate, and the dielectric layer 302 on the sidewall of the control gate structure 304 serves as a dielectric layer of the PIP capacitor.
The capacitance value of the PIP capacitor according to the present invention will be exemplarily described below with reference to an example in which the floating gate structure 301 is provided as a block gate and a plurality of stripe-shaped spacer regions arranged side by side in the first direction are provided in the block gate.
Illustratively, the floating gate layer 3012 in the floating gate structure has a thickness h (as shown in fig. 3D-2), the control gate structure 304 in the region of the PIP capacitor covering the floating gate structure 301 has a width L, and the dielectric layer 302 has a thickness D 1 The strip-shaped spacing region 300A is to adopt a block-shaped gate as the floating gate structure 301 and divide the floating gate structure into n strips, the width of a single strip is w, and the spacing between adjacent strips (i.e., the width of the spacing region) is d; thus, according to the formula for the plate capacitance:
in the present invention, the capacitance of the PIP capacitor is:
further, in the PIP capacitor according to the present invention, the coverage area of the control gate is used as an effective area of the PIP capacitor, and S' ═ w × n + d (n-1)]L, when n is large, the capacitance per unit area is calculated as n-1 ≈ n:
for a process with a specific size, the height of the floating gate structure is determined, that is, the floating gate layer h in the floating gate structure is determined, C' is the width w of the strip shape separated by the interval from the floating gate structure, the width d of the interval region and the thickness d of the dielectric layer 302 1 Determining that the width w of the stripe, the width d of the spacer region and the thickness of the dielectric layer 302 are d 1 The smaller, theThe larger the capacitance C' of the bit area.
In a conventional flash memory device process with a stacked gate structure, an ONO layer is used as a dielectric layer in a PIP capacitor, wherein the thickness of the ONO layer is relatively thick, so that C' for finally forming the PIP capacitor is relatively small. In the PIP capacitor according to the present invention, the capacitance C' per unit area is increased by reducing the thickness of the dielectric layer 302, for example, forming a tunnel oxide layer. Further, according to an example of the present invention, the spacer regions provided on the floating gate structure of the PIP capacitor region are stripe-shaped, so that the number n-1 of stripe-shaped spacer regions and the width L of the control gate material layer 303 covering the floating gate structure 301 can be selected according to the value of the capacitance C' per unit area to obtain a desired capacitance value.
It is to be understood that the above-mentioned process of calculating the capacitance of the capacitor is only exemplary in the example that the floating gate structure 301 is provided as a block gate and a plurality of strip-shaped spacing regions arranged in parallel along the first direction are provided in the block gate, and those skilled in the art will understand that the floating gate structure 301 is provided as at least two strip-shaped gates 301A arranged in parallel and the strip-shaped spacing regions 300A are provided between the strip-shaped gates 301A, and similar calculation can be performed according to the above-mentioned method.
So far, an exemplary description has been given of a method of manufacturing a semiconductor device according to the present invention. In one example according to the present invention, further comprising: contact structures are formed to electrically connect the respective structures of the flash memory cell device region and the PIP capacitor region to an external circuit.
As shown in fig. 3E-1, 3E-2, 3E-3, 3E-4, and 3E-5, contact holes 305 are formed, wherein the contact holes 305 located at the flash memory cell device region connect the control gate structure 304 and the semiconductor substrate 300 to Word Lines (WL), Bit Lines (BL), and control Source Lines (SL) of an external circuit, and simultaneously, the contact holes 305 located at the PIP capacitor region connect the control gate structure 304 and the floating gate layer 3012 of the floating gate structure 301 to an external circuit as lower and upper plates of a PIP capacitor.
Illustratively, the contact hole 305 located at the PIP capacitor region includes a first contact hole 3051 and a second contact hole 3052, wherein the first contact hole 3051 connects the floating gate layer 3012 of the floating gate structure 301 to an external circuit by contacting with a sidewall of the floating gate structure 301; the second contact hole 3052 leads out the control gate structure to an external circuit.
In one example according to the present invention, as shown in fig. 3E-2, 3E-3, 3E-4, and 3E-5, first contact holes 3051 are provided at the spacing region 300A to connect the floating gate layer 3012 of the floating gate structure 301 to an external circuit by contacting with the sidewalls of the floating gate structure 301.
In one example according to the present invention, as shown in fig. 3E-4 and 3E-5, the spacing regions 300A are disposed in a stripe shape juxtaposed along the first direction, and the aperture of the first contact hole 3051 is greater than or equal to the width of the spacing region in the first direction. The aperture of the first contact hole 3051 is set to be greater than or equal to the width of the spacing region in the first direction, so that the phenomenon that the contact hole cannot be in contact with the floating gate layer of the floating gate structure when being aligned and offset can be reduced, the process cost is reduced, and the yield of semiconductor devices is improved.
In one example according to the present invention, as shown in fig. 3E-4 and 3E-5, the first contact hole 3051 is located at an end of the spacing region 300A, so that when the aperture of the contact hole is larger than the width of the spacing region in the first direction, contact with at least two sides of the floating gate layer of the floating gate structure can be achieved (in an example in which the floating gate structure is provided as a block gate and a plurality of stripe-shaped spacing regions are provided in the block gate in parallel along the first direction, contact with three sides can be achieved, as shown in fig. 3E-4), thereby further reducing the occurrence of a phenomenon that contact with the floating gate layer of the floating gate structure is not possible due to alignment shift of the contact hole.
The above is an exemplary description of a method for manufacturing a semiconductor device according to the present invention, and according to the method for manufacturing a semiconductor device of the present invention, integration of a flash memory device and a PIP capacitor is realized, a PIP capacitor is formed by disposing a dielectric layer between a side wall of a floating gate layer in a floating gate structure and a control gate structure, and the PIP capacitor of an upper and lower structure is changed into a left and right structure, so that the PIP capacitor is manufactured while a flash memory cell is manufactured without increasing any process steps and other costs.
Example two
The present invention also provides a semiconductor device comprising:
a semiconductor substrate;
the floating gate structure comprises a floating gate layer, and the floating gate structure comprises a spacing region which exposes part of the semiconductor substrate;
the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer;
a control gate structure partially covering the floating gate structure; wherein,
the floating gate layer, the control gate structure and the dielectric layer between the floating gate layer and the control gate structure on the side wall of the floating gate layer form a PIP capacitor.
It is manufactured using the method described in example one.
A semiconductor device according to an example of the present invention is exemplarily described with reference to fig. 3E-1, fig. 3E-2, fig. 3E-3, fig. 3E-4, and fig. 3E-5.
As shown in fig. 3E-1, 3E-2, 3E-3, 3E-4, and 3E-5, the semiconductor device according to the present invention includes a semiconductor substrate 300.
Illustratively, a semiconductor device according to the present invention includes a flash memory device region and a PIP capacitor region. Fig. 3E-1 illustrates a schematic view of a device structure as a flash memory device region, fig. 3E-4 and 3E-5 illustrate schematic plan views of devices as a PIP capacitor region, and fig. 3E-2 and 3E-3 illustrate schematic views of device structures as viewed in X and Y directions of fig. 3E-4, respectively.
According to the semiconductor device of the present invention, the semiconductor substrate 300 includes a floating gate structure 301 thereon, and the floating gate structure 301 includes a spacer region 300A therein to expose a portion of the semiconductor substrate 300.
Illustratively, the floating gate structure 301 includes a gate dielectric layer 3011, a floating gate layer 3012, and a field oxide 3013.
Illustratively, the material of the gate dielectric layer 3011 includes silicon oxide.
Illustratively, the material of the floating gate layer 3012 includes monocrystalline silicon, polycrystalline silicon, doped polycrystalline silicon, and the like.
According to the semiconductor device of the invention, the semiconductor substrate 300 and the side wall of the floating gate layer 3012 of the floating gate structure 301 are covered by a dielectric layer 302.
Illustratively, the dielectric layer 302 includes a tunnel oxide layer. The dielectric layer 302 is set as a tunneling oxide layer, so that the forming process of the dielectric layer can be simplified, the formed dielectric layer is uniform in thickness and good in dielectric property, and finally the formation of a semiconductor device is improved.
According to the semiconductor device of the present invention, the control gate structure 304 partially covers the dielectric layer on the sidewall of the floating gate layer 3012 of the floating gate structure 301; the floating gate layer 3012, the control gate structure 304, and the dielectric layer 302 located between the floating gate layer 3012 and the control gate structure 304 on the sidewall of the floating gate layer 3012 form a PIP capacitor.
Illustratively, as shown in fig. 3E-4 and 3E-5, the spaced areas 300A are arranged in stripes arranged side by side along the first direction. Because the floating gate material layer is oxidized into the field oxide by thermal oxidation in the forming process of the floating gate structure, and the interval regions are arranged into a plurality of strips instead of being connected into a block, the phenomenon that the floating gate material layer is completely oxidized and is not conductive in the thermal oxidation process, so that a subsequent PIP device cannot be formed can be avoided.
Meanwhile, the floating gate structure 301 is set to include the strip-shaped spacing region 300A, and in the process of subsequently forming the contact hole to connect the floating gate layer in the floating gate structure 301 out, the contact hole can be set in the strip-shaped spacing region to increase the probability that the contact hole is in contact with the floating gate layer in the floating gate structure 301, so that poor contact caused by contact hole deviation is avoided.
Illustratively, as shown in fig. 3E-5, the floating gate structure 301 in the PIP capacitor region includes at least two strip-shaped gate electrodes 301A juxtaposed along a first direction, with the spacer region disposed therebetween.
Illustratively, as shown in fig. 3E-4, the floating gate structure 301 in the PIP capacitor region is configured as a block gate, and the block gate includes a plurality of the spaced regions 300A arranged in parallel along a first direction, and the spaced regions are in the shape of stripes. The spaced regions arranged on the floating gate structure of the PIP capacitor region are in the shape of strips, so that the number of the strip spaced regions and the width of the control gate structure 304 covering the floating gate structure 301 can be selected according to the value of the capacitance per unit area to be designed to obtain the required capacitance value.
Illustratively, as shown in FIGS. 3E-4 and 3E-5, the control gate structure 304 covers the floating gate structure along the first direction and exposes a portion of the semiconductor substrate.
Illustratively, as shown in fig. 3E-1, 3E-2, 3E-3, 3E-4, and 3E-5, contact holes 305 are further included to connect the floating gate layer, the control gate structure, and the external circuit to form the PIP capacitor.
Illustratively, as shown in fig. 3E-2, 3E-3, 3E-4, and 3E-5, the contact holes 305 include a first contact hole 3051 in contact with the floating gate layer 3012 and a second contact hole 3052 in contact with the control gate structure 304, wherein the first contact hole 3051 is in contact with a sidewall of the floating gate layer 3012.
Illustratively, as shown in FIGS. 3E-2, 3E-3, 3E-4, and 3E-5, the first contact hole is located in the spacing region 300A.
Illustratively, as shown in fig. 3E-4 and 3E-5, the spacing regions 300A are disposed in a stripe shape juxtaposed along the first direction, and the aperture of the first contact hole 3051 is greater than or equal to the width of the spacing region in the first direction. The aperture of the first contact hole 3051 is set to be greater than or equal to the width of the spacing region in the first direction, so that the phenomenon that the contact hole cannot be in contact with the floating gate layer of the floating gate structure when being aligned and offset can be reduced, the process cost is reduced, and the yield of semiconductor devices is improved.
Illustratively, the first contact hole 3051 is located at an end portion of the spacing region 300A, so that when an aperture of the contact hole is larger than a width of the spacing region in the first direction, contact with at least two sides of the floating gate layer of the floating gate structure can be achieved (in an example in which the floating gate structure is provided as a block gate and a plurality of stripe-shaped spacing regions are provided in the block gate in parallel along the first direction, contact with three sides can be achieved, as shown in fig. 3E-4), thereby further reducing occurrence of a phenomenon that contact with the floating gate layer of the floating gate structure cannot be achieved due to alignment shift of the contact hole.
The above is an exemplary description of a semiconductor device according to the present invention, in which a flash memory device and a PIP capacitor are integrated, wherein the PIP capacitor is formed by disposing a dielectric layer between a side wall of a floating gate layer in a floating gate structure and a control gate structure, and the PIP capacitor in an upper and lower structure is changed into a left and right structure, so that a PIP capacitor can be manufactured while a flash memory cell is manufactured without adding any process steps or other costs.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device according to embodiment two. According to the semiconductor device, the flash memory device and the PIP capacitor are integrated, wherein the PIP capacitor is formed by arranging the dielectric layer between the side wall of the floating gate layer in the floating gate structure and the control gate structure, and the PIP capacitor with the upper structure and the lower structure is changed into a left-right structure, so that the PIP capacitor can be manufactured while the flash memory unit is manufactured without increasing any process steps and other costs; thus, the electronic device according to the invention also has the advantages described above.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A semiconductor device, comprising:
the semiconductor substrate comprises a flash memory device region and a PIP capacitor region, wherein the flash memory device region is a flash memory device region comprising a separation gate structure;
the floating gate structure is positioned on a semiconductor substrate and comprises a floating gate layer and field oxide positioned on the floating gate layer, and the floating gate structure comprises a spacing region exposing part of the semiconductor substrate;
the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer;
the control gate structure partially covers the dielectric layer on the side wall of the floating gate layer; wherein,
the floating gate layer, the control gate structure and the dielectric layer between the floating gate layer and the control gate structure on the side wall of the floating gate layer form a PIP capacitor.
2. The semiconductor device of claim 1, wherein the dielectric layer comprises a tunnel oxide layer.
3. The semiconductor device according to claim 1, wherein the spacing regions are provided in a stripe shape juxtaposed in the first direction.
4. The semiconductor device of claim 3, wherein the floating gate structure in the PIP capacitor region comprises at least two strip-shaped gates juxtaposed along a first direction, the strip-shaped gates having the spacer region disposed therebetween.
5. The semiconductor device of claim 3, wherein the floating gate structure in the PIP capacitor region is configured as a block gate comprising a plurality of spacer regions juxtaposed along a first direction, the spacer regions being stripe-shaped.
6. The semiconductor device of claim 3, wherein the control gate structure layer covers the floating gate structure along the first direction and exposes a portion of the semiconductor substrate.
7. The semiconductor device according to claim 1 or 3, further comprising contact holes connecting the floating gate layer, the control gate structure to an external circuit to constitute the PIP capacitor.
8. The semiconductor device according to claim 7, wherein the contact hole comprises a first contact hole in contact with the floating gate layer and a second contact hole in contact with a control gate structure, wherein the first contact hole is in contact with a sidewall of the floating gate layer.
9. The semiconductor device according to claim 8, wherein the first contact hole is located in the spacing region.
10. The semiconductor device according to claim 9, wherein the arrangement of the spacing regions is a stripe shape arranged side by side along a first direction, and the first contact hole aperture is larger than or equal to a width of the spacing region in the first direction.
11. The semiconductor device according to claim 8, wherein the first contact hole is located at an end portion of the spacing region.
12. A method of manufacturing a semiconductor device, comprising:
step S1, providing a semiconductor substrate, forming a floating gate structure on the semiconductor substrate, wherein the floating gate structure comprises a floating gate layer, and the floating gate structure comprises a spacing region exposing part of the semiconductor substrate;
step S2, forming a dielectric layer on the surface of the semiconductor substrate, wherein the dielectric layer covers the semiconductor substrate and the side wall of the floating gate layer;
step S3, depositing a control gate material layer on the surface of the semiconductor substrate to cover the dielectric layer and the floating gate structure;
step S4, patterning the control gate material layer to form a control gate structure partially covering the dielectric layer on the side wall of the floating gate layer, wherein,
the floating gate layer, the control gate structure and the dielectric layer between the side wall of the floating gate layer and the control gate structure form a PIP capacitor.
13. An electronic device comprising the semiconductor device according to claim 1.
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| CN109979993A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | High-pressure MOS component and preparation method thereof, electronic device |
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| KR101205029B1 (en) * | 2010-12-30 | 2012-11-26 | 에스케이하이닉스 주식회사 | Capacitor in non-volatile memory device |
| US9559178B2 (en) * | 2015-01-23 | 2017-01-31 | Nxp Usa, Inc. | Non-volatile memory (NVM) cell and device structure integration |
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Denomination of invention: A manufacturing method for semiconductor devices, semiconductor devices, and electronic devices Granted publication date: 20220916 Pledgee: Bank of China Limited Wuxi Branch Pledgor: CSMC TECHNOLOGIES FAB2 Co.,Ltd. Registration number: Y2024980041363 |