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CN113035802A - Semiconductor packaging structure and forming method thereof - Google Patents

Semiconductor packaging structure and forming method thereof Download PDF

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Publication number
CN113035802A
CN113035802A CN202110142977.7A CN202110142977A CN113035802A CN 113035802 A CN113035802 A CN 113035802A CN 202110142977 A CN202110142977 A CN 202110142977A CN 113035802 A CN113035802 A CN 113035802A
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China
Prior art keywords
thermoelectric cooling
package
semiconductor package
package structure
thermoelectric
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CN202110142977.7A
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Chinese (zh)
Inventor
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202110142977.7A priority Critical patent/CN113035802A/en
Publication of CN113035802A publication Critical patent/CN113035802A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a semiconductor packaging structure, comprising: a package including a chip within the package; the thermoelectric refrigerating piece is positioned on the upper surface of the packaging piece and is provided with a plurality of through holes; and a plurality of connectors connecting the package and the thermoelectric cooling fins, wherein the thermoelectric cooling fins have a first portion located at a position corresponding to the chip, and the first portion has a thicker thickness or a higher density of the number of through holes than other portions. The invention aims to provide a semiconductor packaging structure and a forming method thereof, so as to improve the heat dissipation of the semiconductor packaging structure.

Description

Semiconductor packaging structure and forming method thereof
Technical Field
Embodiments of the invention relate to a semiconductor package structure and a method of forming the same.
Background
In a conventional package structure, a high temperature generated by a chip operation may cause a difference in temperature distribution at a center and an edge of the package structure, and the temperature difference may cause a problem of warpage, deformation or poor connection of the package structure, which may further cause an open circuit of the entire electronic device.
Disclosure of Invention
In view of the problems in the related art, an object of the present invention is to provide a semiconductor package structure and a method for forming the same, so as to improve the heat dissipation of the semiconductor package structure.
To achieve the above object, the present invention provides a semiconductor package structure, comprising: a package including a chip within the package; the thermoelectric refrigerating piece is positioned on the upper surface of the packaging piece and is provided with a plurality of through holes; and a plurality of connectors connecting the package and the thermoelectric cooling fins, wherein the thermoelectric cooling fins have a first portion located at a position corresponding to the chip, and the first portion has a thicker thickness or a higher density of the number of through holes than other portions.
In some embodiments, the diameter of the through-holes in the thermoelectric cooling fins is tapered towards the package.
In some embodiments, the thermoelectric cooling fins are formed by alternating stacks of dielectric layers and redistribution lines, with vias disposed between the stacked redistribution lines to electrically connect the multilayer redistribution lines, the vias including N-type material/P-type material.
In some embodiments, the number of layers of the dielectric layer and the redistribution line in the first portion is greater than the number of layers of the dielectric layer and the redistribution line in the other portion.
In some embodiments, the line width/pitch of the redistribution lines in the first portion is smaller than the line width/pitch of the redistribution lines in the other portions, and the diameter of the vias in the first portion is smaller than the diameter of the vias in the other portions.
In some embodiments, the thermoelectric cooling plate includes a cold junction and a hot junction disposed opposite the cold junction, and the cold junction is connected to the upper surface of the package by a plurality of connectors.
In some embodiments, the plurality of connectors are formed as solder or bumps.
In some embodiments, a capillary underfill encapsulating the plurality of connectors is further disposed between the package and the thermoelectric cooling plate.
In some embodiments, an adhesive material covering the plurality of connectors is further disposed between the package and the thermoelectric cooling plate.
In some embodiments, the first portion of the thermoelectric cooling fins is located directly above the chip.
In some embodiments, further comprising: and the lead is used for electrically connecting the bonding pad which is not covered by the thermoelectric refrigerating sheet at the upper surface of the packaging piece to the upper surface of the thermoelectric refrigerating sheet.
In some embodiments, the package encapsulates a plurality of chips, the first portion covers the plurality of chips, and the other portions are located on both sides of the first portion.
In some embodiments, the thermoelectric cooling fins comprise a first thermoelectric cooling fin overlying an upper surface of the enclosure and a second thermoelectric cooling fin positioned on the first thermoelectric cooling fin, the second thermoelectric cooling fin positioned directly above the chip in the elevation direction, the first portion comprising the second thermoelectric cooling fin.
In some embodiments, the thermoelectric cooling fins include a third thermoelectric cooling fin, a fourth thermoelectric cooling fin, and a second thermoelectric cooling fin on the third thermoelectric cooling fin, the second thermoelectric cooling fin, and the first portion includes the second thermoelectric cooling fin.
In some embodiments, there is provided a method of forming a semiconductor package structure, comprising: providing a packaging piece, and packaging the chip in the packaging piece; forming a thermoelectric refrigerating sheet with a plurality of connecting pieces on the lower surface; and connecting a plurality of connectors to the upper surface of the package, wherein the thermoelectric cooling plate has a first portion at the position corresponding to the chip, and the first portion has a thicker thickness or a higher density of through holes than other portions.
In some embodiments, the diameter of the through-hole in the thermoelectric cooling fin is formed to be gradually reduced from top to bottom.
In some embodiments, the diameter of the through hole is formed to gradually decrease toward the cold junction surface of the thermoelectric cooling plate and gradually increase toward the hot junction surface of the thermoelectric cooling plate.
In some embodiments, the cold junction is connected to the upper surface of the package by a plurality of connections.
In some embodiments, the step of forming the thermoelectric cooling fins with the through holes comprises: forming redistribution lines on the carrier; forming a dielectric layer on the redistribution line; forming a first opening in the dielectric layer exposing the redistribution line; filling an N-type material in the first opening; forming a second opening in the dielectric layer exposing the redistribution line; and filling the second opening with a P-type material.
In some embodiments, the step of forming the redistribution line comprises: forming a mask layer on a carrier; removing a portion of the mask layer to form a third opening; forming a metal material at the bottom of the third opening; the remaining portions of the mask layer are removed to form redistribution lines comprising the metal material.
Drawings
Fig. 1 to 30 illustrate sequential formation processes of a semiconductor package structure according to an embodiment of the present application.
Fig. 31 to 41 show schematic structural views of semiconductor package structures according to different embodiments of the present application.
Detailed Description
In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.
Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.
Since the temperature of the heat source is higher than that of other positions, the heat source and other positions will have different temperatures when the system is loaded. The use of the uniform-thickness TEG on the surface of the package for heat dissipation still causes warpage, deformation and even poor connection of the connectors, and finally causes open circuit, which is more obvious as the size of the package is larger or/and the load is higher. TEGs are typically made using soft board materials, are relatively weak, have a relatively limited ability to withstand stress equilibrium alone, and therefore can only be used to encase refrigeration materials.
The semiconductor package structure and the method of forming the same of the present application are explained in detail below with reference to the accompanying drawings.
Referring to fig. 1, a first seed layer 12 is formed on a carrier 10. In an embodiment, the first seed layer 12 may be formed by a Physical Vapor Deposition (PVD) process.
Referring to fig. 2, a first mask layer 20 is formed on the first seed layer 12, the first mask layer 20 may include a Photoresist (PR) material, and an exposure process 21 is performed to cure the first mask layer 20.
Referring to fig. 3, the first mask layer 20 is patterned and a first metal layer 30 is formed in the patterned first mask layer 20.
Referring to fig. 4, the patterned first mask layer 20 is removed, and the first seed layer 20 is etched using the first metal layer 30 as a mask so that the first seed layer 20 has the same pattern as the first metal layer 30.
Referring to fig. 5, a semiconductor device 52 is placed on the adjacent first metal layer 30 using a jig 50, and a vacuum state is maintained between the jig 50 and the semiconductor device 52 during the clamping.
Referring to fig. 6, a first dielectric layer 60 is formed overlying the first metal layer 30 and the first seed layer 20. In an embodiment, the first dielectric layer 60 may include a Polyamide (PA) material, and the first dielectric layer 60 is subjected to an exposure process 61 for curing.
Referring to fig. 7, first and second openings 71 and 72 are formed in the first dielectric layer 60 to expose the first metal layer 30.
Referring to fig. 8, a first thermoelectric material 84 is filled into the first opening 71 using a first mask 80 and a pressing tool 82, wherein the first mask 80 covers the second opening 72, and the opening of the first mask 80 is aligned with the first opening 71.
Referring to fig. 9, a second thermoelectric material 94 is filled into the second opening 72 using a second mask 90 and a pressing tool 92, wherein the second mask 90 covers the first thermoelectric material 84 and the openings of the second mask 90 are aligned with the second opening 72. In an embodiment, the first thermoelectric material 124 is a P-type material and the second thermoelectric material 125 is an N-type material to form an N-type electrode and a P-type electrode, respectively. In embodiments, the N-type and P-type electrodes are regular polygons (e.g., squares or equilateral triangles), circles, or irregular shapes in plan view. In an embodiment, the N-type electrode and the P-type electrode are connected in series or in parallel. In other embodiments, the first thermoelectric material 124 is an N-type material and the second thermoelectric material 125 is a P-type material. When two conductors or semiconductors (N-type or P-type) with different types have a temperature difference (Δ T) between two junctions, if the two junctions are closed loops, current will be generated, and if the two junctions are open loops, potential difference (V) will be generated, which is Seebeck Effect (Seebeck Effect) in thermoelectric Effect; when a voltage is applied to a closed loop formed by two conductors or semiconductors (N-type or P-type) with different types to generate current, a phenomenon that one end absorbs heat and the other end releases heat is generated at two joints, namely a Peltier Effect (Peltier Effect) in the thermoelectric Effect, and the Peltier Effect can be generated at the interface of two different materials or between different phase boundaries of a multiphase material or within different concentration gradient ranges of a heterogeneous material; when current flows through a single conductor or semiconductor with non-uniform temperature, certain heat (called Thomson heat) is absorbed or released in addition to irreversible Joule heat; conversely, when the temperatures of two ends of a single conductor or semiconductor are different, a potential difference (Emf) is formed across the material, which is the Thomson Effect. In one embodiment, the P-type material may be SiGe, SiGe/GaP, CeFe3.5Co0.5Sb12、Zn4Sb3、Bi0.25Sb0.75Te3And the like. The N-type material can be PbTe, SiGe, Bi2Te2.7Se0.3、CoSb3、Zn4Sb3And the like.
Referring to fig. 10, a second seed layer 100 is formed on the first dielectric layer 60. In an embodiment, the second seed layer 100 may be formed by a Physical Vapor Deposition (PVD) process. In an embodiment, the second seed layer 100 includes copper and titanium.
Referring to fig. 11, a third mask layer 110 is formed on the second seed layer 100, the third mask layer 110 may include a Photoresist (PR) material, and an exposure process 111 is performed to cure the third mask layer 110.
Referring to fig. 12, the third mask layer 110 is patterned to expose the second seed layer 100. And a second metal layer 120 is formed on the exposed second seed layer 100.
Referring to fig. 13, the patterned third mask layer 110 is removed, and the second seed layer 100 is etched using the second metal layer 120 as a mask so that the second seed layer 100 has the same pattern as the second metal layer 120.
Referring to fig. 14, a second dielectric layer 140 is formed to cover the second seed layer 100 and the second metal layer 120. In an embodiment, the second dielectric layer 140 may include a Polyamide (PA) material, and the heating process 141 is performed on the second dielectric layer 140.
Referring to fig. 15, a third sub-layer 150 is formed on the second dielectric layer 140. In an embodiment, the third sub-layer 150 may be formed by a Physical Vapor Deposition (PVD) process.
Referring to fig. 16, a fourth mask layer 160 is formed on the third sub-layer 150, the fourth mask layer 160 may include a Photoresist (PR) material, and an exposure process 161 is performed to cure the fourth mask layer 160.
Referring to fig. 17, the fourth mask layer 160 is patterned to expose the third sub-layer 150. And a third metal layer 170 is formed on the exposed third sub-layer 150.
Referring to fig. 18, the patterned fourth mask layer 160 is removed, and the third sub-layer 150 is etched using the third metal layer 170 as a mask so that the third sub-layer 150 has the same pattern as the third metal layer 170.
Referring to fig. 19, a third dielectric layer 190 is formed overlying the third metal layer 170. In an embodiment, the third dielectric layer 190 may include a Polyamide (PA) material, and the exposure process 191 is performed on the third dielectric layer 190 to cure.
Referring to fig. 20, a third opening 201 and a fourth opening 202 are formed in the third dielectric layer 190 adjacent to each other in sequence to expose the third metal layer 170.
Referring to fig. 21, the first thermoelectric material 84 is filled into the third opening 201 using a fifth mask 210 and a pressing tool 212, wherein the fifth mask 210 covers the fourth opening 202, and the opening of the fifth mask 210 is aligned with the third opening 201.
Referring to fig. 22, the second thermoelectric material 94 is filled into the fourth opening 202 using a sixth mask 220 and a pressing tool 222, wherein the sixth mask 220 covers the first thermoelectric material 84, and the openings of the sixth mask 220 are aligned with the fourth opening 202. In an embodiment, the first thermoelectric material 124 is a P-type material and the second thermoelectric material 125 is an N-type material. In other embodiments, the first thermoelectric material 124 is an N-type material and the second thermoelectric material 125 is a P-type material.
Referring to fig. 23, an opening through the third dielectric layer 190 and the second dielectric layer 140 is etched, and a fourth sub-layer 230 is formed in the opening and on the third dielectric layer 190. In an embodiment, the fourth sub-layer 230 may be formed by a Physical Vapor Deposition (PVD) process.
Referring to fig. 24, a seventh mask layer 240 is formed on the fourth sub-layer 230, the seventh mask layer 240 may include a Photoresist (PR) material, and an exposure process 241 is performed to cure the seventh mask layer 240.
Referring to fig. 25, the seventh mask layer 240 is patterned to expose the fourth sub-layer 230. And a fourth metal layer 250 is formed on the exposed fourth sub-layer 230.
Referring to fig. 26, the patterned seventh mask layer 240 is removed, and the fourth sub-layer 230 is etched using the fourth metal layer 250 as a mask so that the fourth sub-layer 230 has the same pattern as the fourth metal layer 250.
Referring to fig. 27, a fourth dielectric layer 270 is formed covering the fourth metal layer 250. In an embodiment, the fourth dielectric layer 270 may include a Polyamide (PA) material, and the exposure process 271 is performed on the fourth dielectric layer 270 for curing.
Referring to fig. 28 to 29, the carrier 10 is removed to form the first thermoelectric cooling plate 280, and a plurality of connection members 290 are formed on the exposed first seed layer 12 of the first thermoelectric cooling plate 280. In an embodiment, the connection 290 is formed as a solder ball.
Referring to fig. 30, a first thermoelectric cooling plate 280 is placed on the package 312 and a second thermoelectric cooling plate 314 is placed on the first thermoelectric cooling plate 280. The second thermoelectric cooling fins 314 are aligned with the chip 316 of the package 312 to form the semiconductor package structure 300 of the present application.
Referring to fig. 31, in contrast to fig. 29, in an embodiment, the connection 290 is formed as a micro bump.
Referring to fig. 32, fibers 320 are also formed in the first dielectric layer 60 and the second dielectric layer 140. In embodiments that include and/or do not include fibers 320, the first dielectric layer 60 and the second dielectric layer 140 may be organic dielectrics, such as Polyimide (PI), epoxy, Polybenzoxazole (PBO), flame retardant class 4 materials (FR4), pre-cured resins (PP), Ajinomotobuild-up film (ABF), bismaleimide triazine resin (BT), photosensitive and/or non-photosensitive liquids. In embodiments that do not include fibers 320, the first 60 and second 140 dielectric layers may be inorganic electrolytes, such as silicon, glass, ceramic, oxides (e.g., SiOx, TaOx), nitrides (e.g., SiNx).
Referring to fig. 33, Capillary Underfill (CUF)330 is also filled around the connection 290.
Referring to fig. 34, the first thermoelectric cooling plate 280 and the package 312 are additionally connected by a lead 340.
Referring to fig. 35, the first thermoelectric cooling plate 280 includes a plurality of cells.
Referring to fig. 36, the connection 290 of fig. 36 is for input only, as compared to the connection 290 of fig. 29, which includes connections for input and output.
Referring to fig. 37, the connection 290 of fig. 37 is for output only, as compared to the connection 290 of fig. 29, which includes connections for input and output.
Referring to fig. 38, the chip 316 includes a plurality arranged side by side. Referring to fig. 39, the chip 316 is formed to occupy a wider area in the package 312.
Referring to fig. 40, the thermoelectric cooling fins include third and fourth thermoelectric cooling fins 390 and 392 disposed side by side covering the upper surface of the package 31, and a second thermoelectric cooling fin 314 on the third and fourth thermoelectric cooling fins 390 and 392.
Referring to fig. 41, a balance film 400 is further formed on the first thermoelectric cooling plate 280 for further reducing the possibility of the generation of warpage. The balancing film 400 may include one or more of copper, nickel, titanium, tungsten, or platinum alloys and/or non-metals (e.g., PI, ABF, epoxy, or solder resist ink).
The invention discloses a packaging structure using Thermoelectric refrigerating sheet for heat dissipation and a manufacturing method thereof, wherein a Thermoelectric refrigerating sheet (TEG) which is manufactured by the principle that direct current generates temperature difference and is coated by a soft board material is mainly arranged outside the relative position of a heating source (such as a power management chip) of the packaging structure so as to effectively bring high temperature generated during the operation of the packaging structure to the outside of the packaging structure, effectively avoid the problems of warping, deformation, poor joint and the like caused by the high temperature, and avoid delamination caused by the thermal expansion phenomenon generated by the heating of the soft board material. The TEG manufactured by the soft board can be attached to any curved surface, and if the soft board is attached to the surface of the packaging structure, the tensile stress of the packaging structure can be effectively resisted due to the surface film effect, so that the warping phenomenon is reduced. In an embodiment, the heat Dissipation Efficiency (Thermal Dissipation Efficiency) of the chip raised from room temperature to 400 ℃ is tested, and the heat Dissipation Efficiency of the package structure provided with the thermoelectric cooling plate is 1.6-4 times of that of a common package body and is 5 times of that of a single IC chip.
The present invention provides a semiconductor package structure 300, comprising: a package 312 including a chip 316 within the package 312; thermoelectric cooling fins (280, 314, etc.) located on the upper surface of the package 312 and provided with a plurality of through holes (the portions of the fourth sub-layer 230 and the fourth metal layer 250 extending in the third dielectric layer 190 and the second dielectric layer 140); and a plurality of connectors 290 connecting the package 312 and the thermoelectric cooling fins, wherein the thermoelectric cooling fins have a first portion (for example, a portion of all the thermoelectric cooling fins projected upward from the chip 312) at a position corresponding to the chip 312, and the first portion has a thicker thickness or a higher density of the number of through holes than other portions. In some embodiments, the diameter of the through-holes in the thermoelectric cooling fins tapers down toward the enclosure 312. In some embodiments, the thermoelectric cooling fins 312 are formed by alternating stacks of dielectric layers (60, 140, 190) and redistribution lines (laterally extending portions of seed layers and metal layers in the dielectric layers), with vias disposed between the stacked redistribution lines to electrically connect the multilayer redistribution lines, the vias including N-type material/P-type material. In some embodiments, the number of layers of the dielectric layer and the redistribution line in the first portion is greater than the number of layers of the dielectric layer and the redistribution line in the other portion. In some embodiments, the line width/pitch of the redistribution lines in the first portion is smaller than the line width/pitch of the redistribution lines in the other portions, and the diameter of the vias in the first portion is smaller than the diameter of the vias in the other portions. In some embodiments, the thermoelectric cooling fins include a cold side junction and a hot side junction disposed opposite the cold side junction, the cold side junction being connected to the upper surface of the package 312 by a plurality of connectors 290. In some embodiments, the plurality of connections 290 are formed as solder or bumps. In some embodiments, a capillary underfill 330 covering the plurality of connectors 290 is further disposed between the package 312 and the thermoelectric cooling fins. In some embodiments, an adhesive material covering the plurality of connectors is also disposed between the package 312 and the thermoelectric cooling fins. In some embodiments, the first portion of the thermoelectric cooling fins is located directly above the chip. In some embodiments, further comprising: and a wire 340 electrically connecting a pad at the upper surface of the package 312, which is not covered by the thermoelectric cooling fin, to the upper surface of the thermoelectric cooling fin 280. In some embodiments, the package 312 encapsulates a plurality of chips 316, with a first portion covering the plurality of chips and other portions on both sides of the first portion. In some embodiments, the thermoelectric cooling fins comprise a first thermoelectric cooling fin 280 covering the upper surface of the enclosure 312 and a second thermoelectric cooling fin 314 positioned on the first thermoelectric cooling fin, the second thermoelectric cooling fin 314 being positioned directly above the chip 316 in the elevation direction, the first portion comprising the second thermoelectric cooling fin 314. In some embodiments, the thermoelectric cooling fins include a third thermoelectric cooling fin 390, a fourth thermoelectric cooling fin 392 and a second thermoelectric cooling fin 280 on the third thermoelectric cooling fin 390, the fourth thermoelectric cooling fin 392 disposed side by side covering the upper surface of the package, the first portion including the second thermoelectric cooling fin 280.
In some embodiments, there is provided a method of forming a semiconductor package structure, comprising: providing a package 312, and packaging the chip 316 in the package 312; forming a thermoelectric cooling plate having a plurality of connecting members 290 on a lower surface thereof; a plurality of connectors 290 are connected to the upper surface of the package 312, wherein the thermoelectric cooling fins have a first portion at a position corresponding to the chip 316, the first portion having a thicker thickness or a higher density of the number of through holes than other portions. In some embodiments, the diameter of the through-holes in the thermoelectric cooling fins 316 is formed to gradually decrease from top to bottom. In some embodiments, the diameter of the through hole is formed to gradually decrease toward the cold junction surface of the thermoelectric cooling plate and gradually increase toward the hot junction surface of the thermoelectric cooling plate. In some embodiments, the cold junction is connected to the upper surface of the package by a plurality of connections. In some embodiments, the step of forming the thermoelectric cooling fins with the through holes comprises: forming redistribution lines on the carrier 10; forming a dielectric layer on the redistribution line; forming a first opening in the dielectric layer exposing the redistribution line; filling an N-type material in the first opening; forming a second opening in the dielectric layer exposing the redistribution line; and filling the second opening with a P-type material. In some embodiments, the step of forming the redistribution line comprises: forming a mask layer on a carrier; removing a portion of the mask layer to form a third opening; forming a metal material at the bottom of the third opening; the remaining portions of the mask layer are removed to form redistribution lines comprising the metal material.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A semiconductor package structure, comprising:
a package including a chip within the package;
the thermoelectric refrigerating piece is positioned on the upper surface of the packaging piece and is provided with a plurality of through holes; and
a plurality of connectors connecting the package and the thermoelectric cooling plate,
wherein the thermoelectric cooling plate has a first portion at a position corresponding to the chip, the first portion having a greater thickness or a higher density of the number of through holes than other portions.
2. The semiconductor package structure of claim 1, wherein the diameter of the through-hole in the thermoelectric cooling fin is tapered toward the package.
3. The semiconductor package structure of claim 1, wherein the thermoelectric cooling fins are stacked with dielectric layers and redistribution lines alternating, wherein vias are disposed between the stacked redistribution lines to electrically connect the redistribution lines in multiple layers, wherein the vias comprise N-type material/P-type material.
4. The semiconductor package structure of claim 3, wherein a number of layers of the dielectric layer and the redistribution line in the first portion is greater than a number of layers of the dielectric layer and the redistribution line in the other portion.
5. The semiconductor package structure of claim 3, wherein a line width/spacing of the redistribution lines in the first portion is smaller than a line width/spacing of the redistribution lines in the other portions, and wherein a diameter of the vias in the first portion is smaller than a diameter of the vias in the other portions.
6. The semiconductor package structure of claim 1, wherein the thermoelectric cooling fins comprise a cold junction and a hot junction disposed opposite the cold junction, the cold junction being connected to the upper surface of the package by the plurality of connectors.
7. The semiconductor package structure of claim 1, wherein a capillary underfill encapsulating the plurality of connectors is further disposed between the package and the thermoelectric cooling plate.
8. The semiconductor package structure of claim 1, wherein an adhesive material covering the plurality of connectors is further disposed between the package and the thermoelectric cooling fins.
9. The semiconductor package structure of claim 1, further comprising:
a lead electrically connecting a pad at the upper surface of the package not covered by the thermoelectric cooling fins to an upper surface of the thermoelectric cooling fins.
10. The semiconductor package structure of claim 1, wherein the package is packaged with a plurality of chips, the first portion covers the plurality of chips, and the other portions are located on both sides of the first portion.
CN202110142977.7A 2021-02-02 2021-02-02 Semiconductor packaging structure and forming method thereof Pending CN113035802A (en)

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CN202110142977.7A CN113035802A (en) 2021-02-02 2021-02-02 Semiconductor packaging structure and forming method thereof

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